2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
11 * Johan Lorensson (lateralusx.github@gmail.com)
13 * (C) 2003 Ximian, Inc.
14 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
15 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
16 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
26 #include <mono/metadata/abi-details.h>
27 #include <mono/metadata/appdomain.h>
28 #include <mono/metadata/debug-helpers.h>
29 #include <mono/metadata/threads.h>
30 #include <mono/metadata/profiler-private.h>
31 #include <mono/metadata/mono-debug.h>
32 #include <mono/metadata/gc-internals.h>
33 #include <mono/utils/mono-math.h>
34 #include <mono/utils/mono-mmap.h>
35 #include <mono/utils/mono-memory-model.h>
36 #include <mono/utils/mono-tls.h>
37 #include <mono/utils/mono-hwcap.h>
38 #include <mono/utils/mono-threads.h>
42 #include "mini-amd64.h"
43 #include "cpu-amd64.h"
44 #include "debugger-agent.h"
48 static gboolean optimize_for_xen = TRUE;
50 #define optimize_for_xen 0
53 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
55 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
57 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
60 /* Under windows, the calling convention is never stdcall */
61 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
63 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
66 /* This mutex protects architecture specific caches */
67 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
68 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
69 static mono_mutex_t mini_arch_mutex;
71 /* The single step trampoline */
72 static gpointer ss_trampoline;
74 /* The breakpoint trampoline */
75 static gpointer bp_trampoline;
77 /* Offset between fp and the first argument in the callee */
78 #define ARGS_OFFSET 16
79 #define GP_SCRATCH_REG AMD64_R11
82 * AMD64 register usage:
83 * - callee saved registers are used for global register allocation
84 * - %r11 is used for materializing 64 bit constants in opcodes
85 * - the rest is used for local allocation
89 * Floating point comparison results:
99 mono_arch_regname (int reg)
102 case AMD64_RAX: return "%rax";
103 case AMD64_RBX: return "%rbx";
104 case AMD64_RCX: return "%rcx";
105 case AMD64_RDX: return "%rdx";
106 case AMD64_RSP: return "%rsp";
107 case AMD64_RBP: return "%rbp";
108 case AMD64_RDI: return "%rdi";
109 case AMD64_RSI: return "%rsi";
110 case AMD64_R8: return "%r8";
111 case AMD64_R9: return "%r9";
112 case AMD64_R10: return "%r10";
113 case AMD64_R11: return "%r11";
114 case AMD64_R12: return "%r12";
115 case AMD64_R13: return "%r13";
116 case AMD64_R14: return "%r14";
117 case AMD64_R15: return "%r15";
122 static const char * packed_xmmregs [] = {
123 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
124 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
127 static const char * single_xmmregs [] = {
128 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
129 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
133 mono_arch_fregname (int reg)
135 if (reg < AMD64_XMM_NREG)
136 return single_xmmregs [reg];
142 mono_arch_xregname (int reg)
144 if (reg < AMD64_XMM_NREG)
145 return packed_xmmregs [reg];
154 return mono_debug_count ();
160 static inline gboolean
161 amd64_is_near_call (guint8 *code)
164 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
167 return code [0] == 0xe8;
170 static inline gboolean
171 amd64_use_imm32 (gint64 val)
173 if (mini_get_debug_options()->single_imm_size)
176 return amd64_is_imm32 (val);
180 amd64_patch (unsigned char* code, gpointer target)
185 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
190 if ((code [0] & 0xf8) == 0xb8) {
191 /* amd64_set_reg_template */
192 *(guint64*)(code + 1) = (guint64)target;
194 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
195 /* mov 0(%rip), %dreg */
196 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
198 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
199 /* call *<OFFSET>(%rip) */
200 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
202 else if (code [0] == 0xe8) {
204 gint64 disp = (guint8*)target - (guint8*)code;
205 g_assert (amd64_is_imm32 (disp));
206 x86_patch (code, (unsigned char*)target);
209 x86_patch (code, (unsigned char*)target);
213 mono_amd64_patch (unsigned char* code, gpointer target)
215 amd64_patch (code, target);
218 #define DEBUG(a) if (cfg->verbose_level > 1) a
221 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
223 ainfo->offset = *stack_size;
225 if (*gr >= PARAM_REGS) {
226 ainfo->storage = ArgOnStack;
227 ainfo->arg_size = sizeof (mgreg_t);
228 /* Since the same stack slot size is used for all arg */
229 /* types, it needs to be big enough to hold them all */
230 (*stack_size) += sizeof(mgreg_t);
233 ainfo->storage = ArgInIReg;
234 ainfo->reg = param_regs [*gr];
240 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
242 ainfo->offset = *stack_size;
244 if (*gr >= FLOAT_PARAM_REGS) {
245 ainfo->storage = ArgOnStack;
246 ainfo->arg_size = sizeof (mgreg_t);
247 /* Since the same stack slot size is used for both float */
248 /* types, it needs to be big enough to hold them both */
249 (*stack_size) += sizeof(mgreg_t);
252 /* A double register */
254 ainfo->storage = ArgInDoubleSSEReg;
256 ainfo->storage = ArgInFloatSSEReg;
262 typedef enum ArgumentClass {
270 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
272 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
275 ptype = mini_get_underlying_type (type);
276 switch (ptype->type) {
285 case MONO_TYPE_STRING:
286 case MONO_TYPE_OBJECT:
287 case MONO_TYPE_CLASS:
288 case MONO_TYPE_SZARRAY:
290 case MONO_TYPE_FNPTR:
291 case MONO_TYPE_ARRAY:
294 class2 = ARG_CLASS_INTEGER;
299 class2 = ARG_CLASS_INTEGER;
301 class2 = ARG_CLASS_SSE;
305 case MONO_TYPE_TYPEDBYREF:
306 g_assert_not_reached ();
308 case MONO_TYPE_GENERICINST:
309 if (!mono_type_generic_inst_is_valuetype (ptype)) {
310 class2 = ARG_CLASS_INTEGER;
314 case MONO_TYPE_VALUETYPE: {
315 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
318 for (i = 0; i < info->num_fields; ++i) {
320 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
325 g_assert_not_reached ();
329 if (class1 == class2)
331 else if (class1 == ARG_CLASS_NO_CLASS)
333 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
334 class1 = ARG_CLASS_MEMORY;
335 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
336 class1 = ARG_CLASS_INTEGER;
338 class1 = ARG_CLASS_SSE;
349 * collect_field_info_nested:
351 * Collect field info from KLASS recursively into FIELDS.
354 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
356 MonoMarshalType *info;
360 info = mono_marshal_load_type_info (klass);
362 for (i = 0; i < info->num_fields; ++i) {
363 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
364 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
369 f.type = info->fields [i].field->type;
370 f.size = mono_marshal_type_size (info->fields [i].field->type,
371 info->fields [i].mspec,
372 &align, TRUE, unicode);
373 f.offset = offset + info->fields [i].offset;
374 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
375 /* This can happen with .pack directives eg. 'fixed' arrays */
376 if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
377 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
378 g_array_append_val (fields_array, f);
379 while (f.size + f.offset < info->native_size) {
381 g_array_append_val (fields_array, f);
384 f.size = info->native_size - f.offset;
385 g_array_append_val (fields_array, f);
388 g_array_append_val (fields_array, f);
394 MonoClassField *field;
397 while ((field = mono_class_get_fields (klass, &iter))) {
398 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
400 if (MONO_TYPE_ISSTRUCT (field->type)) {
401 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
406 f.type = field->type;
407 f.size = mono_type_size (field->type, &align);
408 f.offset = field->offset - sizeof (MonoObject) + offset;
410 g_array_append_val (fields_array, f);
418 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
419 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
422 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
424 gboolean result = FALSE;
426 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
427 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
429 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
430 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
431 arg_info->pair_size [0] = 0;
432 arg_info->pair_size [1] = 0;
435 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
436 /* Pass parameter in integer register. */
437 arg_info->pair_storage [0] = ArgInIReg;
438 arg_info->pair_regs [0] = int_regs [*current_int_reg];
439 (*current_int_reg) ++;
441 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
442 /* Pass parameter in float register. */
443 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
444 arg_info->pair_regs [0] = float_regs [*current_float_reg];
445 (*current_float_reg) ++;
449 if (result == TRUE) {
450 arg_info->pair_size [0] = arg_size;
457 static inline gboolean
458 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
460 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
463 static inline gboolean
464 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
466 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
470 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
471 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
473 /* Windows x64 value type ABI.
475 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
477 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
478 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
479 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
480 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
482 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
484 * Integers/Float types smaller than or equal to 8 bytes
485 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
486 * Properly sized struct/unions (1,2,4,8)
487 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
488 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
489 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
492 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
496 /* Parameter cases. */
497 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
498 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
500 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
501 arg_info->storage = ArgValuetypeInReg;
502 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
503 /* No more registers, fallback passing parameter on stack as value. */
504 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
506 /* Passing value directly on stack, so use size of value. */
507 arg_info->storage = ArgOnStack;
508 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
509 arg_info->offset = *stack_size;
510 arg_info->arg_size = arg_size;
511 *stack_size += arg_size;
514 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
515 arg_info->storage = ArgValuetypeAddrInIReg;
516 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
517 /* No more registers, fallback passing address to parameter on stack. */
518 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
520 /* Passing an address to value on stack, so use size of register as argument size. */
521 arg_info->storage = ArgValuetypeAddrOnStack;
522 arg_size = sizeof (mgreg_t);
523 arg_info->offset = *stack_size;
524 arg_info->arg_size = arg_size;
525 *stack_size += arg_size;
529 /* Return value cases. */
530 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
531 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
533 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
534 arg_info->storage = ArgValuetypeInReg;
535 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
537 /* Only RAX/XMM0 should be used to return valuetype. */
538 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
540 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
541 arg_info->storage = ArgValuetypeAddrInIReg;
542 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
544 /* Only RAX should be used to return valuetype address. */
545 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
547 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
548 arg_info->offset = *stack_size;
549 *stack_size += arg_size;
555 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
558 *arg_class = ARG_CLASS_NO_CLASS;
560 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
563 /* Calculate argument class type and size of marshalled type. */
564 MonoMarshalType *info = mono_marshal_load_type_info (klass);
565 *arg_size = info->native_size;
567 /* Calculate argument class type and size of managed type. */
568 *arg_size = mono_class_value_size (klass, NULL);
571 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
572 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
574 if (*arg_class == ARG_CLASS_MEMORY) {
575 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
576 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
580 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
581 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
582 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
583 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
584 * it must be represented in call and cannot be dropped.
586 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
587 arg_info->pass_empty_struct = TRUE;
588 *arg_size = SIZEOF_REGISTER;
589 *arg_class = ARG_CLASS_INTEGER;
592 assert (*arg_class != ARG_CLASS_NO_CLASS);
596 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
597 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
599 guint32 arg_size = SIZEOF_REGISTER;
600 MonoClass *klass = NULL;
601 ArgumentClass arg_class;
603 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
605 klass = mono_class_from_mono_type (type);
606 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
608 /* Only drop value type if its not an empty struct as input that must be represented in call */
609 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
610 arg_info->storage = ArgValuetypeInReg;
611 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
613 /* Alocate storage for value type. */
614 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
618 #endif /* TARGET_WIN32 */
621 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
623 guint32 *gr, guint32 *fr, guint32 *stack_size)
626 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
628 guint32 size, quad, nquads, i, nfields;
629 /* Keep track of the size used in each quad so we can */
630 /* use the right size when copying args/return vars. */
631 guint32 quadsize [2] = {8, 8};
632 ArgumentClass args [2];
633 StructFieldInfo *fields = NULL;
634 GArray *fields_array;
636 gboolean pass_on_stack = FALSE;
639 klass = mono_class_from_mono_type (type);
640 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
642 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
643 /* We pass and return vtypes of size 8 in a register */
644 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
645 pass_on_stack = TRUE;
648 /* If this struct can't be split up naturally into 8-byte */
649 /* chunks (registers), pass it on the stack. */
651 MonoMarshalType *info = mono_marshal_load_type_info (klass);
653 struct_size = info->native_size;
655 struct_size = mono_class_value_size (klass, NULL);
658 * Collect field information recursively to be able to
659 * handle nested structures.
661 fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
662 collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
663 fields = (StructFieldInfo*)fields_array->data;
664 nfields = fields_array->len;
666 for (i = 0; i < nfields; ++i) {
667 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
668 pass_on_stack = TRUE;
674 ainfo->storage = ArgValuetypeInReg;
675 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
680 /* Allways pass in memory */
681 ainfo->offset = *stack_size;
682 *stack_size += ALIGN_TO (size, 8);
683 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
685 ainfo->arg_size = ALIGN_TO (size, 8);
687 g_array_free (fields_array, TRUE);
697 int n = mono_class_value_size (klass, NULL);
699 quadsize [0] = n >= 8 ? 8 : n;
700 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
702 /* Always pass in 1 or 2 integer registers */
703 args [0] = ARG_CLASS_INTEGER;
704 args [1] = ARG_CLASS_INTEGER;
705 /* Only the simplest cases are supported */
706 if (is_return && nquads != 1) {
707 args [0] = ARG_CLASS_MEMORY;
708 args [1] = ARG_CLASS_MEMORY;
712 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
713 * The X87 and SSEUP stuff is left out since there are no such types in
717 ainfo->storage = ArgValuetypeInReg;
718 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
722 if (struct_size > 16) {
723 ainfo->offset = *stack_size;
724 *stack_size += ALIGN_TO (struct_size, 8);
725 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
727 ainfo->arg_size = ALIGN_TO (struct_size, 8);
729 g_array_free (fields_array, TRUE);
733 args [0] = ARG_CLASS_NO_CLASS;
734 args [1] = ARG_CLASS_NO_CLASS;
735 for (quad = 0; quad < nquads; ++quad) {
736 ArgumentClass class1;
739 class1 = ARG_CLASS_MEMORY;
741 class1 = ARG_CLASS_NO_CLASS;
742 for (i = 0; i < nfields; ++i) {
743 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
744 /* Unaligned field */
748 /* Skip fields in other quad */
749 if ((quad == 0) && (fields [i].offset >= 8))
751 if ((quad == 1) && (fields [i].offset < 8))
754 /* How far into this quad this data extends.*/
755 /* (8 is size of quad) */
756 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
758 class1 = merge_argument_class_from_type (fields [i].type, class1);
760 /* Empty structs have a nonzero size, causing this assert to be hit */
762 g_assert (class1 != ARG_CLASS_NO_CLASS);
763 args [quad] = class1;
767 g_array_free (fields_array, TRUE);
769 /* Post merger cleanup */
770 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
771 args [0] = args [1] = ARG_CLASS_MEMORY;
773 /* Allocate registers */
778 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
780 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
783 ainfo->storage = ArgValuetypeInReg;
784 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
785 g_assert (quadsize [0] <= 8);
786 g_assert (quadsize [1] <= 8);
787 ainfo->pair_size [0] = quadsize [0];
788 ainfo->pair_size [1] = quadsize [1];
789 ainfo->nregs = nquads;
790 for (quad = 0; quad < nquads; ++quad) {
791 switch (args [quad]) {
792 case ARG_CLASS_INTEGER:
793 if (*gr >= PARAM_REGS)
794 args [quad] = ARG_CLASS_MEMORY;
796 ainfo->pair_storage [quad] = ArgInIReg;
798 ainfo->pair_regs [quad] = return_regs [*gr];
800 ainfo->pair_regs [quad] = param_regs [*gr];
805 if (*fr >= FLOAT_PARAM_REGS)
806 args [quad] = ARG_CLASS_MEMORY;
808 if (quadsize[quad] <= 4)
809 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
810 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
811 ainfo->pair_regs [quad] = *fr;
815 case ARG_CLASS_MEMORY:
817 case ARG_CLASS_NO_CLASS:
820 g_assert_not_reached ();
824 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
826 /* Revert possible register assignments */
830 ainfo->offset = *stack_size;
832 arg_size = ALIGN_TO (struct_size, 8);
834 arg_size = nquads * sizeof(mgreg_t);
835 *stack_size += arg_size;
836 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
838 ainfo->arg_size = arg_size;
841 #endif /* !TARGET_WIN32 */
847 * Obtain information about a call according to the calling convention.
848 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
849 * Draft Version 0.23" document for more information.
850 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
851 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
854 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
856 guint32 i, gr, fr, pstart;
858 int n = sig->hasthis + sig->param_count;
859 guint32 stack_size = 0;
861 gboolean is_pinvoke = sig->pinvoke;
864 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
866 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
869 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
875 /* Reserve space where the callee can save the argument registers */
876 stack_size = 4 * sizeof (mgreg_t);
880 ret_type = mini_get_underlying_type (sig->ret);
881 switch (ret_type->type) {
891 case MONO_TYPE_FNPTR:
892 case MONO_TYPE_CLASS:
893 case MONO_TYPE_OBJECT:
894 case MONO_TYPE_SZARRAY:
895 case MONO_TYPE_ARRAY:
896 case MONO_TYPE_STRING:
897 cinfo->ret.storage = ArgInIReg;
898 cinfo->ret.reg = AMD64_RAX;
902 cinfo->ret.storage = ArgInIReg;
903 cinfo->ret.reg = AMD64_RAX;
906 cinfo->ret.storage = ArgInFloatSSEReg;
907 cinfo->ret.reg = AMD64_XMM0;
910 cinfo->ret.storage = ArgInDoubleSSEReg;
911 cinfo->ret.reg = AMD64_XMM0;
913 case MONO_TYPE_GENERICINST:
914 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
915 cinfo->ret.storage = ArgInIReg;
916 cinfo->ret.reg = AMD64_RAX;
919 if (mini_is_gsharedvt_type (ret_type)) {
920 cinfo->ret.storage = ArgGsharedvtVariableInReg;
924 case MONO_TYPE_VALUETYPE:
925 case MONO_TYPE_TYPEDBYREF: {
926 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
928 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
929 g_assert (cinfo->ret.storage != ArgInIReg);
934 g_assert (mini_is_gsharedvt_type (ret_type));
935 cinfo->ret.storage = ArgGsharedvtVariableInReg;
940 g_error ("Can't handle as return value 0x%x", ret_type->type);
945 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
946 * the first argument, allowing 'this' to be always passed in the first arg reg.
947 * Also do this if the first argument is a reference type, since virtual calls
948 * are sometimes made using calli without sig->hasthis set, like in the delegate
951 ArgStorage ret_storage = cinfo->ret.storage;
952 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
954 add_general (&gr, &stack_size, cinfo->args + 0);
956 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
959 add_general (&gr, &stack_size, &cinfo->ret);
960 cinfo->ret.storage = ret_storage;
961 cinfo->vret_arg_index = 1;
965 add_general (&gr, &stack_size, cinfo->args + 0);
967 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
968 add_general (&gr, &stack_size, &cinfo->ret);
969 cinfo->ret.storage = ret_storage;
973 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
975 fr = FLOAT_PARAM_REGS;
977 /* Emit the signature cookie just before the implicit arguments */
978 add_general (&gr, &stack_size, &cinfo->sig_cookie);
981 for (i = pstart; i < sig->param_count; ++i) {
982 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
986 /* The float param registers and other param registers must be the same index on Windows x64.*/
993 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
994 /* We allways pass the sig cookie on the stack for simplicity */
996 * Prevent implicit arguments + the sig cookie from being passed
1000 fr = FLOAT_PARAM_REGS;
1002 /* Emit the signature cookie just before the implicit arguments */
1003 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1006 ptype = mini_get_underlying_type (sig->params [i]);
1007 switch (ptype->type) {
1010 add_general (&gr, &stack_size, ainfo);
1014 add_general (&gr, &stack_size, ainfo);
1018 add_general (&gr, &stack_size, ainfo);
1023 case MONO_TYPE_FNPTR:
1024 case MONO_TYPE_CLASS:
1025 case MONO_TYPE_OBJECT:
1026 case MONO_TYPE_STRING:
1027 case MONO_TYPE_SZARRAY:
1028 case MONO_TYPE_ARRAY:
1029 add_general (&gr, &stack_size, ainfo);
1031 case MONO_TYPE_GENERICINST:
1032 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1033 add_general (&gr, &stack_size, ainfo);
1036 if (mini_is_gsharedvt_variable_type (ptype)) {
1037 /* gsharedvt arguments are passed by ref */
1038 add_general (&gr, &stack_size, ainfo);
1039 if (ainfo->storage == ArgInIReg)
1040 ainfo->storage = ArgGSharedVtInReg;
1042 ainfo->storage = ArgGSharedVtOnStack;
1046 case MONO_TYPE_VALUETYPE:
1047 case MONO_TYPE_TYPEDBYREF:
1048 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1053 add_general (&gr, &stack_size, ainfo);
1056 add_float (&fr, &stack_size, ainfo, FALSE);
1059 add_float (&fr, &stack_size, ainfo, TRUE);
1062 case MONO_TYPE_MVAR:
1063 /* gsharedvt arguments are passed by ref */
1064 g_assert (mini_is_gsharedvt_type (ptype));
1065 add_general (&gr, &stack_size, ainfo);
1066 if (ainfo->storage == ArgInIReg)
1067 ainfo->storage = ArgGSharedVtInReg;
1069 ainfo->storage = ArgGSharedVtOnStack;
1072 g_assert_not_reached ();
1076 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1078 fr = FLOAT_PARAM_REGS;
1080 /* Emit the signature cookie just before the implicit arguments */
1081 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1084 cinfo->stack_usage = stack_size;
1085 cinfo->reg_usage = gr;
1086 cinfo->freg_usage = fr;
1091 * mono_arch_get_argument_info:
1092 * @csig: a method signature
1093 * @param_count: the number of parameters to consider
1094 * @arg_info: an array to store the result infos
1096 * Gathers information on parameters such as size, alignment and
1097 * padding. arg_info should be large enought to hold param_count + 1 entries.
1099 * Returns the size of the argument area on the stack.
1102 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1105 CallInfo *cinfo = get_call_info (NULL, csig);
1106 guint32 args_size = cinfo->stack_usage;
1108 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1109 if (csig->hasthis) {
1110 arg_info [0].offset = 0;
1113 for (k = 0; k < param_count; k++) {
1114 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1116 arg_info [k + 1].size = 0;
1125 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1129 MonoType *callee_ret;
1131 c1 = get_call_info (NULL, caller_sig);
1132 c2 = get_call_info (NULL, callee_sig);
1133 res = c1->stack_usage >= c2->stack_usage;
1134 callee_ret = mini_get_underlying_type (callee_sig->ret);
1135 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1136 /* An address on the callee's stack is passed as the first argument */
1146 * Initialize the cpu to execute managed code.
1149 mono_arch_cpu_init (void)
1154 /* spec compliance requires running with double precision */
1155 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1156 fpcw &= ~X86_FPCW_PRECC_MASK;
1157 fpcw |= X86_FPCW_PREC_DOUBLE;
1158 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1159 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1161 /* TODO: This is crashing on Win64 right now.
1162 * _control87 (_PC_53, MCW_PC);
1168 * Initialize architecture specific code.
1171 mono_arch_init (void)
1173 mono_os_mutex_init_recursive (&mini_arch_mutex);
1175 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1176 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1177 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1178 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1179 mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1181 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1182 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1186 bp_trampoline = mini_get_breakpoint_trampoline ();
1190 * Cleanup architecture specific code.
1193 mono_arch_cleanup (void)
1195 mono_os_mutex_destroy (&mini_arch_mutex);
1199 * This function returns the optimizations supported on this cpu.
1202 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1208 if (mono_hwcap_x86_has_cmov) {
1209 opts |= MONO_OPT_CMOV;
1211 if (mono_hwcap_x86_has_fcmov)
1212 opts |= MONO_OPT_FCMOV;
1214 *exclude_mask |= MONO_OPT_FCMOV;
1216 *exclude_mask |= MONO_OPT_CMOV;
1220 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1221 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1222 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1223 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1224 /* will now have a reference to an argument that won't be fully decomposed. */
1225 *exclude_mask |= MONO_OPT_SIMD;
1232 * This function test for all SSE functions supported.
1234 * Returns a bitmask corresponding to all supported versions.
1238 mono_arch_cpu_enumerate_simd_versions (void)
1240 guint32 sse_opts = 0;
1242 if (mono_hwcap_x86_has_sse1)
1243 sse_opts |= SIMD_VERSION_SSE1;
1245 if (mono_hwcap_x86_has_sse2)
1246 sse_opts |= SIMD_VERSION_SSE2;
1248 if (mono_hwcap_x86_has_sse3)
1249 sse_opts |= SIMD_VERSION_SSE3;
1251 if (mono_hwcap_x86_has_ssse3)
1252 sse_opts |= SIMD_VERSION_SSSE3;
1254 if (mono_hwcap_x86_has_sse41)
1255 sse_opts |= SIMD_VERSION_SSE41;
1257 if (mono_hwcap_x86_has_sse42)
1258 sse_opts |= SIMD_VERSION_SSE42;
1260 if (mono_hwcap_x86_has_sse4a)
1261 sse_opts |= SIMD_VERSION_SSE4a;
1269 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1274 for (i = 0; i < cfg->num_varinfo; i++) {
1275 MonoInst *ins = cfg->varinfo [i];
1276 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1279 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1282 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1283 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1286 if (mono_is_regsize_var (ins->inst_vtype)) {
1287 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1288 g_assert (i == vmv->idx);
1289 vars = g_list_prepend (vars, vmv);
1293 vars = mono_varlist_sort (cfg, vars, 0);
1299 * mono_arch_compute_omit_fp:
1301 * Determine whenever the frame pointer can be eliminated.
1304 mono_arch_compute_omit_fp (MonoCompile *cfg)
1306 MonoMethodSignature *sig;
1307 MonoMethodHeader *header;
1311 if (cfg->arch.omit_fp_computed)
1314 header = cfg->header;
1316 sig = mono_method_signature (cfg->method);
1318 if (!cfg->arch.cinfo)
1319 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1320 cinfo = (CallInfo *)cfg->arch.cinfo;
1323 * FIXME: Remove some of the restrictions.
1325 cfg->arch.omit_fp = TRUE;
1326 cfg->arch.omit_fp_computed = TRUE;
1328 if (cfg->disable_omit_fp)
1329 cfg->arch.omit_fp = FALSE;
1331 if (!debug_omit_fp ())
1332 cfg->arch.omit_fp = FALSE;
1334 if (cfg->method->save_lmf)
1335 cfg->arch.omit_fp = FALSE;
1337 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1338 cfg->arch.omit_fp = FALSE;
1339 if (header->num_clauses)
1340 cfg->arch.omit_fp = FALSE;
1341 if (cfg->param_area)
1342 cfg->arch.omit_fp = FALSE;
1343 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1344 cfg->arch.omit_fp = FALSE;
1345 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1346 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1347 cfg->arch.omit_fp = FALSE;
1348 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1349 ArgInfo *ainfo = &cinfo->args [i];
1351 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1353 * The stack offset can only be determined when the frame
1356 cfg->arch.omit_fp = FALSE;
1361 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1362 MonoInst *ins = cfg->varinfo [i];
1365 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1370 mono_arch_get_global_int_regs (MonoCompile *cfg)
1374 mono_arch_compute_omit_fp (cfg);
1376 if (cfg->arch.omit_fp)
1377 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1379 /* We use the callee saved registers for global allocation */
1380 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1381 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1382 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1383 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1384 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1386 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1387 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1394 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1399 /* All XMM registers */
1400 for (i = 0; i < 16; ++i)
1401 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1407 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1409 static GList *r = NULL;
1414 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1415 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1416 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1417 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1418 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1419 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1421 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1422 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1423 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1424 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1425 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1426 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1427 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1428 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1430 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1437 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1440 static GList *r = NULL;
1445 for (i = 0; i < AMD64_XMM_NREG; ++i)
1446 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1448 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1455 * mono_arch_regalloc_cost:
1457 * Return the cost, in number of memory references, of the action of
1458 * allocating the variable VMV into a register during global register
1462 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1464 MonoInst *ins = cfg->varinfo [vmv->idx];
1466 if (cfg->method->save_lmf)
1467 /* The register is already saved */
1468 /* substract 1 for the invisible store in the prolog */
1469 return (ins->opcode == OP_ARG) ? 0 : 1;
1472 return (ins->opcode == OP_ARG) ? 1 : 2;
1476 * mono_arch_fill_argument_info:
1478 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1482 mono_arch_fill_argument_info (MonoCompile *cfg)
1485 MonoMethodSignature *sig;
1490 sig = mono_method_signature (cfg->method);
1492 cinfo = (CallInfo *)cfg->arch.cinfo;
1493 sig_ret = mini_get_underlying_type (sig->ret);
1496 * Contrary to mono_arch_allocate_vars (), the information should describe
1497 * where the arguments are at the beginning of the method, not where they can be
1498 * accessed during the execution of the method. The later makes no sense for the
1499 * global register allocator, since a variable can be in more than one location.
1501 switch (cinfo->ret.storage) {
1503 case ArgInFloatSSEReg:
1504 case ArgInDoubleSSEReg:
1505 cfg->ret->opcode = OP_REGVAR;
1506 cfg->ret->inst_c0 = cinfo->ret.reg;
1508 case ArgValuetypeInReg:
1509 cfg->ret->opcode = OP_REGOFFSET;
1510 cfg->ret->inst_basereg = -1;
1511 cfg->ret->inst_offset = -1;
1516 g_assert_not_reached ();
1519 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1520 ArgInfo *ainfo = &cinfo->args [i];
1522 ins = cfg->args [i];
1524 switch (ainfo->storage) {
1526 case ArgInFloatSSEReg:
1527 case ArgInDoubleSSEReg:
1528 ins->opcode = OP_REGVAR;
1529 ins->inst_c0 = ainfo->reg;
1532 ins->opcode = OP_REGOFFSET;
1533 ins->inst_basereg = -1;
1534 ins->inst_offset = -1;
1536 case ArgValuetypeInReg:
1538 ins->opcode = OP_NOP;
1541 g_assert_not_reached ();
1547 mono_arch_allocate_vars (MonoCompile *cfg)
1550 MonoMethodSignature *sig;
1553 guint32 locals_stack_size, locals_stack_align;
1557 sig = mono_method_signature (cfg->method);
1559 cinfo = (CallInfo *)cfg->arch.cinfo;
1560 sig_ret = mini_get_underlying_type (sig->ret);
1562 mono_arch_compute_omit_fp (cfg);
1565 * We use the ABI calling conventions for managed code as well.
1566 * Exception: valuetypes are only sometimes passed or returned in registers.
1570 * The stack looks like this:
1571 * <incoming arguments passed on the stack>
1573 * <lmf/caller saved registers>
1576 * <localloc area> -> grows dynamically
1580 if (cfg->arch.omit_fp) {
1581 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1582 cfg->frame_reg = AMD64_RSP;
1585 /* Locals are allocated backwards from %fp */
1586 cfg->frame_reg = AMD64_RBP;
1590 cfg->arch.saved_iregs = cfg->used_int_regs;
1591 if (cfg->method->save_lmf) {
1592 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1593 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1594 cfg->arch.saved_iregs |= iregs_to_save;
1597 if (cfg->arch.omit_fp)
1598 cfg->arch.reg_save_area_offset = offset;
1599 /* Reserve space for callee saved registers */
1600 for (i = 0; i < AMD64_NREG; ++i)
1601 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1602 offset += sizeof(mgreg_t);
1604 if (!cfg->arch.omit_fp)
1605 cfg->arch.reg_save_area_offset = -offset;
1607 if (sig_ret->type != MONO_TYPE_VOID) {
1608 switch (cinfo->ret.storage) {
1610 case ArgInFloatSSEReg:
1611 case ArgInDoubleSSEReg:
1612 cfg->ret->opcode = OP_REGVAR;
1613 cfg->ret->inst_c0 = cinfo->ret.reg;
1614 cfg->ret->dreg = cinfo->ret.reg;
1616 case ArgValuetypeAddrInIReg:
1617 case ArgGsharedvtVariableInReg:
1618 /* The register is volatile */
1619 cfg->vret_addr->opcode = OP_REGOFFSET;
1620 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1621 if (cfg->arch.omit_fp) {
1622 cfg->vret_addr->inst_offset = offset;
1626 cfg->vret_addr->inst_offset = -offset;
1628 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1629 printf ("vret_addr =");
1630 mono_print_ins (cfg->vret_addr);
1633 case ArgValuetypeInReg:
1634 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1635 cfg->ret->opcode = OP_REGOFFSET;
1636 cfg->ret->inst_basereg = cfg->frame_reg;
1637 if (cfg->arch.omit_fp) {
1638 cfg->ret->inst_offset = offset;
1639 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1641 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1642 cfg->ret->inst_offset = - offset;
1646 g_assert_not_reached ();
1650 /* Allocate locals */
1651 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1652 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1653 char *mname = mono_method_full_name (cfg->method, TRUE);
1654 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1659 if (locals_stack_align) {
1660 offset += (locals_stack_align - 1);
1661 offset &= ~(locals_stack_align - 1);
1663 if (cfg->arch.omit_fp) {
1664 cfg->locals_min_stack_offset = offset;
1665 cfg->locals_max_stack_offset = offset + locals_stack_size;
1667 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1668 cfg->locals_max_stack_offset = - offset;
1671 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1672 if (offsets [i] != -1) {
1673 MonoInst *ins = cfg->varinfo [i];
1674 ins->opcode = OP_REGOFFSET;
1675 ins->inst_basereg = cfg->frame_reg;
1676 if (cfg->arch.omit_fp)
1677 ins->inst_offset = (offset + offsets [i]);
1679 ins->inst_offset = - (offset + offsets [i]);
1680 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1683 offset += locals_stack_size;
1685 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1686 g_assert (!cfg->arch.omit_fp);
1687 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1688 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1691 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1692 ins = cfg->args [i];
1693 if (ins->opcode != OP_REGVAR) {
1694 ArgInfo *ainfo = &cinfo->args [i];
1695 gboolean inreg = TRUE;
1697 /* FIXME: Allocate volatile arguments to registers */
1698 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1702 * Under AMD64, all registers used to pass arguments to functions
1703 * are volatile across calls.
1704 * FIXME: Optimize this.
1706 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1709 ins->opcode = OP_REGOFFSET;
1711 switch (ainfo->storage) {
1713 case ArgInFloatSSEReg:
1714 case ArgInDoubleSSEReg:
1715 case ArgGSharedVtInReg:
1717 ins->opcode = OP_REGVAR;
1718 ins->dreg = ainfo->reg;
1722 case ArgGSharedVtOnStack:
1723 g_assert (!cfg->arch.omit_fp);
1724 ins->opcode = OP_REGOFFSET;
1725 ins->inst_basereg = cfg->frame_reg;
1726 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1728 case ArgValuetypeInReg:
1730 case ArgValuetypeAddrInIReg:
1731 case ArgValuetypeAddrOnStack: {
1733 g_assert (!cfg->arch.omit_fp);
1734 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1735 MONO_INST_NEW (cfg, indir, 0);
1737 indir->opcode = OP_REGOFFSET;
1738 if (ainfo->pair_storage [0] == ArgInIReg) {
1739 indir->inst_basereg = cfg->frame_reg;
1740 offset = ALIGN_TO (offset, sizeof (gpointer));
1741 offset += (sizeof (gpointer));
1742 indir->inst_offset = - offset;
1745 indir->inst_basereg = cfg->frame_reg;
1746 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1749 ins->opcode = OP_VTARG_ADDR;
1750 ins->inst_left = indir;
1758 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1759 ins->opcode = OP_REGOFFSET;
1760 ins->inst_basereg = cfg->frame_reg;
1761 /* These arguments are saved to the stack in the prolog */
1762 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1763 if (cfg->arch.omit_fp) {
1764 ins->inst_offset = offset;
1765 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1766 // Arguments are yet supported by the stack map creation code
1767 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1769 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1770 ins->inst_offset = - offset;
1771 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1777 cfg->stack_offset = offset;
1781 mono_arch_create_vars (MonoCompile *cfg)
1783 MonoMethodSignature *sig;
1787 sig = mono_method_signature (cfg->method);
1789 if (!cfg->arch.cinfo)
1790 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1791 cinfo = (CallInfo *)cfg->arch.cinfo;
1793 if (cinfo->ret.storage == ArgValuetypeInReg)
1794 cfg->ret_var_is_local = TRUE;
1796 sig_ret = mini_get_underlying_type (sig->ret);
1797 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1798 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1799 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1800 printf ("vret_addr = ");
1801 mono_print_ins (cfg->vret_addr);
1805 if (cfg->gen_sdb_seq_points) {
1808 if (cfg->compile_aot) {
1809 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1810 ins->flags |= MONO_INST_VOLATILE;
1811 cfg->arch.seq_point_info_var = ins;
1813 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1814 ins->flags |= MONO_INST_VOLATILE;
1815 cfg->arch.ss_tramp_var = ins;
1817 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1818 ins->flags |= MONO_INST_VOLATILE;
1819 cfg->arch.bp_tramp_var = ins;
1822 if (cfg->method->save_lmf)
1823 cfg->create_lmf_var = TRUE;
1825 if (cfg->method->save_lmf) {
1831 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1837 MONO_INST_NEW (cfg, ins, OP_MOVE);
1838 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1839 ins->sreg1 = tree->dreg;
1840 MONO_ADD_INS (cfg->cbb, ins);
1841 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1843 case ArgInFloatSSEReg:
1844 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1845 ins->dreg = mono_alloc_freg (cfg);
1846 ins->sreg1 = tree->dreg;
1847 MONO_ADD_INS (cfg->cbb, ins);
1849 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1851 case ArgInDoubleSSEReg:
1852 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1853 ins->dreg = mono_alloc_freg (cfg);
1854 ins->sreg1 = tree->dreg;
1855 MONO_ADD_INS (cfg->cbb, ins);
1857 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1861 g_assert_not_reached ();
1866 arg_storage_to_load_membase (ArgStorage storage)
1870 #if defined(__mono_ilp32__)
1871 return OP_LOADI8_MEMBASE;
1873 return OP_LOAD_MEMBASE;
1875 case ArgInDoubleSSEReg:
1876 return OP_LOADR8_MEMBASE;
1877 case ArgInFloatSSEReg:
1878 return OP_LOADR4_MEMBASE;
1880 g_assert_not_reached ();
1887 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1889 MonoMethodSignature *tmp_sig;
1892 if (call->tail_call)
1895 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1898 * mono_ArgIterator_Setup assumes the signature cookie is
1899 * passed first and all the arguments which were before it are
1900 * passed on the stack after the signature. So compensate by
1901 * passing a different signature.
1903 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1904 tmp_sig->param_count -= call->signature->sentinelpos;
1905 tmp_sig->sentinelpos = 0;
1906 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1908 sig_reg = mono_alloc_ireg (cfg);
1909 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1911 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1915 static inline LLVMArgStorage
1916 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1920 return LLVMArgInIReg;
1923 case ArgGSharedVtInReg:
1924 case ArgGSharedVtOnStack:
1925 return LLVMArgGSharedVt;
1927 g_assert_not_reached ();
1933 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1939 LLVMCallInfo *linfo;
1940 MonoType *t, *sig_ret;
1942 n = sig->param_count + sig->hasthis;
1943 sig_ret = mini_get_underlying_type (sig->ret);
1945 cinfo = get_call_info (cfg->mempool, sig);
1947 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1950 * LLVM always uses the native ABI while we use our own ABI, the
1951 * only difference is the handling of vtypes:
1952 * - we only pass/receive them in registers in some cases, and only
1953 * in 1 or 2 integer registers.
1955 switch (cinfo->ret.storage) {
1957 linfo->ret.storage = LLVMArgNone;
1960 case ArgInFloatSSEReg:
1961 case ArgInDoubleSSEReg:
1962 linfo->ret.storage = LLVMArgNormal;
1964 case ArgValuetypeInReg: {
1965 ainfo = &cinfo->ret;
1968 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1969 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1970 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1971 cfg->disable_llvm = TRUE;
1975 linfo->ret.storage = LLVMArgVtypeInReg;
1976 for (j = 0; j < 2; ++j)
1977 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1980 case ArgValuetypeAddrInIReg:
1981 case ArgGsharedvtVariableInReg:
1982 /* Vtype returned using a hidden argument */
1983 linfo->ret.storage = LLVMArgVtypeRetAddr;
1984 linfo->vret_arg_index = cinfo->vret_arg_index;
1987 g_assert_not_reached ();
1991 for (i = 0; i < n; ++i) {
1992 ainfo = cinfo->args + i;
1994 if (i >= sig->hasthis)
1995 t = sig->params [i - sig->hasthis];
1997 t = &mono_defaults.int_class->byval_arg;
1998 t = mini_type_get_underlying_type (t);
2000 linfo->args [i].storage = LLVMArgNone;
2002 switch (ainfo->storage) {
2004 linfo->args [i].storage = LLVMArgNormal;
2006 case ArgInDoubleSSEReg:
2007 case ArgInFloatSSEReg:
2008 linfo->args [i].storage = LLVMArgNormal;
2011 if (MONO_TYPE_ISSTRUCT (t))
2012 linfo->args [i].storage = LLVMArgVtypeByVal;
2014 linfo->args [i].storage = LLVMArgNormal;
2016 case ArgValuetypeInReg:
2018 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2019 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2020 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2021 cfg->disable_llvm = TRUE;
2025 linfo->args [i].storage = LLVMArgVtypeInReg;
2026 for (j = 0; j < 2; ++j)
2027 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2029 case ArgGSharedVtInReg:
2030 case ArgGSharedVtOnStack:
2031 linfo->args [i].storage = LLVMArgGSharedVt;
2034 cfg->exception_message = g_strdup ("ainfo->storage");
2035 cfg->disable_llvm = TRUE;
2045 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2048 MonoMethodSignature *sig;
2054 sig = call->signature;
2055 n = sig->param_count + sig->hasthis;
2057 cinfo = get_call_info (cfg->mempool, sig);
2061 if (COMPILE_LLVM (cfg)) {
2062 /* We shouldn't be called in the llvm case */
2063 cfg->disable_llvm = TRUE;
2068 * Emit all arguments which are passed on the stack to prevent register
2069 * allocation problems.
2071 for (i = 0; i < n; ++i) {
2073 ainfo = cinfo->args + i;
2075 in = call->args [i];
2077 if (sig->hasthis && i == 0)
2078 t = &mono_defaults.object_class->byval_arg;
2080 t = sig->params [i - sig->hasthis];
2082 t = mini_get_underlying_type (t);
2083 //XXX what about ArgGSharedVtOnStack here?
2084 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2086 if (t->type == MONO_TYPE_R4)
2087 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2088 else if (t->type == MONO_TYPE_R8)
2089 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2091 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2093 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2095 if (cfg->compute_gc_maps) {
2098 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2104 * Emit all parameters passed in registers in non-reverse order for better readability
2105 * and to help the optimization in emit_prolog ().
2107 for (i = 0; i < n; ++i) {
2108 ainfo = cinfo->args + i;
2110 in = call->args [i];
2112 if (ainfo->storage == ArgInIReg)
2113 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2116 for (i = n - 1; i >= 0; --i) {
2119 ainfo = cinfo->args + i;
2121 in = call->args [i];
2123 if (sig->hasthis && i == 0)
2124 t = &mono_defaults.object_class->byval_arg;
2126 t = sig->params [i - sig->hasthis];
2127 t = mini_get_underlying_type (t);
2129 switch (ainfo->storage) {
2133 case ArgInFloatSSEReg:
2134 case ArgInDoubleSSEReg:
2135 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2138 case ArgValuetypeInReg:
2139 case ArgValuetypeAddrInIReg:
2140 case ArgValuetypeAddrOnStack:
2141 case ArgGSharedVtInReg:
2142 case ArgGSharedVtOnStack: {
2143 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2144 /* Already emitted above */
2146 //FIXME what about ArgGSharedVtOnStack ?
2147 if (ainfo->storage == ArgOnStack && call->tail_call) {
2148 MonoInst *call_inst = (MonoInst*)call;
2149 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2150 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2158 size = mono_type_native_stack_size (t, &align);
2161 * Other backends use mono_type_stack_size (), but that
2162 * aligns the size to 8, which is larger than the size of
2163 * the source, leading to reads of invalid memory if the
2164 * source is at the end of address space.
2166 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2169 if (size >= 10000) {
2170 /* Avoid asserts in emit_memcpy () */
2171 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2172 /* Continue normally */
2175 if (size > 0 || ainfo->pass_empty_struct) {
2176 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2177 arg->sreg1 = in->dreg;
2178 arg->klass = mono_class_from_mono_type (t);
2179 arg->backend.size = size;
2180 arg->inst_p0 = call;
2181 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2182 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2184 MONO_ADD_INS (cfg->cbb, arg);
2189 g_assert_not_reached ();
2192 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2193 /* Emit the signature cookie just before the implicit arguments */
2194 emit_sig_cookie (cfg, call, cinfo);
2197 /* Handle the case where there are no implicit arguments */
2198 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2199 emit_sig_cookie (cfg, call, cinfo);
2201 switch (cinfo->ret.storage) {
2202 case ArgValuetypeInReg:
2203 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2205 * Tell the JIT to use a more efficient calling convention: call using
2206 * OP_CALL, compute the result location after the call, and save the
2209 call->vret_in_reg = TRUE;
2211 * Nullify the instruction computing the vret addr to enable
2212 * future optimizations.
2215 NULLIFY_INS (call->vret_var);
2217 if (call->tail_call)
2220 * The valuetype is in RAX:RDX after the call, need to be copied to
2221 * the stack. Push the address here, so the call instruction can
2224 if (!cfg->arch.vret_addr_loc) {
2225 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2226 /* Prevent it from being register allocated or optimized away */
2227 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2230 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2233 case ArgValuetypeAddrInIReg:
2234 case ArgGsharedvtVariableInReg: {
2236 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2237 vtarg->sreg1 = call->vret_var->dreg;
2238 vtarg->dreg = mono_alloc_preg (cfg);
2239 MONO_ADD_INS (cfg->cbb, vtarg);
2241 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2248 if (cfg->method->save_lmf) {
2249 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2250 MONO_ADD_INS (cfg->cbb, arg);
2253 call->stack_usage = cinfo->stack_usage;
2257 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2260 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2261 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2262 int size = ins->backend.size;
2264 switch (ainfo->storage) {
2265 case ArgValuetypeInReg: {
2269 for (part = 0; part < 2; ++part) {
2270 if (ainfo->pair_storage [part] == ArgNone)
2273 if (ainfo->pass_empty_struct) {
2274 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2275 NEW_ICONST (cfg, load, 0);
2278 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2279 load->inst_basereg = src->dreg;
2280 load->inst_offset = part * sizeof(mgreg_t);
2282 switch (ainfo->pair_storage [part]) {
2284 load->dreg = mono_alloc_ireg (cfg);
2286 case ArgInDoubleSSEReg:
2287 case ArgInFloatSSEReg:
2288 load->dreg = mono_alloc_freg (cfg);
2291 g_assert_not_reached ();
2295 MONO_ADD_INS (cfg->cbb, load);
2297 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2301 case ArgValuetypeAddrInIReg:
2302 case ArgValuetypeAddrOnStack: {
2303 MonoInst *vtaddr, *load;
2305 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2307 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2309 MONO_INST_NEW (cfg, load, OP_LDADDR);
2310 cfg->has_indirection = TRUE;
2311 load->inst_p0 = vtaddr;
2312 vtaddr->flags |= MONO_INST_INDIRECT;
2313 load->type = STACK_MP;
2314 load->klass = vtaddr->klass;
2315 load->dreg = mono_alloc_ireg (cfg);
2316 MONO_ADD_INS (cfg->cbb, load);
2317 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2319 if (ainfo->pair_storage [0] == ArgInIReg) {
2320 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2321 arg->dreg = mono_alloc_ireg (cfg);
2322 arg->sreg1 = load->dreg;
2324 MONO_ADD_INS (cfg->cbb, arg);
2325 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2327 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2331 case ArgGSharedVtInReg:
2333 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2335 case ArgGSharedVtOnStack:
2336 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2340 int dreg = mono_alloc_ireg (cfg);
2342 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2343 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2344 } else if (size <= 40) {
2345 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2347 // FIXME: Code growth
2348 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2351 if (cfg->compute_gc_maps) {
2353 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2359 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2361 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2363 if (ret->type == MONO_TYPE_R4) {
2364 if (COMPILE_LLVM (cfg))
2365 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2367 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2369 } else if (ret->type == MONO_TYPE_R8) {
2370 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2374 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2377 #endif /* DISABLE_JIT */
2379 #define EMIT_COND_BRANCH(ins,cond,sign) \
2380 if (ins->inst_true_bb->native_offset) { \
2381 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2383 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2384 if ((cfg->opt & MONO_OPT_BRANCH) && \
2385 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2386 x86_branch8 (code, cond, 0, sign); \
2388 x86_branch32 (code, cond, 0, sign); \
2392 MonoMethodSignature *sig;
2397 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2401 switch (cinfo->ret.storage) {
2404 case ArgInFloatSSEReg:
2405 case ArgInDoubleSSEReg:
2406 case ArgValuetypeAddrInIReg:
2407 case ArgValuetypeInReg:
2413 for (i = 0; i < cinfo->nargs; ++i) {
2414 ArgInfo *ainfo = &cinfo->args [i];
2415 switch (ainfo->storage) {
2417 case ArgInFloatSSEReg:
2418 case ArgInDoubleSSEReg:
2419 case ArgValuetypeInReg:
2422 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2434 * mono_arch_dyn_call_prepare:
2436 * Return a pointer to an arch-specific structure which contains information
2437 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2438 * supported for SIG.
2439 * This function is equivalent to ffi_prep_cif in libffi.
2442 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2444 ArchDynCallInfo *info;
2447 cinfo = get_call_info (NULL, sig);
2449 if (!dyn_call_supported (sig, cinfo)) {
2454 info = g_new0 (ArchDynCallInfo, 1);
2455 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2457 info->cinfo = cinfo;
2459 return (MonoDynCallInfo*)info;
2463 * mono_arch_dyn_call_free:
2465 * Free a MonoDynCallInfo structure.
2468 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2470 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2472 g_free (ainfo->cinfo);
2476 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2477 #define GREG_TO_PTR(greg) (gpointer)(greg)
2480 * mono_arch_get_start_dyn_call:
2482 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2483 * store the result into BUF.
2484 * ARGS should be an array of pointers pointing to the arguments.
2485 * RET should point to a memory buffer large enought to hold the result of the
2487 * This function should be as fast as possible, any work which does not depend
2488 * on the actual values of the arguments should be done in
2489 * mono_arch_dyn_call_prepare ().
2490 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2494 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2496 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2497 DynCallArgs *p = (DynCallArgs*)buf;
2498 int arg_index, greg, freg, i, pindex;
2499 MonoMethodSignature *sig = dinfo->sig;
2500 int buffer_offset = 0;
2501 static int param_reg_to_index [16];
2502 static gboolean param_reg_to_index_inited;
2504 if (!param_reg_to_index_inited) {
2505 for (i = 0; i < PARAM_REGS; ++i)
2506 param_reg_to_index [param_regs [i]] = i;
2507 mono_memory_barrier ();
2508 param_reg_to_index_inited = 1;
2511 g_assert (buf_len >= sizeof (DynCallArgs));
2521 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2522 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2527 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2528 p->regs [greg ++] = PTR_TO_GREG(ret);
2530 for (; pindex < sig->param_count; pindex++) {
2531 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2532 gpointer *arg = args [arg_index ++];
2533 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2536 if (ainfo->storage == ArgOnStack) {
2537 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2539 slot = param_reg_to_index [ainfo->reg];
2543 p->regs [slot] = PTR_TO_GREG(*(arg));
2549 case MONO_TYPE_STRING:
2550 case MONO_TYPE_CLASS:
2551 case MONO_TYPE_ARRAY:
2552 case MONO_TYPE_SZARRAY:
2553 case MONO_TYPE_OBJECT:
2557 #if !defined(__mono_ilp32__)
2561 p->regs [slot] = PTR_TO_GREG(*(arg));
2563 #if defined(__mono_ilp32__)
2566 p->regs [slot] = *(guint64*)(arg);
2570 p->regs [slot] = *(guint8*)(arg);
2573 p->regs [slot] = *(gint8*)(arg);
2576 p->regs [slot] = *(gint16*)(arg);
2579 p->regs [slot] = *(guint16*)(arg);
2582 p->regs [slot] = *(gint32*)(arg);
2585 p->regs [slot] = *(guint32*)(arg);
2587 case MONO_TYPE_R4: {
2590 *(float*)&d = *(float*)(arg);
2592 p->fregs [freg ++] = d;
2597 p->fregs [freg ++] = *(double*)(arg);
2599 case MONO_TYPE_GENERICINST:
2600 if (MONO_TYPE_IS_REFERENCE (t)) {
2601 p->regs [slot] = PTR_TO_GREG(*(arg));
2603 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2604 MonoClass *klass = mono_class_from_mono_type (t);
2605 guint8 *nullable_buf;
2608 size = mono_class_value_size (klass, NULL);
2609 nullable_buf = p->buffer + buffer_offset;
2610 buffer_offset += size;
2611 g_assert (buffer_offset <= 256);
2613 /* The argument pointed to by arg is either a boxed vtype or null */
2614 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2616 arg = (gpointer*)nullable_buf;
2622 case MONO_TYPE_VALUETYPE: {
2623 switch (ainfo->storage) {
2624 case ArgValuetypeInReg:
2625 for (i = 0; i < 2; ++i) {
2626 switch (ainfo->pair_storage [i]) {
2630 slot = param_reg_to_index [ainfo->pair_regs [i]];
2631 p->regs [slot] = ((mgreg_t*)(arg))[i];
2633 case ArgInDoubleSSEReg:
2635 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2638 g_assert_not_reached ();
2644 for (i = 0; i < ainfo->arg_size / 8; ++i)
2645 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2648 g_assert_not_reached ();
2654 g_assert_not_reached ();
2660 * mono_arch_finish_dyn_call:
2662 * Store the result of a dyn call into the return value buffer passed to
2663 * start_dyn_call ().
2664 * This function should be as fast as possible, any work which does not depend
2665 * on the actual values of the arguments should be done in
2666 * mono_arch_dyn_call_prepare ().
2669 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2671 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2672 MonoMethodSignature *sig = dinfo->sig;
2673 DynCallArgs *dargs = (DynCallArgs*)buf;
2674 guint8 *ret = dargs->ret;
2675 mgreg_t res = dargs->res;
2676 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2679 switch (sig_ret->type) {
2680 case MONO_TYPE_VOID:
2681 *(gpointer*)ret = NULL;
2683 case MONO_TYPE_STRING:
2684 case MONO_TYPE_CLASS:
2685 case MONO_TYPE_ARRAY:
2686 case MONO_TYPE_SZARRAY:
2687 case MONO_TYPE_OBJECT:
2691 *(gpointer*)ret = GREG_TO_PTR(res);
2697 *(guint8*)ret = res;
2700 *(gint16*)ret = res;
2703 *(guint16*)ret = res;
2706 *(gint32*)ret = res;
2709 *(guint32*)ret = res;
2712 *(gint64*)ret = res;
2715 *(guint64*)ret = res;
2718 *(float*)ret = *(float*)&(dargs->fregs [0]);
2721 *(double*)ret = dargs->fregs [0];
2723 case MONO_TYPE_GENERICINST:
2724 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2725 *(gpointer*)ret = GREG_TO_PTR(res);
2730 case MONO_TYPE_VALUETYPE:
2731 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2734 ArgInfo *ainfo = &dinfo->cinfo->ret;
2736 g_assert (ainfo->storage == ArgValuetypeInReg);
2738 for (i = 0; i < 2; ++i) {
2739 switch (ainfo->pair_storage [0]) {
2741 ((mgreg_t*)ret)[i] = res;
2743 case ArgInDoubleSSEReg:
2744 ((double*)ret)[i] = dargs->fregs [i];
2749 g_assert_not_reached ();
2756 g_assert_not_reached ();
2760 /* emit an exception if condition is fail */
2761 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2763 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2764 if (tins == NULL) { \
2765 mono_add_patch_info (cfg, code - cfg->native_code, \
2766 MONO_PATCH_INFO_EXC, exc_name); \
2767 x86_branch32 (code, cond, 0, signed); \
2769 EMIT_COND_BRANCH (tins, cond, signed); \
2773 #define EMIT_FPCOMPARE(code) do { \
2774 amd64_fcompp (code); \
2775 amd64_fnstsw (code); \
2778 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2779 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2780 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2781 amd64_ ##op (code); \
2782 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2783 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2787 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2789 gboolean no_patch = FALSE;
2792 * FIXME: Add support for thunks
2795 gboolean near_call = FALSE;
2798 * Indirect calls are expensive so try to make a near call if possible.
2799 * The caller memory is allocated by the code manager so it is
2800 * guaranteed to be at a 32 bit offset.
2803 if (patch_type != MONO_PATCH_INFO_ABS) {
2804 /* The target is in memory allocated using the code manager */
2807 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2808 if (((MonoMethod*)data)->klass->image->aot_module)
2809 /* The callee might be an AOT method */
2811 if (((MonoMethod*)data)->dynamic)
2812 /* The target is in malloc-ed memory */
2816 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2818 * The call might go directly to a native function without
2821 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2823 gconstpointer target = mono_icall_get_wrapper (mi);
2824 if ((((guint64)target) >> 32) != 0)
2830 MonoJumpInfo *jinfo = NULL;
2832 if (cfg->abs_patches)
2833 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2835 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2836 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2837 if (mi && (((guint64)mi->func) >> 32) == 0)
2842 * This is not really an optimization, but required because the
2843 * generic class init trampolines use R11 to pass the vtable.
2848 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2850 if (info->func == info->wrapper) {
2852 if ((((guint64)info->func) >> 32) == 0)
2856 /* See the comment in mono_codegen () */
2857 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2861 else if ((((guint64)data) >> 32) == 0) {
2868 if (cfg->method->dynamic)
2869 /* These methods are allocated using malloc */
2872 #ifdef MONO_ARCH_NOMAP32BIT
2875 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2876 if (optimize_for_xen)
2879 if (cfg->compile_aot) {
2886 * Align the call displacement to an address divisible by 4 so it does
2887 * not span cache lines. This is required for code patching to work on SMP
2890 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2891 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2892 amd64_padding (code, pad_size);
2894 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2895 amd64_call_code (code, 0);
2898 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2899 amd64_set_reg_template (code, GP_SCRATCH_REG);
2900 amd64_call_reg (code, GP_SCRATCH_REG);
2907 static inline guint8*
2908 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2911 if (win64_adjust_stack)
2912 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2914 code = emit_call_body (cfg, code, patch_type, data);
2916 if (win64_adjust_stack)
2917 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2924 store_membase_imm_to_store_membase_reg (int opcode)
2927 case OP_STORE_MEMBASE_IMM:
2928 return OP_STORE_MEMBASE_REG;
2929 case OP_STOREI4_MEMBASE_IMM:
2930 return OP_STOREI4_MEMBASE_REG;
2931 case OP_STOREI8_MEMBASE_IMM:
2932 return OP_STOREI8_MEMBASE_REG;
2940 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2943 * mono_arch_peephole_pass_1:
2945 * Perform peephole opts which should/can be performed before local regalloc
2948 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2952 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2953 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2955 switch (ins->opcode) {
2959 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2961 * X86_LEA is like ADD, but doesn't have the
2962 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2963 * its operand to 64 bit.
2965 ins->opcode = OP_X86_LEA_MEMBASE;
2966 ins->inst_basereg = ins->sreg1;
2971 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2975 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2976 * the latter has length 2-3 instead of 6 (reverse constant
2977 * propagation). These instruction sequences are very common
2978 * in the initlocals bblock.
2980 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2981 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2982 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2983 ins2->sreg1 = ins->dreg;
2984 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2986 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2989 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2997 case OP_COMPARE_IMM:
2998 case OP_LCOMPARE_IMM:
2999 /* OP_COMPARE_IMM (reg, 0)
3001 * OP_AMD64_TEST_NULL (reg)
3004 ins->opcode = OP_AMD64_TEST_NULL;
3006 case OP_ICOMPARE_IMM:
3008 ins->opcode = OP_X86_TEST_NULL;
3010 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3012 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3013 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3015 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3016 * OP_COMPARE_IMM reg, imm
3018 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3020 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3021 ins->inst_basereg == last_ins->inst_destbasereg &&
3022 ins->inst_offset == last_ins->inst_offset) {
3023 ins->opcode = OP_ICOMPARE_IMM;
3024 ins->sreg1 = last_ins->sreg1;
3026 /* check if we can remove cmp reg,0 with test null */
3028 ins->opcode = OP_X86_TEST_NULL;
3034 mono_peephole_ins (bb, ins);
3039 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3043 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3044 switch (ins->opcode) {
3047 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3048 /* reg = 0 -> XOR (reg, reg) */
3049 /* XOR sets cflags on x86, so we cant do it always */
3050 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3051 ins->opcode = OP_LXOR;
3052 ins->sreg1 = ins->dreg;
3053 ins->sreg2 = ins->dreg;
3061 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3062 * 0 result into 64 bits.
3064 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3065 ins->opcode = OP_IXOR;
3069 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3073 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3074 * the latter has length 2-3 instead of 6 (reverse constant
3075 * propagation). These instruction sequences are very common
3076 * in the initlocals bblock.
3078 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3079 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3080 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3081 ins2->sreg1 = ins->dreg;
3082 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3084 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3087 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3096 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3097 ins->opcode = OP_X86_INC_REG;
3100 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3101 ins->opcode = OP_X86_DEC_REG;
3105 mono_peephole_ins (bb, ins);
3109 #define NEW_INS(cfg,ins,dest,op) do { \
3110 MONO_INST_NEW ((cfg), (dest), (op)); \
3111 (dest)->cil_code = (ins)->cil_code; \
3112 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3116 * mono_arch_lowering_pass:
3118 * Converts complex opcodes into simpler ones so that each IR instruction
3119 * corresponds to one machine instruction.
3122 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3124 MonoInst *ins, *n, *temp;
3127 * FIXME: Need to add more instructions, but the current machine
3128 * description can't model some parts of the composite instructions like
3131 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3132 switch (ins->opcode) {
3136 case OP_IDIV_UN_IMM:
3137 case OP_IREM_UN_IMM:
3140 mono_decompose_op_imm (cfg, bb, ins);
3142 case OP_COMPARE_IMM:
3143 case OP_LCOMPARE_IMM:
3144 if (!amd64_use_imm32 (ins->inst_imm)) {
3145 NEW_INS (cfg, ins, temp, OP_I8CONST);
3146 temp->inst_c0 = ins->inst_imm;
3147 temp->dreg = mono_alloc_ireg (cfg);
3148 ins->opcode = OP_COMPARE;
3149 ins->sreg2 = temp->dreg;
3152 #ifndef __mono_ilp32__
3153 case OP_LOAD_MEMBASE:
3155 case OP_LOADI8_MEMBASE:
3156 /* Don't generate memindex opcodes (to simplify */
3157 /* read sandboxing) */
3158 if (!amd64_use_imm32 (ins->inst_offset)) {
3159 NEW_INS (cfg, ins, temp, OP_I8CONST);
3160 temp->inst_c0 = ins->inst_offset;
3161 temp->dreg = mono_alloc_ireg (cfg);
3162 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3163 ins->inst_indexreg = temp->dreg;
3166 #ifndef __mono_ilp32__
3167 case OP_STORE_MEMBASE_IMM:
3169 case OP_STOREI8_MEMBASE_IMM:
3170 if (!amd64_use_imm32 (ins->inst_imm)) {
3171 NEW_INS (cfg, ins, temp, OP_I8CONST);
3172 temp->inst_c0 = ins->inst_imm;
3173 temp->dreg = mono_alloc_ireg (cfg);
3174 ins->opcode = OP_STOREI8_MEMBASE_REG;
3175 ins->sreg1 = temp->dreg;
3178 #ifdef MONO_ARCH_SIMD_INTRINSICS
3179 case OP_EXPAND_I1: {
3180 int temp_reg1 = mono_alloc_ireg (cfg);
3181 int temp_reg2 = mono_alloc_ireg (cfg);
3182 int original_reg = ins->sreg1;
3184 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3185 temp->sreg1 = original_reg;
3186 temp->dreg = temp_reg1;
3188 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3189 temp->sreg1 = temp_reg1;
3190 temp->dreg = temp_reg2;
3193 NEW_INS (cfg, ins, temp, OP_LOR);
3194 temp->sreg1 = temp->dreg = temp_reg2;
3195 temp->sreg2 = temp_reg1;
3197 ins->opcode = OP_EXPAND_I2;
3198 ins->sreg1 = temp_reg2;
3207 bb->max_vreg = cfg->next_vreg;
3211 branch_cc_table [] = {
3212 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3213 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3214 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3217 /* Maps CMP_... constants to X86_CC_... constants */
3220 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3221 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3225 cc_signed_table [] = {
3226 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3227 FALSE, FALSE, FALSE, FALSE
3230 /*#include "cprop.c"*/
3232 static unsigned char*
3233 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3236 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3238 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3241 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3243 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3247 static unsigned char*
3248 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3250 int sreg = tree->sreg1;
3251 int need_touch = FALSE;
3253 #if defined(TARGET_WIN32)
3255 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3256 if (!tree->flags & MONO_INST_INIT)
3265 * If requested stack size is larger than one page,
3266 * perform stack-touch operation
3269 * Generate stack probe code.
3270 * Under Windows, it is necessary to allocate one page at a time,
3271 * "touching" stack after each successful sub-allocation. This is
3272 * because of the way stack growth is implemented - there is a
3273 * guard page before the lowest stack page that is currently commited.
3274 * Stack normally grows sequentially so OS traps access to the
3275 * guard page and commits more pages when needed.
3277 amd64_test_reg_imm (code, sreg, ~0xFFF);
3278 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3280 br[2] = code; /* loop */
3281 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3282 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3283 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3284 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3285 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3286 amd64_patch (br[3], br[2]);
3287 amd64_test_reg_reg (code, sreg, sreg);
3288 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3289 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3291 br[1] = code; x86_jump8 (code, 0);
3293 amd64_patch (br[0], code);
3294 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3295 amd64_patch (br[1], code);
3296 amd64_patch (br[4], code);
3299 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3301 if (tree->flags & MONO_INST_INIT) {
3303 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3304 amd64_push_reg (code, AMD64_RAX);
3307 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3308 amd64_push_reg (code, AMD64_RCX);
3311 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3312 amd64_push_reg (code, AMD64_RDI);
3316 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3317 if (sreg != AMD64_RCX)
3318 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3319 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3321 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3322 if (cfg->param_area)
3323 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3325 amd64_prefix (code, X86_REP_PREFIX);
3328 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3329 amd64_pop_reg (code, AMD64_RDI);
3330 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3331 amd64_pop_reg (code, AMD64_RCX);
3332 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3333 amd64_pop_reg (code, AMD64_RAX);
3339 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3344 /* Move return value to the target register */
3345 /* FIXME: do this in the local reg allocator */
3346 switch (ins->opcode) {
3349 case OP_CALL_MEMBASE:
3352 case OP_LCALL_MEMBASE:
3353 g_assert (ins->dreg == AMD64_RAX);
3357 case OP_FCALL_MEMBASE: {
3358 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3359 if (rtype->type == MONO_TYPE_R4) {
3360 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3363 if (ins->dreg != AMD64_XMM0)
3364 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3370 case OP_RCALL_MEMBASE:
3371 if (ins->dreg != AMD64_XMM0)
3372 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3376 case OP_VCALL_MEMBASE:
3379 case OP_VCALL2_MEMBASE:
3380 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3381 if (cinfo->ret.storage == ArgValuetypeInReg) {
3382 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3384 /* Load the destination address */
3385 g_assert (loc->opcode == OP_REGOFFSET);
3386 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3388 for (quad = 0; quad < 2; quad ++) {
3389 switch (cinfo->ret.pair_storage [quad]) {
3391 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3393 case ArgInFloatSSEReg:
3394 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3396 case ArgInDoubleSSEReg:
3397 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3412 #endif /* DISABLE_JIT */
3415 static int tls_gs_offset;
3419 mono_arch_have_fast_tls (void)
3422 static gboolean have_fast_tls = FALSE;
3423 static gboolean inited = FALSE;
3426 if (mini_get_debug_options ()->use_fallback_tls)
3430 return have_fast_tls;
3432 ins = (guint8*)pthread_getspecific;
3435 * We're looking for these two instructions:
3437 * mov %gs:[offset](,%rdi,8),%rax
3440 have_fast_tls = ins [0] == 0x65 &&
3450 tls_gs_offset = ins[5];
3453 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3454 * For that version we're looking for these instructions:
3458 * mov %gs:[offset](,%rdi,8),%rax
3462 if (!have_fast_tls) {
3463 have_fast_tls = ins [0] == 0x55 &&
3478 tls_gs_offset = ins[9];
3482 return have_fast_tls;
3483 #elif defined(TARGET_ANDROID)
3486 if (mini_get_debug_options ()->use_fallback_tls)
3493 mono_amd64_get_tls_gs_offset (void)
3496 return tls_gs_offset;
3498 g_assert_not_reached ();
3504 * mono_amd64_emit_tls_get:
3505 * @code: buffer to store code to
3506 * @dreg: hard register where to place the result
3507 * @tls_offset: offset info
3509 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3510 * the dreg register the item in the thread local storage identified
3513 * Returns: a pointer to the end of the stored code
3516 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3519 if (tls_offset < 64) {
3520 x86_prefix (code, X86_GS_PREFIX);
3521 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3525 g_assert (tls_offset < 0x440);
3526 /* Load TEB->TlsExpansionSlots */
3527 x86_prefix (code, X86_GS_PREFIX);
3528 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3529 amd64_test_reg_reg (code, dreg, dreg);
3531 amd64_branch (code, X86_CC_EQ, code, TRUE);
3532 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3533 amd64_patch (buf [0], code);
3535 #elif defined(TARGET_MACH)
3536 x86_prefix (code, X86_GS_PREFIX);
3537 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3539 if (optimize_for_xen) {
3540 x86_prefix (code, X86_FS_PREFIX);
3541 amd64_mov_reg_mem (code, dreg, 0, 8);
3542 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3544 x86_prefix (code, X86_FS_PREFIX);
3545 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3552 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3555 g_assert_not_reached ();
3556 #elif defined(TARGET_MACH)
3557 x86_prefix (code, X86_GS_PREFIX);
3558 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3560 g_assert (!optimize_for_xen);
3561 x86_prefix (code, X86_FS_PREFIX);
3562 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3570 * Emit code to initialize an LMF structure at LMF_OFFSET.
3573 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3576 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3579 * sp is saved right before calls but we need to save it here too so
3580 * async stack walks would work.
3582 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3584 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3585 if (cfg->arch.omit_fp && cfa_offset != -1)
3586 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3588 /* These can't contain refs */
3589 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3590 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3591 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3592 /* These are handled automatically by the stack marking code */
3593 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3600 #define TEB_LAST_ERROR_OFFSET 0x068
3603 emit_get_last_error (guint8* code, int dreg)
3605 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3606 x86_prefix (code, X86_GS_PREFIX);
3607 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3615 emit_get_last_error (guint8* code, int dreg)
3617 g_assert_not_reached ();
3622 /* benchmark and set based on cpu */
3623 #define LOOP_ALIGNMENT 8
3624 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3628 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3633 guint8 *code = cfg->native_code + cfg->code_len;
3636 /* Fix max_offset estimate for each successor bb */
3637 if (cfg->opt & MONO_OPT_BRANCH) {
3638 int current_offset = cfg->code_len;
3639 MonoBasicBlock *current_bb;
3640 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3641 current_bb->max_offset = current_offset;
3642 current_offset += current_bb->max_length;
3646 if (cfg->opt & MONO_OPT_LOOP) {
3647 int pad, align = LOOP_ALIGNMENT;
3648 /* set alignment depending on cpu */
3649 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3651 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3652 amd64_padding (code, pad);
3653 cfg->code_len += pad;
3654 bb->native_offset = cfg->code_len;
3658 if (cfg->verbose_level > 2)
3659 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3661 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3662 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3663 g_assert (!cfg->compile_aot);
3665 cov->data [bb->dfn].cil_code = bb->cil_code;
3666 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3667 /* this is not thread save, but good enough */
3668 amd64_inc_membase (code, AMD64_R11, 0);
3671 offset = code - cfg->native_code;
3673 mono_debug_open_block (cfg, bb, offset);
3675 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3676 x86_breakpoint (code);
3678 MONO_BB_FOR_EACH_INS (bb, ins) {
3679 offset = code - cfg->native_code;
3681 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3683 #define EXTRA_CODE_SPACE (16)
3685 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3686 cfg->code_size *= 2;
3687 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3688 code = cfg->native_code + offset;
3689 cfg->stat_code_reallocs++;
3692 if (cfg->debug_info)
3693 mono_debug_record_line_number (cfg, ins, offset);
3695 switch (ins->opcode) {
3697 amd64_mul_reg (code, ins->sreg2, TRUE);
3700 amd64_mul_reg (code, ins->sreg2, FALSE);
3702 case OP_X86_SETEQ_MEMBASE:
3703 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3705 case OP_STOREI1_MEMBASE_IMM:
3706 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3708 case OP_STOREI2_MEMBASE_IMM:
3709 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3711 case OP_STOREI4_MEMBASE_IMM:
3712 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3714 case OP_STOREI1_MEMBASE_REG:
3715 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3717 case OP_STOREI2_MEMBASE_REG:
3718 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3720 /* In AMD64 NaCl, pointers are 4 bytes, */
3721 /* so STORE_* != STOREI8_*. Likewise below. */
3722 case OP_STORE_MEMBASE_REG:
3723 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3725 case OP_STOREI8_MEMBASE_REG:
3726 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3728 case OP_STOREI4_MEMBASE_REG:
3729 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3731 case OP_STORE_MEMBASE_IMM:
3732 /* In NaCl, this could be a PCONST type, which could */
3733 /* mean a pointer type was copied directly into the */
3734 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3735 /* the value would be 0x00000000FFFFFFFF which is */
3736 /* not proper for an imm32 unless you cast it. */
3737 g_assert (amd64_is_imm32 (ins->inst_imm));
3738 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3740 case OP_STOREI8_MEMBASE_IMM:
3741 g_assert (amd64_is_imm32 (ins->inst_imm));
3742 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3745 #ifdef __mono_ilp32__
3746 /* In ILP32, pointers are 4 bytes, so separate these */
3747 /* cases, use literal 8 below where we really want 8 */
3748 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3749 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3753 // FIXME: Decompose this earlier
3754 if (amd64_use_imm32 (ins->inst_imm))
3755 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3757 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3758 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3762 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3763 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3766 // FIXME: Decompose this earlier
3767 if (amd64_use_imm32 (ins->inst_imm))
3768 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3770 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3771 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3775 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3776 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3779 /* For NaCl, pointers are 4 bytes, so separate these */
3780 /* cases, use literal 8 below where we really want 8 */
3781 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3782 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3784 case OP_LOAD_MEMBASE:
3785 g_assert (amd64_is_imm32 (ins->inst_offset));
3786 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3788 case OP_LOADI8_MEMBASE:
3789 /* Use literal 8 instead of sizeof pointer or */
3790 /* register, we really want 8 for this opcode */
3791 g_assert (amd64_is_imm32 (ins->inst_offset));
3792 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3794 case OP_LOADI4_MEMBASE:
3795 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3797 case OP_LOADU4_MEMBASE:
3798 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3800 case OP_LOADU1_MEMBASE:
3801 /* The cpu zero extends the result into 64 bits */
3802 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3804 case OP_LOADI1_MEMBASE:
3805 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3807 case OP_LOADU2_MEMBASE:
3808 /* The cpu zero extends the result into 64 bits */
3809 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3811 case OP_LOADI2_MEMBASE:
3812 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3814 case OP_AMD64_LOADI8_MEMINDEX:
3815 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3817 case OP_LCONV_TO_I1:
3818 case OP_ICONV_TO_I1:
3820 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3822 case OP_LCONV_TO_I2:
3823 case OP_ICONV_TO_I2:
3825 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3827 case OP_LCONV_TO_U1:
3828 case OP_ICONV_TO_U1:
3829 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3831 case OP_LCONV_TO_U2:
3832 case OP_ICONV_TO_U2:
3833 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3836 /* Clean out the upper word */
3837 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3840 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3844 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3846 case OP_COMPARE_IMM:
3847 #if defined(__mono_ilp32__)
3848 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3849 g_assert (amd64_is_imm32 (ins->inst_imm));
3850 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3853 case OP_LCOMPARE_IMM:
3854 g_assert (amd64_is_imm32 (ins->inst_imm));
3855 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3857 case OP_X86_COMPARE_REG_MEMBASE:
3858 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3860 case OP_X86_TEST_NULL:
3861 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3863 case OP_AMD64_TEST_NULL:
3864 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3867 case OP_X86_ADD_REG_MEMBASE:
3868 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3870 case OP_X86_SUB_REG_MEMBASE:
3871 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3873 case OP_X86_AND_REG_MEMBASE:
3874 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3876 case OP_X86_OR_REG_MEMBASE:
3877 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3879 case OP_X86_XOR_REG_MEMBASE:
3880 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3883 case OP_X86_ADD_MEMBASE_IMM:
3884 /* FIXME: Make a 64 version too */
3885 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3887 case OP_X86_SUB_MEMBASE_IMM:
3888 g_assert (amd64_is_imm32 (ins->inst_imm));
3889 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3891 case OP_X86_AND_MEMBASE_IMM:
3892 g_assert (amd64_is_imm32 (ins->inst_imm));
3893 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3895 case OP_X86_OR_MEMBASE_IMM:
3896 g_assert (amd64_is_imm32 (ins->inst_imm));
3897 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3899 case OP_X86_XOR_MEMBASE_IMM:
3900 g_assert (amd64_is_imm32 (ins->inst_imm));
3901 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3903 case OP_X86_ADD_MEMBASE_REG:
3904 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3906 case OP_X86_SUB_MEMBASE_REG:
3907 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3909 case OP_X86_AND_MEMBASE_REG:
3910 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3912 case OP_X86_OR_MEMBASE_REG:
3913 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3915 case OP_X86_XOR_MEMBASE_REG:
3916 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3918 case OP_X86_INC_MEMBASE:
3919 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3921 case OP_X86_INC_REG:
3922 amd64_inc_reg_size (code, ins->dreg, 4);
3924 case OP_X86_DEC_MEMBASE:
3925 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3927 case OP_X86_DEC_REG:
3928 amd64_dec_reg_size (code, ins->dreg, 4);
3930 case OP_X86_MUL_REG_MEMBASE:
3931 case OP_X86_MUL_MEMBASE_REG:
3932 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3934 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3935 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3937 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3938 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3940 case OP_AMD64_COMPARE_MEMBASE_REG:
3941 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3943 case OP_AMD64_COMPARE_MEMBASE_IMM:
3944 g_assert (amd64_is_imm32 (ins->inst_imm));
3945 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3947 case OP_X86_COMPARE_MEMBASE8_IMM:
3948 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3950 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3951 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3953 case OP_AMD64_COMPARE_REG_MEMBASE:
3954 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3957 case OP_AMD64_ADD_REG_MEMBASE:
3958 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3960 case OP_AMD64_SUB_REG_MEMBASE:
3961 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3963 case OP_AMD64_AND_REG_MEMBASE:
3964 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3966 case OP_AMD64_OR_REG_MEMBASE:
3967 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3969 case OP_AMD64_XOR_REG_MEMBASE:
3970 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3973 case OP_AMD64_ADD_MEMBASE_REG:
3974 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3976 case OP_AMD64_SUB_MEMBASE_REG:
3977 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3979 case OP_AMD64_AND_MEMBASE_REG:
3980 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3982 case OP_AMD64_OR_MEMBASE_REG:
3983 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3985 case OP_AMD64_XOR_MEMBASE_REG:
3986 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3989 case OP_AMD64_ADD_MEMBASE_IMM:
3990 g_assert (amd64_is_imm32 (ins->inst_imm));
3991 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3993 case OP_AMD64_SUB_MEMBASE_IMM:
3994 g_assert (amd64_is_imm32 (ins->inst_imm));
3995 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3997 case OP_AMD64_AND_MEMBASE_IMM:
3998 g_assert (amd64_is_imm32 (ins->inst_imm));
3999 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4001 case OP_AMD64_OR_MEMBASE_IMM:
4002 g_assert (amd64_is_imm32 (ins->inst_imm));
4003 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4005 case OP_AMD64_XOR_MEMBASE_IMM:
4006 g_assert (amd64_is_imm32 (ins->inst_imm));
4007 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4011 amd64_breakpoint (code);
4013 case OP_RELAXED_NOP:
4014 x86_prefix (code, X86_REP_PREFIX);
4022 case OP_DUMMY_STORE:
4023 case OP_DUMMY_ICONST:
4024 case OP_DUMMY_R8CONST:
4025 case OP_NOT_REACHED:
4028 case OP_IL_SEQ_POINT:
4029 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4031 case OP_SEQ_POINT: {
4032 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4033 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4036 /* Load ss_tramp_var */
4037 /* This is equal to &ss_trampoline */
4038 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4039 /* Load the trampoline address */
4040 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4041 /* Call it if it is non-null */
4042 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4044 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4045 amd64_call_reg (code, AMD64_R11);
4046 amd64_patch (label, code);
4050 * This is the address which is saved in seq points,
4052 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4054 if (cfg->compile_aot) {
4055 guint32 offset = code - cfg->native_code;
4057 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4061 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4062 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4063 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4064 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4065 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4067 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4068 /* Call the trampoline */
4069 amd64_call_reg (code, AMD64_R11);
4070 amd64_patch (label, code);
4072 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4076 * Emit a test+branch against a constant, the constant will be overwritten
4077 * by mono_arch_set_breakpoint () to cause the test to fail.
4079 amd64_mov_reg_imm (code, AMD64_R11, 0);
4080 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4082 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4085 g_assert (var->opcode == OP_REGOFFSET);
4086 /* Load bp_tramp_var */
4087 /* This is equal to &bp_trampoline */
4088 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4089 /* Call the trampoline */
4090 amd64_call_membase (code, AMD64_R11, 0);
4091 amd64_patch (label, code);
4094 * Add an additional nop so skipping the bp doesn't cause the ip to point
4095 * to another IL offset.
4103 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4106 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4110 g_assert (amd64_is_imm32 (ins->inst_imm));
4111 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4114 g_assert (amd64_is_imm32 (ins->inst_imm));
4115 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4120 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4123 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4127 g_assert (amd64_is_imm32 (ins->inst_imm));
4128 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4131 g_assert (amd64_is_imm32 (ins->inst_imm));
4132 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4135 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4139 g_assert (amd64_is_imm32 (ins->inst_imm));
4140 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4143 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4148 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4150 switch (ins->inst_imm) {
4154 if (ins->dreg != ins->sreg1)
4155 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4156 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4159 /* LEA r1, [r2 + r2*2] */
4160 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4163 /* LEA r1, [r2 + r2*4] */
4164 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4167 /* LEA r1, [r2 + r2*2] */
4169 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4170 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4173 /* LEA r1, [r2 + r2*8] */
4174 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4177 /* LEA r1, [r2 + r2*4] */
4179 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4180 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4183 /* LEA r1, [r2 + r2*2] */
4185 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4186 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4189 /* LEA r1, [r2 + r2*4] */
4190 /* LEA r1, [r1 + r1*4] */
4191 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4192 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4195 /* LEA r1, [r2 + r2*4] */
4197 /* LEA r1, [r1 + r1*4] */
4198 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4199 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4200 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4203 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4210 /* Regalloc magic makes the div/rem cases the same */
4211 if (ins->sreg2 == AMD64_RDX) {
4212 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4214 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4217 amd64_div_reg (code, ins->sreg2, TRUE);
4222 if (ins->sreg2 == AMD64_RDX) {
4223 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4224 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4225 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4227 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4228 amd64_div_reg (code, ins->sreg2, FALSE);
4233 if (ins->sreg2 == AMD64_RDX) {
4234 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4235 amd64_cdq_size (code, 4);
4236 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4238 amd64_cdq_size (code, 4);
4239 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4244 if (ins->sreg2 == AMD64_RDX) {
4245 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4246 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4247 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4249 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4250 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4254 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4255 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4258 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4262 g_assert (amd64_is_imm32 (ins->inst_imm));
4263 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4266 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4270 g_assert (amd64_is_imm32 (ins->inst_imm));
4271 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4274 g_assert (ins->sreg2 == AMD64_RCX);
4275 amd64_shift_reg (code, X86_SHL, ins->dreg);
4278 g_assert (ins->sreg2 == AMD64_RCX);
4279 amd64_shift_reg (code, X86_SAR, ins->dreg);
4283 g_assert (amd64_is_imm32 (ins->inst_imm));
4284 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4287 g_assert (amd64_is_imm32 (ins->inst_imm));
4288 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4290 case OP_LSHR_UN_IMM:
4291 g_assert (amd64_is_imm32 (ins->inst_imm));
4292 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4295 g_assert (ins->sreg2 == AMD64_RCX);
4296 amd64_shift_reg (code, X86_SHR, ins->dreg);
4300 g_assert (amd64_is_imm32 (ins->inst_imm));
4301 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4306 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4309 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4312 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4315 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4319 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4322 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4325 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4328 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4331 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4334 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4337 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4340 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4343 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4346 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4349 amd64_neg_reg_size (code, ins->sreg1, 4);
4352 amd64_not_reg_size (code, ins->sreg1, 4);
4355 g_assert (ins->sreg2 == AMD64_RCX);
4356 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4359 g_assert (ins->sreg2 == AMD64_RCX);
4360 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4363 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4365 case OP_ISHR_UN_IMM:
4366 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4369 g_assert (ins->sreg2 == AMD64_RCX);
4370 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4373 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4376 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4379 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4380 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4382 case OP_IMUL_OVF_UN:
4383 case OP_LMUL_OVF_UN: {
4384 /* the mul operation and the exception check should most likely be split */
4385 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4386 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4387 /*g_assert (ins->sreg2 == X86_EAX);
4388 g_assert (ins->dreg == X86_EAX);*/
4389 if (ins->sreg2 == X86_EAX) {
4390 non_eax_reg = ins->sreg1;
4391 } else if (ins->sreg1 == X86_EAX) {
4392 non_eax_reg = ins->sreg2;
4394 /* no need to save since we're going to store to it anyway */
4395 if (ins->dreg != X86_EAX) {
4397 amd64_push_reg (code, X86_EAX);
4399 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4400 non_eax_reg = ins->sreg2;
4402 if (ins->dreg == X86_EDX) {
4405 amd64_push_reg (code, X86_EAX);
4409 amd64_push_reg (code, X86_EDX);
4411 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4412 /* save before the check since pop and mov don't change the flags */
4413 if (ins->dreg != X86_EAX)
4414 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4416 amd64_pop_reg (code, X86_EDX);
4418 amd64_pop_reg (code, X86_EAX);
4419 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4423 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4425 case OP_ICOMPARE_IMM:
4426 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4448 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4456 case OP_CMOV_INE_UN:
4457 case OP_CMOV_IGE_UN:
4458 case OP_CMOV_IGT_UN:
4459 case OP_CMOV_ILE_UN:
4460 case OP_CMOV_ILT_UN:
4466 case OP_CMOV_LNE_UN:
4467 case OP_CMOV_LGE_UN:
4468 case OP_CMOV_LGT_UN:
4469 case OP_CMOV_LLE_UN:
4470 case OP_CMOV_LLT_UN:
4471 g_assert (ins->dreg == ins->sreg1);
4472 /* This needs to operate on 64 bit values */
4473 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4477 amd64_not_reg (code, ins->sreg1);
4480 amd64_neg_reg (code, ins->sreg1);
4485 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4486 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4488 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4491 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4492 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4495 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4496 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4499 if (ins->dreg != ins->sreg1)
4500 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4502 case OP_AMD64_SET_XMMREG_R4: {
4504 if (ins->dreg != ins->sreg1)
4505 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4507 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4511 case OP_AMD64_SET_XMMREG_R8: {
4512 if (ins->dreg != ins->sreg1)
4513 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4517 MonoCallInst *call = (MonoCallInst*)ins;
4518 int i, save_area_offset;
4520 g_assert (!cfg->method->save_lmf);
4522 /* Restore callee saved registers */
4523 save_area_offset = cfg->arch.reg_save_area_offset;
4524 for (i = 0; i < AMD64_NREG; ++i)
4525 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4526 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4527 save_area_offset += 8;
4530 if (cfg->arch.omit_fp) {
4531 if (cfg->arch.stack_alloc_size)
4532 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4534 if (call->stack_usage)
4537 /* Copy arguments on the stack to our argument area */
4538 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4539 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4540 amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4544 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4545 amd64_pop_reg (code, AMD64_RBP);
4546 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4552 offset = code - cfg->native_code;
4553 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4554 if (cfg->compile_aot)
4555 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4557 amd64_set_reg_template (code, AMD64_R11);
4558 amd64_jump_reg (code, AMD64_R11);
4559 ins->flags |= MONO_INST_GC_CALLSITE;
4560 ins->backend.pc_offset = code - cfg->native_code;
4564 /* ensure ins->sreg1 is not NULL */
4565 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4568 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4569 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4579 call = (MonoCallInst*)ins;
4581 * The AMD64 ABI forces callers to know about varargs.
4583 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4584 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4585 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4587 * Since the unmanaged calling convention doesn't contain a
4588 * 'vararg' entry, we have to treat every pinvoke call as a
4589 * potential vararg call.
4593 for (i = 0; i < AMD64_XMM_NREG; ++i)
4594 if (call->used_fregs & (1 << i))
4597 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4599 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4602 if (ins->flags & MONO_INST_HAS_METHOD)
4603 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4605 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4606 ins->flags |= MONO_INST_GC_CALLSITE;
4607 ins->backend.pc_offset = code - cfg->native_code;
4608 code = emit_move_return_value (cfg, ins, code);
4615 case OP_VOIDCALL_REG:
4617 call = (MonoCallInst*)ins;
4619 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4620 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4621 ins->sreg1 = AMD64_R11;
4625 * The AMD64 ABI forces callers to know about varargs.
4627 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4628 if (ins->sreg1 == AMD64_RAX) {
4629 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4630 ins->sreg1 = AMD64_R11;
4632 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4633 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4635 * Since the unmanaged calling convention doesn't contain a
4636 * 'vararg' entry, we have to treat every pinvoke call as a
4637 * potential vararg call.
4641 for (i = 0; i < AMD64_XMM_NREG; ++i)
4642 if (call->used_fregs & (1 << i))
4644 if (ins->sreg1 == AMD64_RAX) {
4645 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4646 ins->sreg1 = AMD64_R11;
4649 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4651 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4654 amd64_call_reg (code, ins->sreg1);
4655 ins->flags |= MONO_INST_GC_CALLSITE;
4656 ins->backend.pc_offset = code - cfg->native_code;
4657 code = emit_move_return_value (cfg, ins, code);
4659 case OP_FCALL_MEMBASE:
4660 case OP_RCALL_MEMBASE:
4661 case OP_LCALL_MEMBASE:
4662 case OP_VCALL_MEMBASE:
4663 case OP_VCALL2_MEMBASE:
4664 case OP_VOIDCALL_MEMBASE:
4665 case OP_CALL_MEMBASE:
4666 call = (MonoCallInst*)ins;
4668 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4669 ins->flags |= MONO_INST_GC_CALLSITE;
4670 ins->backend.pc_offset = code - cfg->native_code;
4671 code = emit_move_return_value (cfg, ins, code);
4675 MonoInst *var = cfg->dyn_call_var;
4678 g_assert (var->opcode == OP_REGOFFSET);
4680 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4681 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4683 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4685 /* Save args buffer */
4686 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4688 /* Set fp arg regs */
4689 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4690 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4692 amd64_branch8 (code, X86_CC_Z, -1, 1);
4693 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4694 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4695 amd64_patch (label, code);
4697 /* Set stack args */
4698 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4699 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4700 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4703 /* Set argument registers */
4704 for (i = 0; i < PARAM_REGS; ++i)
4705 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4708 amd64_call_reg (code, AMD64_R10);
4710 ins->flags |= MONO_INST_GC_CALLSITE;
4711 ins->backend.pc_offset = code - cfg->native_code;
4714 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4715 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4716 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4717 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4720 case OP_AMD64_SAVE_SP_TO_LMF: {
4721 MonoInst *lmf_var = cfg->lmf_var;
4722 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4726 g_assert_not_reached ();
4727 amd64_push_reg (code, ins->sreg1);
4729 case OP_X86_PUSH_IMM:
4730 g_assert_not_reached ();
4731 g_assert (amd64_is_imm32 (ins->inst_imm));
4732 amd64_push_imm (code, ins->inst_imm);
4734 case OP_X86_PUSH_MEMBASE:
4735 g_assert_not_reached ();
4736 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4738 case OP_X86_PUSH_OBJ: {
4739 int size = ALIGN_TO (ins->inst_imm, 8);
4741 g_assert_not_reached ();
4743 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4744 amd64_push_reg (code, AMD64_RDI);
4745 amd64_push_reg (code, AMD64_RSI);
4746 amd64_push_reg (code, AMD64_RCX);
4747 if (ins->inst_offset)
4748 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4750 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4751 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4752 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4754 amd64_prefix (code, X86_REP_PREFIX);
4756 amd64_pop_reg (code, AMD64_RCX);
4757 amd64_pop_reg (code, AMD64_RSI);
4758 amd64_pop_reg (code, AMD64_RDI);
4761 case OP_GENERIC_CLASS_INIT: {
4764 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4766 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4768 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4770 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4771 ins->flags |= MONO_INST_GC_CALLSITE;
4772 ins->backend.pc_offset = code - cfg->native_code;
4774 x86_patch (jump, code);
4779 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4781 case OP_X86_LEA_MEMBASE:
4782 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4785 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4788 /* keep alignment */
4789 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4790 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4791 code = mono_emit_stack_alloc (cfg, code, ins);
4792 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4793 if (cfg->param_area)
4794 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4796 case OP_LOCALLOC_IMM: {
4797 guint32 size = ins->inst_imm;
4798 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4800 if (ins->flags & MONO_INST_INIT) {
4804 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4805 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4807 for (i = 0; i < size; i += 8)
4808 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4809 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4811 amd64_mov_reg_imm (code, ins->dreg, size);
4812 ins->sreg1 = ins->dreg;
4814 code = mono_emit_stack_alloc (cfg, code, ins);
4815 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4818 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4819 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4821 if (cfg->param_area)
4822 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4826 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4827 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4828 (gpointer)"mono_arch_throw_exception", FALSE);
4829 ins->flags |= MONO_INST_GC_CALLSITE;
4830 ins->backend.pc_offset = code - cfg->native_code;
4834 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4835 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4836 (gpointer)"mono_arch_rethrow_exception", FALSE);
4837 ins->flags |= MONO_INST_GC_CALLSITE;
4838 ins->backend.pc_offset = code - cfg->native_code;
4841 case OP_CALL_HANDLER:
4843 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4844 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4845 amd64_call_imm (code, 0);
4846 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4847 /* Restore stack alignment */
4848 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4850 case OP_START_HANDLER: {
4851 /* Even though we're saving RSP, use sizeof */
4852 /* gpointer because spvar is of type IntPtr */
4853 /* see: mono_create_spvar_for_region */
4854 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4855 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4857 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4858 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4860 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4864 case OP_ENDFINALLY: {
4865 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4866 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4870 case OP_ENDFILTER: {
4871 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4872 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4873 /* The local allocator will put the result into RAX */
4878 if (ins->dreg != AMD64_RAX)
4879 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4882 ins->inst_c0 = code - cfg->native_code;
4885 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4886 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4888 if (ins->inst_target_bb->native_offset) {
4889 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4891 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4892 if ((cfg->opt & MONO_OPT_BRANCH) &&
4893 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4894 x86_jump8 (code, 0);
4896 x86_jump32 (code, 0);
4900 amd64_jump_reg (code, ins->sreg1);
4923 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4924 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4926 case OP_COND_EXC_EQ:
4927 case OP_COND_EXC_NE_UN:
4928 case OP_COND_EXC_LT:
4929 case OP_COND_EXC_LT_UN:
4930 case OP_COND_EXC_GT:
4931 case OP_COND_EXC_GT_UN:
4932 case OP_COND_EXC_GE:
4933 case OP_COND_EXC_GE_UN:
4934 case OP_COND_EXC_LE:
4935 case OP_COND_EXC_LE_UN:
4936 case OP_COND_EXC_IEQ:
4937 case OP_COND_EXC_INE_UN:
4938 case OP_COND_EXC_ILT:
4939 case OP_COND_EXC_ILT_UN:
4940 case OP_COND_EXC_IGT:
4941 case OP_COND_EXC_IGT_UN:
4942 case OP_COND_EXC_IGE:
4943 case OP_COND_EXC_IGE_UN:
4944 case OP_COND_EXC_ILE:
4945 case OP_COND_EXC_ILE_UN:
4946 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4948 case OP_COND_EXC_OV:
4949 case OP_COND_EXC_NO:
4951 case OP_COND_EXC_NC:
4952 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4953 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4955 case OP_COND_EXC_IOV:
4956 case OP_COND_EXC_INO:
4957 case OP_COND_EXC_IC:
4958 case OP_COND_EXC_INC:
4959 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4960 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4963 /* floating point opcodes */
4965 double d = *(double *)ins->inst_p0;
4967 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4968 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4971 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4972 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4977 float f = *(float *)ins->inst_p0;
4979 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4981 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4983 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4986 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4987 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4989 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4993 case OP_STORER8_MEMBASE_REG:
4994 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4996 case OP_LOADR8_MEMBASE:
4997 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4999 case OP_STORER4_MEMBASE_REG:
5001 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5003 /* This requires a double->single conversion */
5004 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5005 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5008 case OP_LOADR4_MEMBASE:
5010 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5012 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5013 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5016 case OP_ICONV_TO_R4:
5018 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5020 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5021 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5024 case OP_ICONV_TO_R8:
5025 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5027 case OP_LCONV_TO_R4:
5029 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5031 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5032 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5035 case OP_LCONV_TO_R8:
5036 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5038 case OP_FCONV_TO_R4:
5040 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5042 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5043 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5046 case OP_FCONV_TO_I1:
5047 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5049 case OP_FCONV_TO_U1:
5050 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5052 case OP_FCONV_TO_I2:
5053 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5055 case OP_FCONV_TO_U2:
5056 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5058 case OP_FCONV_TO_U4:
5059 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5061 case OP_FCONV_TO_I4:
5063 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5065 case OP_FCONV_TO_I8:
5066 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5069 case OP_RCONV_TO_I1:
5070 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5071 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5073 case OP_RCONV_TO_U1:
5074 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5075 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5077 case OP_RCONV_TO_I2:
5078 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5079 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5081 case OP_RCONV_TO_U2:
5082 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5083 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5085 case OP_RCONV_TO_I4:
5086 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5088 case OP_RCONV_TO_U4:
5089 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5091 case OP_RCONV_TO_I8:
5092 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5094 case OP_RCONV_TO_R8:
5095 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5097 case OP_RCONV_TO_R4:
5098 if (ins->dreg != ins->sreg1)
5099 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5102 case OP_LCONV_TO_R_UN: {
5105 /* Based on gcc code */
5106 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5107 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5110 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5111 br [1] = code; x86_jump8 (code, 0);
5112 amd64_patch (br [0], code);
5115 /* Save to the red zone */
5116 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5117 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5118 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5119 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5120 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5121 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5122 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5123 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5124 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5126 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5127 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5128 amd64_patch (br [1], code);
5131 case OP_LCONV_TO_OVF_U4:
5132 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5133 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5134 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5136 case OP_LCONV_TO_OVF_I4_UN:
5137 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5138 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5139 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5142 if (ins->dreg != ins->sreg1)
5143 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5146 if (ins->dreg != ins->sreg1)
5147 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5149 case OP_MOVE_F_TO_I4:
5151 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5153 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5154 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5157 case OP_MOVE_I4_TO_F:
5158 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5160 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5162 case OP_MOVE_F_TO_I8:
5163 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5165 case OP_MOVE_I8_TO_F:
5166 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5169 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5172 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5175 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5178 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5181 static double r8_0 = -0.0;
5183 g_assert (ins->sreg1 == ins->dreg);
5185 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5186 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5190 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5193 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5196 static guint64 d = 0x7fffffffffffffffUL;
5198 g_assert (ins->sreg1 == ins->dreg);
5200 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5201 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5205 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5209 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5212 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5215 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5218 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5221 static float r4_0 = -0.0;
5223 g_assert (ins->sreg1 == ins->dreg);
5225 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5226 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5227 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5232 g_assert (cfg->opt & MONO_OPT_CMOV);
5233 g_assert (ins->dreg == ins->sreg1);
5234 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5235 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5238 g_assert (cfg->opt & MONO_OPT_CMOV);
5239 g_assert (ins->dreg == ins->sreg1);
5240 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5241 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5244 g_assert (cfg->opt & MONO_OPT_CMOV);
5245 g_assert (ins->dreg == ins->sreg1);
5246 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5247 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5250 g_assert (cfg->opt & MONO_OPT_CMOV);
5251 g_assert (ins->dreg == ins->sreg1);
5252 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5253 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5256 g_assert (cfg->opt & MONO_OPT_CMOV);
5257 g_assert (ins->dreg == ins->sreg1);
5258 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5259 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5262 g_assert (cfg->opt & MONO_OPT_CMOV);
5263 g_assert (ins->dreg == ins->sreg1);
5264 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5265 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5268 g_assert (cfg->opt & MONO_OPT_CMOV);
5269 g_assert (ins->dreg == ins->sreg1);
5270 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5271 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5274 g_assert (cfg->opt & MONO_OPT_CMOV);
5275 g_assert (ins->dreg == ins->sreg1);
5276 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5277 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5283 * The two arguments are swapped because the fbranch instructions
5284 * depend on this for the non-sse case to work.
5286 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5290 * FIXME: Get rid of this.
5291 * The two arguments are swapped because the fbranch instructions
5292 * depend on this for the non-sse case to work.
5294 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5298 /* zeroing the register at the start results in
5299 * shorter and faster code (we can also remove the widening op)
5301 guchar *unordered_check;
5303 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5304 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5305 unordered_check = code;
5306 x86_branch8 (code, X86_CC_P, 0, FALSE);
5308 if (ins->opcode == OP_FCEQ) {
5309 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5310 amd64_patch (unordered_check, code);
5312 guchar *jump_to_end;
5313 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5315 x86_jump8 (code, 0);
5316 amd64_patch (unordered_check, code);
5317 amd64_inc_reg (code, ins->dreg);
5318 amd64_patch (jump_to_end, code);
5324 /* zeroing the register at the start results in
5325 * shorter and faster code (we can also remove the widening op)
5327 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5328 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5329 if (ins->opcode == OP_FCLT_UN) {
5330 guchar *unordered_check = code;
5331 guchar *jump_to_end;
5332 x86_branch8 (code, X86_CC_P, 0, FALSE);
5333 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5335 x86_jump8 (code, 0);
5336 amd64_patch (unordered_check, code);
5337 amd64_inc_reg (code, ins->dreg);
5338 amd64_patch (jump_to_end, code);
5340 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5345 guchar *unordered_check;
5346 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5347 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5348 unordered_check = code;
5349 x86_branch8 (code, X86_CC_P, 0, FALSE);
5350 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5351 amd64_patch (unordered_check, code);
5356 /* zeroing the register at the start results in
5357 * shorter and faster code (we can also remove the widening op)
5359 guchar *unordered_check;
5361 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5362 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5363 if (ins->opcode == OP_FCGT) {
5364 unordered_check = code;
5365 x86_branch8 (code, X86_CC_P, 0, FALSE);
5366 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5367 amd64_patch (unordered_check, code);
5369 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5374 guchar *unordered_check;
5375 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5376 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5377 unordered_check = code;
5378 x86_branch8 (code, X86_CC_P, 0, FALSE);
5379 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5380 amd64_patch (unordered_check, code);
5390 gboolean unordered = FALSE;
5392 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5393 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5395 switch (ins->opcode) {
5397 x86_cond = X86_CC_EQ;
5400 x86_cond = X86_CC_LT;
5403 x86_cond = X86_CC_GT;
5406 x86_cond = X86_CC_GT;
5410 x86_cond = X86_CC_LT;
5414 g_assert_not_reached ();
5419 guchar *unordered_check;
5420 guchar *jump_to_end;
5422 unordered_check = code;
5423 x86_branch8 (code, X86_CC_P, 0, FALSE);
5424 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5426 x86_jump8 (code, 0);
5427 amd64_patch (unordered_check, code);
5428 amd64_inc_reg (code, ins->dreg);
5429 amd64_patch (jump_to_end, code);
5431 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5435 case OP_FCLT_MEMBASE:
5436 case OP_FCGT_MEMBASE:
5437 case OP_FCLT_UN_MEMBASE:
5438 case OP_FCGT_UN_MEMBASE:
5439 case OP_FCEQ_MEMBASE: {
5440 guchar *unordered_check, *jump_to_end;
5443 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5444 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5446 switch (ins->opcode) {
5447 case OP_FCEQ_MEMBASE:
5448 x86_cond = X86_CC_EQ;
5450 case OP_FCLT_MEMBASE:
5451 case OP_FCLT_UN_MEMBASE:
5452 x86_cond = X86_CC_LT;
5454 case OP_FCGT_MEMBASE:
5455 case OP_FCGT_UN_MEMBASE:
5456 x86_cond = X86_CC_GT;
5459 g_assert_not_reached ();
5462 unordered_check = code;
5463 x86_branch8 (code, X86_CC_P, 0, FALSE);
5464 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5466 switch (ins->opcode) {
5467 case OP_FCEQ_MEMBASE:
5468 case OP_FCLT_MEMBASE:
5469 case OP_FCGT_MEMBASE:
5470 amd64_patch (unordered_check, code);
5472 case OP_FCLT_UN_MEMBASE:
5473 case OP_FCGT_UN_MEMBASE:
5475 x86_jump8 (code, 0);
5476 amd64_patch (unordered_check, code);
5477 amd64_inc_reg (code, ins->dreg);
5478 amd64_patch (jump_to_end, code);
5486 guchar *jump = code;
5487 x86_branch8 (code, X86_CC_P, 0, TRUE);
5488 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5489 amd64_patch (jump, code);
5493 /* Branch if C013 != 100 */
5494 /* branch if !ZF or (PF|CF) */
5495 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5496 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5497 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5500 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5503 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5504 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5508 if (ins->opcode == OP_FBGT) {
5511 /* skip branch if C1=1 */
5513 x86_branch8 (code, X86_CC_P, 0, FALSE);
5514 /* branch if (C0 | C3) = 1 */
5515 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5516 amd64_patch (br1, code);
5519 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5523 /* Branch if C013 == 100 or 001 */
5526 /* skip branch if C1=1 */
5528 x86_branch8 (code, X86_CC_P, 0, FALSE);
5529 /* branch if (C0 | C3) = 1 */
5530 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5531 amd64_patch (br1, code);
5535 /* Branch if C013 == 000 */
5536 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5539 /* Branch if C013=000 or 100 */
5542 /* skip branch if C1=1 */
5544 x86_branch8 (code, X86_CC_P, 0, FALSE);
5545 /* branch if C0=0 */
5546 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5547 amd64_patch (br1, code);
5551 /* Branch if C013 != 001 */
5552 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5553 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5556 /* Transfer value to the fp stack */
5557 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5558 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5559 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5561 amd64_push_reg (code, AMD64_RAX);
5563 amd64_fnstsw (code);
5564 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5565 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5566 amd64_pop_reg (code, AMD64_RAX);
5567 amd64_fstp (code, 0);
5568 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5569 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5572 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5576 code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5579 case OP_MEMORY_BARRIER: {
5580 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5584 case OP_ATOMIC_ADD_I4:
5585 case OP_ATOMIC_ADD_I8: {
5586 int dreg = ins->dreg;
5587 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5589 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5592 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5593 amd64_prefix (code, X86_LOCK_PREFIX);
5594 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5595 /* dreg contains the old value, add with sreg2 value */
5596 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5598 if (ins->dreg != dreg)
5599 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5603 case OP_ATOMIC_EXCHANGE_I4:
5604 case OP_ATOMIC_EXCHANGE_I8: {
5605 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5607 /* LOCK prefix is implied. */
5608 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5609 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5610 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5613 case OP_ATOMIC_CAS_I4:
5614 case OP_ATOMIC_CAS_I8: {
5617 if (ins->opcode == OP_ATOMIC_CAS_I8)
5623 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5624 * an explanation of how this works.
5626 g_assert (ins->sreg3 == AMD64_RAX);
5627 g_assert (ins->sreg1 != AMD64_RAX);
5628 g_assert (ins->sreg1 != ins->sreg2);
5630 amd64_prefix (code, X86_LOCK_PREFIX);
5631 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5633 if (ins->dreg != AMD64_RAX)
5634 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5637 case OP_ATOMIC_LOAD_I1: {
5638 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5641 case OP_ATOMIC_LOAD_U1: {
5642 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5645 case OP_ATOMIC_LOAD_I2: {
5646 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5649 case OP_ATOMIC_LOAD_U2: {
5650 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5653 case OP_ATOMIC_LOAD_I4: {
5654 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5657 case OP_ATOMIC_LOAD_U4:
5658 case OP_ATOMIC_LOAD_I8:
5659 case OP_ATOMIC_LOAD_U8: {
5660 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5663 case OP_ATOMIC_LOAD_R4: {
5664 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5665 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5668 case OP_ATOMIC_LOAD_R8: {
5669 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5672 case OP_ATOMIC_STORE_I1:
5673 case OP_ATOMIC_STORE_U1:
5674 case OP_ATOMIC_STORE_I2:
5675 case OP_ATOMIC_STORE_U2:
5676 case OP_ATOMIC_STORE_I4:
5677 case OP_ATOMIC_STORE_U4:
5678 case OP_ATOMIC_STORE_I8:
5679 case OP_ATOMIC_STORE_U8: {
5682 switch (ins->opcode) {
5683 case OP_ATOMIC_STORE_I1:
5684 case OP_ATOMIC_STORE_U1:
5687 case OP_ATOMIC_STORE_I2:
5688 case OP_ATOMIC_STORE_U2:
5691 case OP_ATOMIC_STORE_I4:
5692 case OP_ATOMIC_STORE_U4:
5695 case OP_ATOMIC_STORE_I8:
5696 case OP_ATOMIC_STORE_U8:
5701 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5703 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5707 case OP_ATOMIC_STORE_R4: {
5708 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5709 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5711 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5715 case OP_ATOMIC_STORE_R8: {
5718 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5722 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5726 case OP_CARD_TABLE_WBARRIER: {
5727 int ptr = ins->sreg1;
5728 int value = ins->sreg2;
5730 int nursery_shift, card_table_shift;
5731 gpointer card_table_mask;
5732 size_t nursery_size;
5734 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5735 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5736 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5738 /*If either point to the stack we can simply avoid the WB. This happens due to
5739 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5741 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5745 * We need one register we can clobber, we choose EDX and make sreg1
5746 * fixed EAX to work around limitations in the local register allocator.
5747 * sreg2 might get allocated to EDX, but that is not a problem since
5748 * we use it before clobbering EDX.
5750 g_assert (ins->sreg1 == AMD64_RAX);
5753 * This is the code we produce:
5756 * edx >>= nursery_shift
5757 * cmp edx, (nursery_start >> nursery_shift)
5760 * edx >>= card_table_shift
5766 if (mono_gc_card_table_nursery_check ()) {
5767 if (value != AMD64_RDX)
5768 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5769 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5770 if (shifted_nursery_start >> 31) {
5772 * The value we need to compare against is 64 bits, so we need
5773 * another spare register. We use RBX, which we save and
5776 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5777 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5778 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5779 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5781 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5783 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5785 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5786 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5787 if (card_table_mask)
5788 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5790 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5791 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5793 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5795 if (mono_gc_card_table_nursery_check ())
5796 x86_patch (br, code);
5799 #ifdef MONO_ARCH_SIMD_INTRINSICS
5800 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5802 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5805 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5808 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5811 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5814 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5817 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5820 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5821 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5824 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5827 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5830 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5833 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5836 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5839 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5842 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5845 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5848 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5851 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5854 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5857 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5860 case OP_PSHUFLEW_HIGH:
5861 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5862 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5864 case OP_PSHUFLEW_LOW:
5865 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5866 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5869 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5870 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5873 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5874 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5877 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5878 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5882 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5885 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5888 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5891 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5894 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5897 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5901 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5904 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5907 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5910 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5913 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5916 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5919 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5922 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5925 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5928 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5931 case OP_EXTRACT_MASK:
5932 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5936 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5939 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5942 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5946 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5949 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5952 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5955 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5959 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5962 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5965 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5968 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5972 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5975 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5978 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5982 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5985 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5988 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5992 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5995 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5999 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6005 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6019 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6022 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6025 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6028 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6032 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6035 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6038 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6041 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6044 case OP_PSUM_ABS_DIFF:
6045 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6048 case OP_UNPACK_LOWB:
6049 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6051 case OP_UNPACK_LOWW:
6052 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6054 case OP_UNPACK_LOWD:
6055 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6057 case OP_UNPACK_LOWQ:
6058 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6060 case OP_UNPACK_LOWPS:
6061 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6063 case OP_UNPACK_LOWPD:
6064 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6067 case OP_UNPACK_HIGHB:
6068 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6070 case OP_UNPACK_HIGHW:
6071 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6073 case OP_UNPACK_HIGHD:
6074 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6076 case OP_UNPACK_HIGHQ:
6077 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6079 case OP_UNPACK_HIGHPS:
6080 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6082 case OP_UNPACK_HIGHPD:
6083 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6087 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6090 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6093 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6096 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6099 case OP_PADDB_SAT_UN:
6100 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6102 case OP_PSUBB_SAT_UN:
6103 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6105 case OP_PADDW_SAT_UN:
6106 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6108 case OP_PSUBW_SAT_UN:
6109 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6113 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6116 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6119 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6122 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6126 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6129 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6132 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6134 case OP_PMULW_HIGH_UN:
6135 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6138 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6142 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6145 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6149 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6152 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6156 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6159 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6163 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6166 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6170 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6173 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6177 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6180 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6184 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6187 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6190 /*TODO: This is appart of the sse spec but not added
6192 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6195 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6200 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6203 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6206 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6209 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6212 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6215 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6218 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6221 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6224 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6227 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6231 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6234 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6238 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6239 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6241 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6246 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6248 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6249 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6253 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6255 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6256 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6257 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6261 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6263 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6266 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6268 case OP_EXTRACTX_U2:
6269 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6271 case OP_INSERTX_U1_SLOW:
6272 /*sreg1 is the extracted ireg (scratch)
6273 /sreg2 is the to be inserted ireg (scratch)
6274 /dreg is the xreg to receive the value*/
6276 /*clear the bits from the extracted word*/
6277 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6278 /*shift the value to insert if needed*/
6279 if (ins->inst_c0 & 1)
6280 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6281 /*join them together*/
6282 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6283 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6285 case OP_INSERTX_I4_SLOW:
6286 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6287 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6288 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6290 case OP_INSERTX_I8_SLOW:
6291 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6293 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6295 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6298 case OP_INSERTX_R4_SLOW:
6299 switch (ins->inst_c0) {
6302 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6304 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6307 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6309 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6311 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6312 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6315 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6317 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6319 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6320 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6323 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6325 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6327 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6328 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6332 case OP_INSERTX_R8_SLOW:
6334 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6336 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6338 case OP_STOREX_MEMBASE_REG:
6339 case OP_STOREX_MEMBASE:
6340 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6342 case OP_LOADX_MEMBASE:
6343 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6345 case OP_LOADX_ALIGNED_MEMBASE:
6346 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6348 case OP_STOREX_ALIGNED_MEMBASE_REG:
6349 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6351 case OP_STOREX_NTA_MEMBASE_REG:
6352 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6354 case OP_PREFETCH_MEMBASE:
6355 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6359 /*FIXME the peephole pass should have killed this*/
6360 if (ins->dreg != ins->sreg1)
6361 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6364 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6367 amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6369 case OP_ICONV_TO_R4_RAW:
6370 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6372 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6375 case OP_FCONV_TO_R8_X:
6376 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6379 case OP_XCONV_R8_TO_I4:
6380 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6381 switch (ins->backend.source_opcode) {
6382 case OP_FCONV_TO_I1:
6383 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6385 case OP_FCONV_TO_U1:
6386 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6388 case OP_FCONV_TO_I2:
6389 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6391 case OP_FCONV_TO_U2:
6392 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6398 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6399 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6400 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6403 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6404 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6407 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6408 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6412 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6414 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6415 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6417 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6420 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6421 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6424 case OP_LIVERANGE_START: {
6425 if (cfg->verbose_level > 1)
6426 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6427 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6430 case OP_LIVERANGE_END: {
6431 if (cfg->verbose_level > 1)
6432 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6433 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6436 case OP_GC_SAFE_POINT: {
6439 g_assert (mono_threads_is_coop_enabled ());
6441 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6442 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6443 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6444 amd64_patch (br[0], code);
6448 case OP_GC_LIVENESS_DEF:
6449 case OP_GC_LIVENESS_USE:
6450 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6451 ins->backend.pc_offset = code - cfg->native_code;
6453 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6454 ins->backend.pc_offset = code - cfg->native_code;
6455 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6457 case OP_GET_LAST_ERROR:
6458 emit_get_last_error(code, ins->dreg);
6461 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6462 g_assert_not_reached ();
6465 if ((code - cfg->native_code - offset) > max_len) {
6466 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6467 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6468 g_assert_not_reached ();
6472 cfg->code_len = code - cfg->native_code;
6475 #endif /* DISABLE_JIT */
6478 mono_arch_register_lowlevel_calls (void)
6480 /* The signature doesn't matter */
6481 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6483 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6485 extern void __chkstk (void);
6486 mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6488 extern void ___chkstk_ms (void);
6489 mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6495 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6497 unsigned char *ip = ji->ip.i + code;
6500 * Debug code to help track down problems where the target of a near call is
6503 if (amd64_is_near_call (ip)) {
6504 gint64 disp = (guint8*)target - (guint8*)ip;
6506 if (!amd64_is_imm32 (disp)) {
6507 printf ("TYPE: %d\n", ji->type);
6509 case MONO_PATCH_INFO_INTERNAL_METHOD:
6510 printf ("V: %s\n", ji->data.name);
6512 case MONO_PATCH_INFO_METHOD_JUMP:
6513 case MONO_PATCH_INFO_METHOD:
6514 printf ("V: %s\n", ji->data.method->name);
6522 amd64_patch (ip, (gpointer)target);
6528 get_max_epilog_size (MonoCompile *cfg)
6530 int max_epilog_size = 16;
6532 if (cfg->method->save_lmf)
6533 max_epilog_size += 256;
6535 if (mono_jit_trace_calls != NULL)
6536 max_epilog_size += 50;
6538 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6539 max_epilog_size += 50;
6541 max_epilog_size += (AMD64_NREG * 2);
6543 return max_epilog_size;
6547 * This macro is used for testing whenever the unwinder works correctly at every point
6548 * where an async exception can happen.
6550 /* This will generate a SIGSEGV at the given point in the code */
6551 #define async_exc_point(code) do { \
6552 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6553 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6554 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6555 cfg->arch.async_point_count ++; \
6561 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6563 int cfa_offset = *cfa_offset_input;
6565 /* Allocate windows stack frame using stack probing method */
6568 if (alloc_size >= 0x1000) {
6569 amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6570 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6573 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6574 if (cfg->arch.omit_fp) {
6575 cfa_offset += alloc_size;
6576 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6577 async_exc_point (code);
6580 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6581 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6582 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6583 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6584 // that will retrieve the expected results.
6585 if (cfg->arch.omit_fp)
6586 mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6589 *cfa_offset_input = cfa_offset;
6592 #endif /* TARGET_WIN32 */
6595 mono_arch_emit_prolog (MonoCompile *cfg)
6597 MonoMethod *method = cfg->method;
6599 MonoMethodSignature *sig;
6601 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6604 MonoInst *lmf_var = cfg->lmf_var;
6605 gboolean args_clobbered = FALSE;
6606 gboolean trace = FALSE;
6608 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6610 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6612 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6615 /* Amount of stack space allocated by register saving code */
6618 /* Offset between RSP and the CFA */
6622 * The prolog consists of the following parts:
6626 * - save callee saved regs using moves
6628 * - save rgctx if needed
6629 * - save lmf if needed
6632 * - save rgctx if needed
6633 * - save lmf if needed
6634 * - save callee saved regs using moves
6639 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6640 // IP saved at CFA - 8
6641 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6642 async_exc_point (code);
6643 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6645 if (!cfg->arch.omit_fp) {
6646 amd64_push_reg (code, AMD64_RBP);
6648 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6649 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6650 async_exc_point (code);
6651 /* These are handled automatically by the stack marking code */
6652 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6654 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6655 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6656 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6657 async_exc_point (code);
6660 /* The param area is always at offset 0 from sp */
6661 /* This needs to be allocated here, since it has to come after the spill area */
6662 if (cfg->param_area) {
6663 if (cfg->arch.omit_fp)
6665 g_assert_not_reached ();
6666 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6669 if (cfg->arch.omit_fp) {
6671 * On enter, the stack is misaligned by the pushing of the return
6672 * address. It is either made aligned by the pushing of %rbp, or by
6675 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6676 if ((alloc_size % 16) == 0) {
6678 /* Mark the padding slot as NOREF */
6679 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6682 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6683 if (cfg->stack_offset != alloc_size) {
6684 /* Mark the padding slot as NOREF */
6685 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6687 cfg->arch.sp_fp_offset = alloc_size;
6691 cfg->arch.stack_alloc_size = alloc_size;
6693 /* Allocate stack frame */
6695 code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6698 /* See mono_emit_stack_alloc */
6699 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6700 guint32 remaining_size = alloc_size;
6701 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6702 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6703 guint32 offset = code - cfg->native_code;
6704 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6705 while (required_code_size >= (cfg->code_size - offset))
6706 cfg->code_size *= 2;
6707 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6708 code = cfg->native_code + offset;
6709 cfg->stat_code_reallocs++;
6712 while (remaining_size >= 0x1000) {
6713 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6714 if (cfg->arch.omit_fp) {
6715 cfa_offset += 0x1000;
6716 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6718 async_exc_point (code);
6720 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6721 remaining_size -= 0x1000;
6723 if (remaining_size) {
6724 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6725 if (cfg->arch.omit_fp) {
6726 cfa_offset += remaining_size;
6727 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6728 async_exc_point (code);
6732 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6733 if (cfg->arch.omit_fp) {
6734 cfa_offset += alloc_size;
6735 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6736 async_exc_point (code);
6742 /* Stack alignment check */
6747 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6748 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6749 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6751 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6752 amd64_breakpoint (code);
6753 amd64_patch (buf, code);
6757 if (mini_get_debug_options ()->init_stacks) {
6758 /* Fill the stack frame with a dummy value to force deterministic behavior */
6760 /* Save registers to the red zone */
6761 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6762 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6764 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6765 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6766 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6769 amd64_prefix (code, X86_REP_PREFIX);
6772 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6773 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6777 if (method->save_lmf)
6778 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6780 /* Save callee saved registers */
6781 if (cfg->arch.omit_fp) {
6782 save_area_offset = cfg->arch.reg_save_area_offset;
6783 /* Save caller saved registers after sp is adjusted */
6784 /* The registers are saved at the bottom of the frame */
6785 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6787 /* The registers are saved just below the saved rbp */
6788 save_area_offset = cfg->arch.reg_save_area_offset;
6791 for (i = 0; i < AMD64_NREG; ++i) {
6792 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6793 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6795 if (cfg->arch.omit_fp) {
6796 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6797 /* These are handled automatically by the stack marking code */
6798 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6800 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6804 save_area_offset += 8;
6805 async_exc_point (code);
6809 /* store runtime generic context */
6810 if (cfg->rgctx_var) {
6811 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6812 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6814 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6816 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6817 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6820 /* compute max_length in order to use short forward jumps */
6821 max_epilog_size = get_max_epilog_size (cfg);
6822 if (cfg->opt & MONO_OPT_BRANCH) {
6823 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6827 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6829 /* max alignment for loops */
6830 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6831 max_length += LOOP_ALIGNMENT;
6833 MONO_BB_FOR_EACH_INS (bb, ins) {
6834 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6837 /* Take prolog and epilog instrumentation into account */
6838 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6839 max_length += max_epilog_size;
6841 bb->max_length = max_length;
6845 sig = mono_method_signature (method);
6848 cinfo = (CallInfo *)cfg->arch.cinfo;
6850 if (sig->ret->type != MONO_TYPE_VOID) {
6851 /* Save volatile arguments to the stack */
6852 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6853 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6856 /* Keep this in sync with emit_load_volatile_arguments */
6857 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6858 ArgInfo *ainfo = cinfo->args + i;
6860 ins = cfg->args [i];
6862 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6863 /* Unused arguments */
6866 /* Save volatile arguments to the stack */
6867 if (ins->opcode != OP_REGVAR) {
6868 switch (ainfo->storage) {
6874 if (stack_offset & 0x1)
6876 else if (stack_offset & 0x2)
6878 else if (stack_offset & 0x4)
6883 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6886 * Save the original location of 'this',
6887 * get_generic_info_from_stack_frame () needs this to properly look up
6888 * the argument value during the handling of async exceptions.
6890 if (ins == cfg->args [0]) {
6891 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6892 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6896 case ArgInFloatSSEReg:
6897 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6899 case ArgInDoubleSSEReg:
6900 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6902 case ArgValuetypeInReg:
6903 for (quad = 0; quad < 2; quad ++) {
6904 switch (ainfo->pair_storage [quad]) {
6906 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6908 case ArgInFloatSSEReg:
6909 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6911 case ArgInDoubleSSEReg:
6912 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6917 g_assert_not_reached ();
6921 case ArgValuetypeAddrInIReg:
6922 if (ainfo->pair_storage [0] == ArgInIReg)
6923 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6925 case ArgValuetypeAddrOnStack:
6927 case ArgGSharedVtInReg:
6928 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6934 /* Argument allocated to (non-volatile) register */
6935 switch (ainfo->storage) {
6937 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6940 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6943 g_assert_not_reached ();
6946 if (ins == cfg->args [0]) {
6947 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6948 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6953 if (cfg->method->save_lmf)
6954 args_clobbered = TRUE;
6957 args_clobbered = TRUE;
6958 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6961 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6962 args_clobbered = TRUE;
6965 * Optimize the common case of the first bblock making a call with the same
6966 * arguments as the method. This works because the arguments are still in their
6967 * original argument registers.
6968 * FIXME: Generalize this
6970 if (!args_clobbered) {
6971 MonoBasicBlock *first_bb = cfg->bb_entry;
6973 int filter = FILTER_IL_SEQ_POINT;
6975 next = mono_bb_first_inst (first_bb, filter);
6976 if (!next && first_bb->next_bb) {
6977 first_bb = first_bb->next_bb;
6978 next = mono_bb_first_inst (first_bb, filter);
6981 if (first_bb->in_count > 1)
6984 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6985 ArgInfo *ainfo = cinfo->args + i;
6986 gboolean match = FALSE;
6988 ins = cfg->args [i];
6989 if (ins->opcode != OP_REGVAR) {
6990 switch (ainfo->storage) {
6992 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6993 if (next->dreg == ainfo->reg) {
6997 next->opcode = OP_MOVE;
6998 next->sreg1 = ainfo->reg;
6999 /* Only continue if the instruction doesn't change argument regs */
7000 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7010 /* Argument allocated to (non-volatile) register */
7011 switch (ainfo->storage) {
7013 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7024 next = mono_inst_next (next, filter);
7025 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7032 if (cfg->gen_sdb_seq_points) {
7033 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7035 /* Initialize seq_point_info_var */
7036 if (cfg->compile_aot) {
7037 /* Initialize the variable from a GOT slot */
7038 /* Same as OP_AOTCONST */
7039 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7040 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7041 g_assert (info_var->opcode == OP_REGOFFSET);
7042 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7045 if (cfg->compile_aot) {
7046 /* Initialize ss_tramp_var */
7047 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7048 g_assert (ins->opcode == OP_REGOFFSET);
7050 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7051 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7052 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7054 /* Initialize ss_tramp_var */
7055 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7056 g_assert (ins->opcode == OP_REGOFFSET);
7058 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7059 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7061 /* Initialize bp_tramp_var */
7062 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7063 g_assert (ins->opcode == OP_REGOFFSET);
7065 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7066 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7070 cfg->code_len = code - cfg->native_code;
7072 g_assert (cfg->code_len < cfg->code_size);
7078 mono_arch_emit_epilog (MonoCompile *cfg)
7080 MonoMethod *method = cfg->method;
7083 int max_epilog_size;
7085 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7086 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7088 max_epilog_size = get_max_epilog_size (cfg);
7090 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7091 cfg->code_size *= 2;
7092 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7093 cfg->stat_code_reallocs++;
7095 code = cfg->native_code + cfg->code_len;
7097 cfg->has_unwind_info_for_epilog = TRUE;
7099 /* Mark the start of the epilog */
7100 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7102 /* Save the uwind state which is needed by the out-of-line code */
7103 mono_emit_unwind_op_remember_state (cfg, code);
7105 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7106 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7108 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7110 if (method->save_lmf) {
7111 /* check if we need to restore protection of the stack after a stack overflow */
7112 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7114 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7115 /* we load the value in a separate instruction: this mechanism may be
7116 * used later as a safer way to do thread interruption
7118 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7119 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7121 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7122 /* note that the call trampoline will preserve eax/edx */
7123 x86_call_reg (code, X86_ECX);
7124 x86_patch (patch, code);
7126 /* FIXME: maybe save the jit tls in the prolog */
7128 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7129 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7133 /* Restore callee saved regs */
7134 for (i = 0; i < AMD64_NREG; ++i) {
7135 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7136 /* Restore only used_int_regs, not arch.saved_iregs */
7137 #if defined(MONO_SUPPORT_TASKLETS)
7140 int restore_reg=(cfg->used_int_regs & (1 << i));
7143 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7144 mono_emit_unwind_op_same_value (cfg, code, i);
7145 async_exc_point (code);
7147 save_area_offset += 8;
7151 /* Load returned vtypes into registers if needed */
7152 cinfo = (CallInfo *)cfg->arch.cinfo;
7153 if (cinfo->ret.storage == ArgValuetypeInReg) {
7154 ArgInfo *ainfo = &cinfo->ret;
7155 MonoInst *inst = cfg->ret;
7157 for (quad = 0; quad < 2; quad ++) {
7158 switch (ainfo->pair_storage [quad]) {
7160 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7162 case ArgInFloatSSEReg:
7163 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7165 case ArgInDoubleSSEReg:
7166 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7171 g_assert_not_reached ();
7176 if (cfg->arch.omit_fp) {
7177 if (cfg->arch.stack_alloc_size) {
7178 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7182 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7183 amd64_pop_reg (code, AMD64_RBP);
7184 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7187 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7190 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7191 async_exc_point (code);
7194 /* Restore the unwind state to be the same as before the epilog */
7195 mono_emit_unwind_op_restore_state (cfg, code);
7197 cfg->code_len = code - cfg->native_code;
7199 g_assert (cfg->code_len < cfg->code_size);
7203 mono_arch_emit_exceptions (MonoCompile *cfg)
7205 MonoJumpInfo *patch_info;
7208 MonoClass *exc_classes [16];
7209 guint8 *exc_throw_start [16], *exc_throw_end [16];
7210 guint32 code_size = 0;
7212 /* Compute needed space */
7213 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7214 if (patch_info->type == MONO_PATCH_INFO_EXC)
7216 if (patch_info->type == MONO_PATCH_INFO_R8)
7217 code_size += 8 + 15; /* sizeof (double) + alignment */
7218 if (patch_info->type == MONO_PATCH_INFO_R4)
7219 code_size += 4 + 15; /* sizeof (float) + alignment */
7220 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7221 code_size += 8 + 7; /*sizeof (void*) + alignment */
7224 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7225 cfg->code_size *= 2;
7226 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7227 cfg->stat_code_reallocs++;
7230 code = cfg->native_code + cfg->code_len;
7232 /* add code to raise exceptions */
7234 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7235 switch (patch_info->type) {
7236 case MONO_PATCH_INFO_EXC: {
7237 MonoClass *exc_class;
7241 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7243 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7244 throw_ip = patch_info->ip.i;
7246 //x86_breakpoint (code);
7247 /* Find a throw sequence for the same exception class */
7248 for (i = 0; i < nthrows; ++i)
7249 if (exc_classes [i] == exc_class)
7252 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7253 x86_jump_code (code, exc_throw_start [i]);
7254 patch_info->type = MONO_PATCH_INFO_NONE;
7258 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7262 exc_classes [nthrows] = exc_class;
7263 exc_throw_start [nthrows] = code;
7265 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7267 patch_info->type = MONO_PATCH_INFO_NONE;
7269 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7271 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7276 exc_throw_end [nthrows] = code;
7286 g_assert(code < cfg->native_code + cfg->code_size);
7289 /* Handle relocations with RIP relative addressing */
7290 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7291 gboolean remove = FALSE;
7292 guint8 *orig_code = code;
7294 switch (patch_info->type) {
7295 case MONO_PATCH_INFO_R8:
7296 case MONO_PATCH_INFO_R4: {
7297 guint8 *pos, *patch_pos;
7300 /* The SSE opcodes require a 16 byte alignment */
7301 code = (guint8*)ALIGN_TO (code, 16);
7303 pos = cfg->native_code + patch_info->ip.i;
7304 if (IS_REX (pos [1])) {
7305 patch_pos = pos + 5;
7306 target_pos = code - pos - 9;
7309 patch_pos = pos + 4;
7310 target_pos = code - pos - 8;
7313 if (patch_info->type == MONO_PATCH_INFO_R8) {
7314 *(double*)code = *(double*)patch_info->data.target;
7315 code += sizeof (double);
7317 *(float*)code = *(float*)patch_info->data.target;
7318 code += sizeof (float);
7321 *(guint32*)(patch_pos) = target_pos;
7326 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7329 if (cfg->compile_aot)
7332 /*loading is faster against aligned addresses.*/
7333 code = (guint8*)ALIGN_TO (code, 8);
7334 memset (orig_code, 0, code - orig_code);
7336 pos = cfg->native_code + patch_info->ip.i;
7338 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7339 if (IS_REX (pos [1]))
7340 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7342 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7344 *(gpointer*)code = (gpointer)patch_info->data.target;
7345 code += sizeof (gpointer);
7355 if (patch_info == cfg->patch_info)
7356 cfg->patch_info = patch_info->next;
7360 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7362 tmp->next = patch_info->next;
7365 g_assert (code < cfg->native_code + cfg->code_size);
7368 cfg->code_len = code - cfg->native_code;
7370 g_assert (cfg->code_len < cfg->code_size);
7374 #endif /* DISABLE_JIT */
7377 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7379 guchar *code = (guchar *)p;
7380 MonoMethodSignature *sig;
7382 int i, n, stack_area = 0;
7384 /* Keep this in sync with mono_arch_get_argument_info */
7386 if (enable_arguments) {
7387 /* Allocate a new area on the stack and save arguments there */
7388 sig = mono_method_signature (cfg->method);
7390 n = sig->param_count + sig->hasthis;
7392 stack_area = ALIGN_TO (n * 8, 16);
7394 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7396 for (i = 0; i < n; ++i) {
7397 inst = cfg->args [i];
7399 if (inst->opcode == OP_REGVAR)
7400 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7402 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7403 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7408 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7409 amd64_set_reg_template (code, AMD64_ARG_REG1);
7410 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7411 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7413 if (enable_arguments)
7414 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7428 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7430 guchar *code = (guchar *)p;
7431 int save_mode = SAVE_NONE;
7432 MonoMethod *method = cfg->method;
7433 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7436 switch (ret_type->type) {
7437 case MONO_TYPE_VOID:
7438 /* special case string .ctor icall */
7439 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7440 save_mode = SAVE_EAX;
7442 save_mode = SAVE_NONE;
7446 save_mode = SAVE_EAX;
7450 save_mode = SAVE_XMM;
7452 case MONO_TYPE_GENERICINST:
7453 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7454 save_mode = SAVE_EAX;
7458 case MONO_TYPE_VALUETYPE:
7459 save_mode = SAVE_STRUCT;
7462 save_mode = SAVE_EAX;
7466 /* Save the result and copy it into the proper argument register */
7467 switch (save_mode) {
7469 amd64_push_reg (code, AMD64_RAX);
7471 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7472 if (enable_arguments)
7473 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7477 if (enable_arguments)
7478 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7481 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7482 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7484 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7486 * The result is already in the proper argument register so no copying
7493 g_assert_not_reached ();
7496 /* Set %al since this is a varargs call */
7497 if (save_mode == SAVE_XMM)
7498 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7500 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7502 if (preserve_argument_registers) {
7503 for (i = 0; i < PARAM_REGS; ++i)
7504 amd64_push_reg (code, param_regs [i]);
7507 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7508 amd64_set_reg_template (code, AMD64_ARG_REG1);
7509 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7511 if (preserve_argument_registers) {
7512 for (i = PARAM_REGS - 1; i >= 0; --i)
7513 amd64_pop_reg (code, param_regs [i]);
7516 /* Restore result */
7517 switch (save_mode) {
7519 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7520 amd64_pop_reg (code, AMD64_RAX);
7526 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7527 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7528 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7533 g_assert_not_reached ();
7540 mono_arch_flush_icache (guint8 *code, gint size)
7546 mono_arch_flush_register_windows (void)
7551 mono_arch_is_inst_imm (gint64 imm)
7553 return amd64_use_imm32 (imm);
7557 * Determine whenever the trap whose info is in SIGINFO is caused by
7561 mono_arch_is_int_overflow (void *sigctx, void *info)
7568 mono_sigctx_to_monoctx (sigctx, &ctx);
7570 rip = (guint8*)ctx.gregs [AMD64_RIP];
7572 if (IS_REX (rip [0])) {
7573 reg = amd64_rex_b (rip [0]);
7579 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7581 reg += x86_modrm_rm (rip [1]);
7583 value = ctx.gregs [reg];
7593 mono_arch_get_patch_offset (guint8 *code)
7599 * mono_breakpoint_clean_code:
7601 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7602 * breakpoints in the original code, they are removed in the copy.
7604 * Returns TRUE if no sw breakpoint was present.
7607 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7610 * If method_start is non-NULL we need to perform bound checks, since we access memory
7611 * at code - offset we could go before the start of the method and end up in a different
7612 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7615 if (!method_start || code - offset >= method_start) {
7616 memcpy (buf, code - offset, size);
7618 int diff = code - method_start;
7619 memset (buf, 0, size);
7620 memcpy (buf + offset - diff, method_start, diff + size - offset);
7626 mono_arch_get_this_arg_reg (guint8 *code)
7628 return AMD64_ARG_REG1;
7632 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7634 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7637 #define MAX_ARCH_DELEGATE_PARAMS 10
7640 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7642 guint8 *code, *start;
7643 GSList *unwind_ops = NULL;
7646 unwind_ops = mono_arch_get_cie_program ();
7649 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7651 /* Replace the this argument with the target */
7652 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7653 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7654 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7656 g_assert ((code - start) < 64);
7657 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7659 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7661 if (param_count == 0) {
7662 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7664 /* We have to shift the arguments left */
7665 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7666 for (i = 0; i < param_count; ++i) {
7669 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7671 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7673 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7677 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7679 g_assert ((code - start) < 64);
7680 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7683 mono_arch_flush_icache (start, code - start);
7686 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7688 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7689 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7693 if (mono_jit_map_is_enabled ()) {
7696 buff = (char*)"delegate_invoke_has_target";
7698 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7699 mono_emit_jit_tramp (start, code - start, buff);
7703 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7708 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7711 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7713 guint8 *code, *start;
7718 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7721 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7723 unwind_ops = mono_arch_get_cie_program ();
7725 /* Replace the this argument with the target */
7726 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7727 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7730 /* Load the IMT reg */
7731 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7734 /* Load the vtable */
7735 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7736 amd64_jump_membase (code, AMD64_RAX, offset);
7737 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7739 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7740 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7741 g_free (tramp_name);
7747 * mono_arch_get_delegate_invoke_impls:
7749 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7753 mono_arch_get_delegate_invoke_impls (void)
7756 MonoTrampInfo *info;
7759 get_delegate_invoke_impl (&info, TRUE, 0);
7760 res = g_slist_prepend (res, info);
7762 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7763 get_delegate_invoke_impl (&info, FALSE, i);
7764 res = g_slist_prepend (res, info);
7767 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7768 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7769 res = g_slist_prepend (res, info);
7772 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7773 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7774 res = g_slist_prepend (res, info);
7775 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7776 res = g_slist_prepend (res, info);
7783 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7785 guint8 *code, *start;
7788 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7791 /* FIXME: Support more cases */
7792 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7796 static guint8* cached = NULL;
7801 if (mono_aot_only) {
7802 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7804 MonoTrampInfo *info;
7805 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7806 mono_tramp_info_register (info, NULL);
7809 mono_memory_barrier ();
7813 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7814 for (i = 0; i < sig->param_count; ++i)
7815 if (!mono_is_regsize_var (sig->params [i]))
7817 if (sig->param_count > 4)
7820 code = cache [sig->param_count];
7824 if (mono_aot_only) {
7825 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7826 start = (guint8 *)mono_aot_get_trampoline (name);
7829 MonoTrampInfo *info;
7830 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7831 mono_tramp_info_register (info, NULL);
7834 mono_memory_barrier ();
7836 cache [sig->param_count] = start;
7843 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7845 MonoTrampInfo *info;
7848 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7850 mono_tramp_info_register (info, NULL);
7855 mono_arch_finish_init (void)
7857 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7858 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7863 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7867 #define CMP_SIZE (6 + 1)
7868 #define CMP_REG_REG_SIZE (4 + 1)
7869 #define BR_SMALL_SIZE 2
7870 #define BR_LARGE_SIZE 6
7871 #define MOV_REG_IMM_SIZE 10
7872 #define MOV_REG_IMM_32BIT_SIZE 6
7873 #define JUMP_REG_SIZE (2 + 1)
7876 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7878 int i, distance = 0;
7879 for (i = start; i < target; ++i)
7880 distance += imt_entries [i]->chunk_size;
7885 * LOCKING: called with the domain lock held
7888 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7889 gpointer fail_tramp)
7893 guint8 *code, *start;
7894 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7897 for (i = 0; i < count; ++i) {
7898 MonoIMTCheckItem *item = imt_entries [i];
7899 if (item->is_equals) {
7900 if (item->check_target_idx) {
7901 if (!item->compare_done) {
7902 if (amd64_use_imm32 ((gint64)item->key))
7903 item->chunk_size += CMP_SIZE;
7905 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7907 if (item->has_target_code) {
7908 item->chunk_size += MOV_REG_IMM_SIZE;
7910 if (vtable_is_32bit)
7911 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7913 item->chunk_size += MOV_REG_IMM_SIZE;
7915 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7918 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7919 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7921 if (vtable_is_32bit)
7922 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7924 item->chunk_size += MOV_REG_IMM_SIZE;
7925 item->chunk_size += JUMP_REG_SIZE;
7926 /* with assert below:
7927 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7932 if (amd64_use_imm32 ((gint64)item->key))
7933 item->chunk_size += CMP_SIZE;
7935 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7936 item->chunk_size += BR_LARGE_SIZE;
7937 imt_entries [item->check_target_idx]->compare_done = TRUE;
7939 size += item->chunk_size;
7942 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7944 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7947 unwind_ops = mono_arch_get_cie_program ();
7949 for (i = 0; i < count; ++i) {
7950 MonoIMTCheckItem *item = imt_entries [i];
7951 item->code_target = code;
7952 if (item->is_equals) {
7953 gboolean fail_case = !item->check_target_idx && fail_tramp;
7955 if (item->check_target_idx || fail_case) {
7956 if (!item->compare_done || fail_case) {
7957 if (amd64_use_imm32 ((gint64)item->key))
7958 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7960 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7961 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7964 item->jmp_code = code;
7965 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7966 if (item->has_target_code) {
7967 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7968 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7970 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7971 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7975 amd64_patch (item->jmp_code, code);
7976 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7977 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7978 item->jmp_code = NULL;
7981 /* enable the commented code to assert on wrong method */
7983 if (amd64_is_imm32 (item->key))
7984 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7986 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7987 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7989 item->jmp_code = code;
7990 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7991 /* See the comment below about R10 */
7992 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7993 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7994 amd64_patch (item->jmp_code, code);
7995 amd64_breakpoint (code);
7996 item->jmp_code = NULL;
7998 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7999 needs to be preserved. R10 needs
8000 to be preserved for calls which
8001 require a runtime generic context,
8002 but interface calls don't. */
8003 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8004 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8008 if (amd64_use_imm32 ((gint64)item->key))
8009 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8011 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8012 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8014 item->jmp_code = code;
8015 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8016 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8018 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8020 g_assert (code - item->code_target <= item->chunk_size);
8022 /* patch the branches to get to the target items */
8023 for (i = 0; i < count; ++i) {
8024 MonoIMTCheckItem *item = imt_entries [i];
8025 if (item->jmp_code) {
8026 if (item->check_target_idx) {
8027 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8033 mono_stats.imt_trampolines_size += code - start;
8034 g_assert (code - start <= size);
8035 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8037 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8039 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8045 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8047 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8051 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8053 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8057 mono_arch_get_cie_program (void)
8061 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8062 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8070 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8072 MonoInst *ins = NULL;
8075 if (cmethod->klass == mono_defaults.math_class) {
8076 if (strcmp (cmethod->name, "Sin") == 0) {
8078 } else if (strcmp (cmethod->name, "Cos") == 0) {
8080 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8082 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8086 if (opcode && fsig->param_count == 1) {
8087 MONO_INST_NEW (cfg, ins, opcode);
8088 ins->type = STACK_R8;
8089 ins->dreg = mono_alloc_freg (cfg);
8090 ins->sreg1 = args [0]->dreg;
8091 MONO_ADD_INS (cfg->cbb, ins);
8095 if (cfg->opt & MONO_OPT_CMOV) {
8096 if (strcmp (cmethod->name, "Min") == 0) {
8097 if (fsig->params [0]->type == MONO_TYPE_I4)
8099 if (fsig->params [0]->type == MONO_TYPE_U4)
8100 opcode = OP_IMIN_UN;
8101 else if (fsig->params [0]->type == MONO_TYPE_I8)
8103 else if (fsig->params [0]->type == MONO_TYPE_U8)
8104 opcode = OP_LMIN_UN;
8105 } else if (strcmp (cmethod->name, "Max") == 0) {
8106 if (fsig->params [0]->type == MONO_TYPE_I4)
8108 if (fsig->params [0]->type == MONO_TYPE_U4)
8109 opcode = OP_IMAX_UN;
8110 else if (fsig->params [0]->type == MONO_TYPE_I8)
8112 else if (fsig->params [0]->type == MONO_TYPE_U8)
8113 opcode = OP_LMAX_UN;
8117 if (opcode && fsig->param_count == 2) {
8118 MONO_INST_NEW (cfg, ins, opcode);
8119 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8120 ins->dreg = mono_alloc_ireg (cfg);
8121 ins->sreg1 = args [0]->dreg;
8122 ins->sreg2 = args [1]->dreg;
8123 MONO_ADD_INS (cfg->cbb, ins);
8127 /* OP_FREM is not IEEE compatible */
8128 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8129 MONO_INST_NEW (cfg, ins, OP_FREM);
8130 ins->inst_i0 = args [0];
8131 ins->inst_i1 = args [1];
8141 mono_arch_print_tree (MonoInst *tree, int arity)
8147 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8149 return ctx->gregs [reg];
8153 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8155 ctx->gregs [reg] = val;
8159 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8161 gpointer *sp, old_value;
8165 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8166 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8169 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8178 * mono_arch_emit_load_aotconst:
8180 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8181 * TARGET from the mscorlib GOT in full-aot code.
8182 * On AMD64, the result is placed into R11.
8185 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8187 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8188 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8194 * mono_arch_get_trampolines:
8196 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8200 mono_arch_get_trampolines (gboolean aot)
8202 return mono_amd64_get_exception_trampolines (aot);
8205 /* Soft Debug support */
8206 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8209 * mono_arch_set_breakpoint:
8211 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8212 * The location should contain code emitted by OP_SEQ_POINT.
8215 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8220 guint32 native_offset = ip - (guint8*)ji->code_start;
8221 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8223 g_assert (info->bp_addrs [native_offset] == 0);
8224 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8226 /* ip points to a mov r11, 0 */
8227 g_assert (code [0] == 0x41);
8228 g_assert (code [1] == 0xbb);
8229 amd64_mov_reg_imm (code, AMD64_R11, 1);
8234 * mono_arch_clear_breakpoint:
8236 * Clear the breakpoint at IP.
8239 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8244 guint32 native_offset = ip - (guint8*)ji->code_start;
8245 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8247 info->bp_addrs [native_offset] = NULL;
8249 amd64_mov_reg_imm (code, AMD64_R11, 0);
8254 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8256 /* We use soft breakpoints on amd64 */
8261 * mono_arch_skip_breakpoint:
8263 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8264 * we resume, the instruction is not executed again.
8267 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8269 g_assert_not_reached ();
8273 * mono_arch_start_single_stepping:
8275 * Start single stepping.
8278 mono_arch_start_single_stepping (void)
8280 ss_trampoline = mini_get_single_step_trampoline ();
8284 * mono_arch_stop_single_stepping:
8286 * Stop single stepping.
8289 mono_arch_stop_single_stepping (void)
8291 ss_trampoline = NULL;
8295 * mono_arch_is_single_step_event:
8297 * Return whenever the machine state in SIGCTX corresponds to a single
8301 mono_arch_is_single_step_event (void *info, void *sigctx)
8303 /* We use soft breakpoints on amd64 */
8308 * mono_arch_skip_single_step:
8310 * Modify CTX so the ip is placed after the single step trigger instruction,
8311 * we resume, the instruction is not executed again.
8314 mono_arch_skip_single_step (MonoContext *ctx)
8316 g_assert_not_reached ();
8320 * mono_arch_create_seq_point_info:
8322 * Return a pointer to a data structure which is used by the sequence
8323 * point implementation in AOTed code.
8326 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8331 // FIXME: Add a free function
8333 mono_domain_lock (domain);
8334 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8336 mono_domain_unlock (domain);
8339 ji = mono_jit_info_table_find (domain, (char*)code);
8342 // FIXME: Optimize the size
8343 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8345 info->ss_tramp_addr = &ss_trampoline;
8347 mono_domain_lock (domain);
8348 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8350 mono_domain_unlock (domain);
8357 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8359 ext->lmf.previous_lmf = prev_lmf;
8360 /* Mark that this is a MonoLMFExt */
8361 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8362 ext->lmf.rsp = (gssize)ext;
8368 mono_arch_opcode_supported (int opcode)
8371 case OP_ATOMIC_ADD_I4:
8372 case OP_ATOMIC_ADD_I8:
8373 case OP_ATOMIC_EXCHANGE_I4:
8374 case OP_ATOMIC_EXCHANGE_I8:
8375 case OP_ATOMIC_CAS_I4:
8376 case OP_ATOMIC_CAS_I8:
8377 case OP_ATOMIC_LOAD_I1:
8378 case OP_ATOMIC_LOAD_I2:
8379 case OP_ATOMIC_LOAD_I4:
8380 case OP_ATOMIC_LOAD_I8:
8381 case OP_ATOMIC_LOAD_U1:
8382 case OP_ATOMIC_LOAD_U2:
8383 case OP_ATOMIC_LOAD_U4:
8384 case OP_ATOMIC_LOAD_U8:
8385 case OP_ATOMIC_LOAD_R4:
8386 case OP_ATOMIC_LOAD_R8:
8387 case OP_ATOMIC_STORE_I1:
8388 case OP_ATOMIC_STORE_I2:
8389 case OP_ATOMIC_STORE_I4:
8390 case OP_ATOMIC_STORE_I8:
8391 case OP_ATOMIC_STORE_U1:
8392 case OP_ATOMIC_STORE_U2:
8393 case OP_ATOMIC_STORE_U4:
8394 case OP_ATOMIC_STORE_U8:
8395 case OP_ATOMIC_STORE_R4:
8396 case OP_ATOMIC_STORE_R8:
8404 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8406 return get_call_info (mp, sig);