mono/mini/local-propagation.c

   1 /*
   2  * local-propagation.c: Local constant, copy and tree propagation.
   3  *
   4  * To make some sense of the tree mover, read mono/docs/tree-mover.txt
   5  *
   6  * Author:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Massimiliano Mantione (massi@ximian.com)
  10  *
  11  * (C) 2006 Novell, Inc.  http://www.novell.com
  12  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  13  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  14  */
  15
  16 #include <config.h>
  17 #ifndef DISABLE_JIT
  18
  19 #include <string.h>
  20 #include <stdio.h>
  21 #ifdef HAVE_ALLOCA_H
  22 #include <alloca.h>
  23 #endif
  24
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/mempool.h>
  27 #include <mono/metadata/opcodes.h>
  28 #include "mini.h"
  29 #include "ir-emit.h"
  30
  31 #ifndef MONO_ARCH_IS_OP_MEMBASE
  32 #define MONO_ARCH_IS_OP_MEMBASE(opcode) FALSE
  33 #endif
  34
  35 static inline MonoBitSet*
  36 mono_bitset_mp_new_noinit (MonoMemPool *mp,  guint32 max_size)
  37 {
  38         int size = mono_bitset_alloc_size (max_size, 0);
  39         gpointer mem;
  40
  41         mem = mono_mempool_alloc (mp, size);
  42         return mono_bitset_mem_new (mem, max_size, MONO_BITSET_DONT_FREE);
  43 }
  44
  45 struct magic_unsigned {
  46         guint32 magic_number;
  47         gboolean addition;
  48         int shift;
  49 };
  50
  51 struct magic_signed {
  52         gint32 magic_number;
  53         int shift;
  54 };
  55
  56 /* http://www.hackersdelight.org/hdcodetxt/magicu.c.txt */
  57 static struct magic_unsigned
  58 compute_magic_unsigned (guint32 divisor) {
  59         guint32 nc, delta, q1, r1, q2, r2;
  60         struct magic_unsigned magu;
  61         gboolean gt = FALSE;
  62         int p;
  63
  64         magu.addition = 0;
  65         nc = -1 - (-divisor) % divisor;
  66         p = 31;
  67         q1 = 0x80000000 / nc;
  68         r1 = 0x80000000 - q1 * nc;
  69         q2 = 0x7FFFFFFF / divisor;
  70         r2 = 0x7FFFFFFF - q2 * divisor;
  71         do {
  72                 p = p + 1;
  73                 if (q1 >= 0x80000000)
  74                         gt = TRUE;
  75                 if (r1 >= nc - r1) {
  76                         q1 = 2 * q1 + 1;
  77                         r1 = 2 * r1 - nc;
  78                 } else {
  79                         q1 = 2 * q1;
  80                         r1 = 2 * r1;
  81                 }
  82                 if (r2 + 1 >= divisor - r2) {
  83                         if (q2 >= 0x7FFFFFFF)
  84                                 magu.addition = 1;
  85                         q2 = 2 * q2 + 1;
  86                         r2 = 2 * r2 + 1 - divisor;
  87                 } else {
  88                         if (q2 >= 0x80000000)
  89                                 magu.addition = 1;
  90                         q2 = 2 * q2;
  91                         r2 = 2 * r2 + 1;
  92                 }
  93                 delta = divisor - 1 - r2;
  94         } while (!gt && (q1 < delta || (q1 == delta && r1 == 0)));
  95
  96         magu.magic_number = q2 + 1;
  97         magu.shift = p - 32;
  98         return magu;
  99 }
 100
 101 /* http://www.hackersdelight.org/hdcodetxt/magic.c.txt */
 102 static struct magic_signed
 103 compute_magic_signed (gint32 divisor) {
 104         int p;
 105         guint32 ad, anc, delta, q1, r1, q2, r2, t;
 106         const guint32 two31 = 0x80000000;
 107         struct magic_signed mag;
 108
 109         ad = abs (divisor);
 110         t = two31 + ((unsigned)divisor >> 31);
 111         anc = t - 1 - t % ad;
 112         p = 31;
 113         q1 = two31 / anc;
 114         r1 = two31 - q1 * anc;
 115         q2 = two31 / ad;
 116         r2 = two31 - q2 * ad;
 117         do {
 118                 p++;
 119                 q1 *= 2;
 120                 r1 *= 2;
 121                 if (r1 >= anc) {
 122                         q1++;
 123                         r1 -= anc;
 124                 }
 125
 126                 q2 *= 2;
 127                 r2 *= 2;
 128
 129                 if (r2 >= ad) {
 130                         q2++;
 131                         r2 -= ad;
 132                 }
 133
 134                 delta = ad - r2;
 135         } while (q1 < delta || (q1 == delta && r1 == 0));
 136
 137         mag.magic_number = q2 + 1;
 138         if (divisor < 0)
 139                 mag.magic_number = -mag.magic_number;
 140         mag.shift = p - 32;
 141         return mag;
 142 }
 143
 144 static gboolean
 145 mono_strength_reduction_division (MonoCompile *cfg, MonoInst *ins)
 146 {
 147         gboolean allocated_vregs = FALSE;
 148         /*
 149          * We don't use it on 32bit systems because on those
 150          * platforms we emulate long multiplication, driving the
 151          * performance back down.
 152          */
 153         switch (ins->opcode) {
 154                 case OP_IDIV_UN_IMM: {
 155                         guint32 tmp_regl;
 156 #if SIZEOF_REGISTER == 8
 157                         guint32 dividend_reg;
 158 #else
 159                         guint32 tmp_regi;
 160 #endif
 161                         struct magic_unsigned mag;
 162                         int power2 = mono_is_power_of_two (ins->inst_imm);
 163
 164                         /* The decomposition doesn't handle exception throwing */
 165                         if (ins->inst_imm == 0)
 166                                 break;
 167
 168                         if (power2 >= 0) {
 169                                 ins->opcode = OP_ISHR_UN_IMM;
 170                                 ins->sreg2 = -1;
 171                                 ins->inst_imm = power2;
 172                                 break;
 173                         }
 174                         allocated_vregs = TRUE;
 175                         /*
 176                          * Replacement of unsigned division with multiplication,
 177                          * shifts and additions Hacker's Delight, chapter 10-10.
 178                          */
 179                         mag = compute_magic_unsigned (ins->inst_imm);
 180                         tmp_regl = alloc_lreg (cfg);
 181 #if SIZEOF_REGISTER == 8
 182                         dividend_reg = alloc_lreg (cfg);
 183                         MONO_EMIT_NEW_I8CONST (cfg, tmp_regl, mag.magic_number);
 184                         MONO_EMIT_NEW_UNALU (cfg, OP_ZEXT_I4, dividend_reg, ins->sreg1);
 185                         MONO_EMIT_NEW_BIALU (cfg, OP_LMUL, tmp_regl, dividend_reg, tmp_regl);
 186                         if (mag.addition) {
 187                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32);
 188                                 MONO_EMIT_NEW_BIALU (cfg, OP_LADD, tmp_regl, tmp_regl, dividend_reg);
 189                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, mag.shift);
 190                         } else {
 191                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, 32 + mag.shift);
 192                         }
 193 #else
 194                         tmp_regi = alloc_ireg (cfg);
 195                         MONO_EMIT_NEW_ICONST (cfg, tmp_regi, mag.magic_number);
 196                         MONO_EMIT_NEW_BIALU (cfg, OP_BIGMUL_UN, tmp_regl, ins->sreg1, tmp_regi);
 197                         /* Long shifts below will be decomposed during cprop */
 198                         if (mag.addition) {
 199                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32);
 200                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADDCC, MONO_LVREG_LS (tmp_regl), MONO_LVREG_LS (tmp_regl), ins->sreg1);
 201                                 /* MONO_LVREG_MS (tmp_reg) is 0, save in it the carry */
 202                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADC, MONO_LVREG_MS (tmp_regl), MONO_LVREG_MS (tmp_regl), MONO_LVREG_MS (tmp_regl));
 203                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, mag.shift);
 204                         } else {
 205                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32 + mag.shift);
 206                         }
 207                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ins->dreg, MONO_LVREG_LS (tmp_regl));
 208 #endif
 209                         mono_jit_stats.optimized_divisions++;
 210                         break;
 211                 }
 212                 case OP_IDIV_IMM: {
 213                         guint32 tmp_regl;
 214 #if SIZEOF_REGISTER == 8
 215                         guint32 dividend_reg;
 216 #else
 217                         guint32 tmp_regi;
 218 #endif
 219                         struct magic_signed mag;
 220                         int power2 = mono_is_power_of_two (ins->inst_imm);
 221                         /* The decomposition doesn't handle exception throwing */
 222                         if (ins->inst_imm == 0 || ins->inst_imm == -1)
 223                                 break;
 224                         allocated_vregs = TRUE;
 225                         if (power2 == 1) {
 226                                 guint32 r1 = alloc_ireg (cfg);
 227                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, r1, ins->sreg1, 31);
 228                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, r1, r1, ins->sreg1);
 229                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, ins->dreg, r1, 1);
 230                                 break;
 231                         } else if (power2 > 0 && power2 < 31) {
 232                                 guint32 r1 = alloc_ireg (cfg);
 233                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, r1, ins->sreg1, 31);
 234                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, r1, r1, (32 - power2));
 235                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, r1, r1, ins->sreg1);
 236                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, ins->dreg, r1, power2);
 237                                 break;
 238                         }
 239
 240                         /*
 241                          * Replacement of signed division with multiplication,
 242                          * shifts and additions Hacker's Delight, chapter 10-6.
 243                          */
 244                         mag = compute_magic_signed (ins->inst_imm);
 245                         tmp_regl = alloc_lreg (cfg);
 246 #if SIZEOF_REGISTER == 8
 247                         dividend_reg = alloc_lreg (cfg);
 248                         MONO_EMIT_NEW_I8CONST (cfg, tmp_regl, mag.magic_number);
 249                         MONO_EMIT_NEW_UNALU (cfg, OP_SEXT_I4, dividend_reg, ins->sreg1);
 250                         MONO_EMIT_NEW_BIALU (cfg, OP_LMUL, tmp_regl, dividend_reg, tmp_regl);
 251                         if ((ins->inst_imm > 0 && mag.magic_number < 0) || (ins->inst_imm < 0 && mag.magic_number > 0)) {
 252                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, 32);
 253                                 if (ins->inst_imm > 0 && mag.magic_number < 0) {
 254                                         MONO_EMIT_NEW_BIALU (cfg, OP_LADD, tmp_regl, tmp_regl, dividend_reg);
 255                                 } else if (ins->inst_imm < 0 && mag.magic_number > 0) {
 256                                         MONO_EMIT_NEW_BIALU (cfg, OP_LSUB, tmp_regl, tmp_regl, dividend_reg);
 257                                 }
 258                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, mag.shift);
 259                         } else {
 260                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, 32 + mag.shift);
 261                         }
 262                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, SIZEOF_REGISTER * 8 - 1);
 263                         MONO_EMIT_NEW_BIALU (cfg, OP_LADD, ins->dreg, ins->dreg, tmp_regl);
 264 #else
 265                         tmp_regi = alloc_ireg (cfg);
 266                         MONO_EMIT_NEW_ICONST (cfg, tmp_regi, mag.magic_number);
 267                         MONO_EMIT_NEW_BIALU (cfg, OP_BIGMUL, tmp_regl, ins->sreg1, tmp_regi);
 268                         if ((ins->inst_imm > 0 && mag.magic_number < 0) || (ins->inst_imm < 0 && mag.magic_number > 0)) {
 269                                 if (ins->inst_imm > 0 && mag.magic_number < 0) {
 270                                         /* Opposite sign, cannot overflow */
 271                                         MONO_EMIT_NEW_BIALU (cfg, OP_IADD, tmp_regi, MONO_LVREG_MS (tmp_regl), ins->sreg1);
 272                                 } else if (ins->inst_imm < 0 && mag.magic_number > 0) {
 273                                         /* Same sign, cannot overflow */
 274                                         MONO_EMIT_NEW_BIALU (cfg, OP_ISUB, tmp_regi, MONO_LVREG_MS (tmp_regl), ins->sreg1);
 275                                 }
 276                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, tmp_regi, tmp_regi, mag.shift);
 277                         } else {
 278                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, tmp_regi, MONO_LVREG_MS (tmp_regl), mag.shift);
 279                         }
 280                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, ins->dreg, tmp_regi, SIZEOF_REGISTER * 8 - 1);
 281                         MONO_EMIT_NEW_BIALU (cfg, OP_IADD, ins->dreg, ins->dreg, tmp_regi);
 282 #endif
 283                         mono_jit_stats.optimized_divisions++;
 284                         break;
 285                 }
 286         }
 287         return allocated_vregs;
 288 }
 289
 290 /*
 291  * Replaces ins with optimized opcodes.
 292  *
 293  * We can emit to cbb the equivalent instructions which will be used as
 294  * replacement for ins, or simply change the fields of ins. Spec needs to
 295  * be updated if we silently change the opcode of ins.
 296  *
 297  * Returns TRUE if additional vregs were allocated.
 298  */
 299 static gboolean
 300 mono_strength_reduction_ins (MonoCompile *cfg, MonoInst *ins, const char **spec)
 301 {
 302         gboolean allocated_vregs = FALSE;
 303
 304         /* FIXME: Add long/float */
 305         switch (ins->opcode) {
 306         case OP_MOVE:
 307         case OP_XMOVE:
 308                 if (ins->dreg == ins->sreg1) {
 309                         NULLIFY_INS (ins);
 310                 }
 311                 break;
 312         case OP_ADD_IMM:
 313         case OP_IADD_IMM:
 314         case OP_SUB_IMM:
 315         case OP_ISUB_IMM:
 316 #if SIZEOF_REGISTER == 8
 317         case OP_LADD_IMM:
 318         case OP_LSUB_IMM:
 319 #endif
 320                 if (ins->inst_imm == 0) {
 321                         ins->opcode = OP_MOVE;
 322                 }
 323                 break;
 324         case OP_MUL_IMM:
 325         case OP_IMUL_IMM:
 326 #if SIZEOF_REGISTER == 8
 327         case OP_LMUL_IMM:
 328 #endif
 329                 if (ins->inst_imm == 0) {
 330                         ins->opcode = (ins->opcode == OP_LMUL_IMM) ? OP_I8CONST : OP_ICONST;
 331                         ins->inst_c0 = 0;
 332                         ins->sreg1 = -1;
 333                 } else if (ins->inst_imm == 1) {
 334                         ins->opcode = OP_MOVE;
 335                 } else if ((ins->opcode == OP_IMUL_IMM) && (ins->inst_imm == -1)) {
 336                         ins->opcode = OP_INEG;
 337                 } else if ((ins->opcode == OP_LMUL_IMM) && (ins->inst_imm == -1)) {
 338                         ins->opcode = OP_LNEG;
 339                 } else {
 340                         int power2 = mono_is_power_of_two (ins->inst_imm);
 341                         if (power2 >= 0) {
 342                                 ins->opcode = (ins->opcode == OP_MUL_IMM) ? OP_SHL_IMM : ((ins->opcode == OP_LMUL_IMM) ? OP_LSHL_IMM : OP_ISHL_IMM);
 343                                 ins->inst_imm = power2;
 344                         }
 345                 }
 346                 break;
 347         case OP_IREM_UN_IMM: {
 348                 int power2 = mono_is_power_of_two (ins->inst_imm);
 349
 350                 if (power2 >= 0) {
 351                         ins->opcode = OP_IAND_IMM;
 352                         ins->sreg2 = -1;
 353                         ins->inst_imm = (1 << power2) - 1;
 354                 }
 355                 break;
 356         }
 357         case OP_IDIV_UN_IMM:
 358         case OP_IDIV_IMM: {
 359                 allocated_vregs = mono_strength_reduction_division (cfg, ins);
 360                 break;
 361         }
 362 #if SIZEOF_REGISTER == 8
 363         case OP_LREM_IMM:
 364 #endif
 365         case OP_IREM_IMM: {
 366                 int power = mono_is_power_of_two (ins->inst_imm);
 367                 if (ins->inst_imm == 1) {
 368                         ins->opcode = OP_ICONST;
 369                         MONO_INST_NULLIFY_SREGS (ins);
 370                         ins->inst_c0 = 0;
 371 #if __s390__
 372                 }
 373 #else
 374                 } else if ((ins->inst_imm > 0) && (ins->inst_imm < (1LL << 32)) && (power != -1)) {
 375                         gboolean is_long = ins->opcode == OP_LREM_IMM;
 376                         int compensator_reg = alloc_ireg (cfg);
 377                         int intermediate_reg;
 378
 379                         /* Based on gcc code */
 380
 381                         /* Add compensation for negative numerators */
 382
 383                         if (power > 1) {
 384                                 intermediate_reg = compensator_reg;
 385                                 MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LSHR_IMM : OP_ISHR_IMM, intermediate_reg, ins->sreg1, is_long ? 63 : 31);
 386                         } else {
 387                                 intermediate_reg = ins->sreg1;
 388                         }
 389
 390                         MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LSHR_UN_IMM : OP_ISHR_UN_IMM, compensator_reg, intermediate_reg, (is_long ? 64 : 32) - power);
 391                         MONO_EMIT_NEW_BIALU (cfg, is_long ? OP_LADD : OP_IADD, ins->dreg, ins->sreg1, compensator_reg);
 392                         /* Compute remainder */
 393                         MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LAND_IMM : OP_AND_IMM, ins->dreg, ins->dreg, (1 << power) - 1);
 394                         /* Remove compensation */
 395                         MONO_EMIT_NEW_BIALU (cfg, is_long ? OP_LSUB : OP_ISUB, ins->dreg, ins->dreg, compensator_reg);
 396
 397                         allocated_vregs = TRUE;
 398                 }
 399 #endif
 400                 break;
 401         }
 402 #if SIZEOF_REGISTER == 4
 403         case OP_LSHR_IMM: {
 404                 if (COMPILE_LLVM (cfg))
 405                         break;
 406                 if (ins->inst_c1 == 32) {
 407                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 408                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 31);
 409                 } else if (ins->inst_c1 == 0) {
 410                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 411                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 412                 } else if (ins->inst_c1 > 32) {
 413                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1 - 32);
 414                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 31);
 415                 } else {
 416                         guint32 tmpreg = alloc_ireg (cfg);
 417                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, tmpreg, MONO_LVREG_MS (ins->sreg1), 32 - ins->inst_c1);
 418                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
 419                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
 420                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->dreg), tmpreg);
 421                         allocated_vregs = TRUE;
 422                 }
 423                 break;
 424         }
 425         case OP_LSHR_UN_IMM: {
 426                 if (COMPILE_LLVM (cfg))
 427                         break;
 428                 if (ins->inst_c1 == 32) {
 429                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 430                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_MS (ins->dreg), 0);
 431                 } else if (ins->inst_c1 == 0) {
 432                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 433                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 434                 } else if (ins->inst_c1 > 32) {
 435                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1 - 32);
 436                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_MS (ins->dreg), 0);
 437                 } else {
 438                         guint32 tmpreg = alloc_ireg (cfg);
 439                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, tmpreg, MONO_LVREG_MS (ins->sreg1), 32 - ins->inst_c1);
 440                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
 441                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
 442                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->dreg), tmpreg);
 443                         allocated_vregs = TRUE;
 444                 }
 445                 break;
 446         }
 447         case OP_LSHL_IMM: {
 448                 if (COMPILE_LLVM (cfg))
 449                         break;
 450                 if (ins->inst_c1 == 32) {
 451                         /* just move the lower half to the upper and zero the lower word */
 452                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 453                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_LS (ins->dreg), 0);
 454                 } else if (ins->inst_c1 == 0) {
 455                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 456                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 457                 } else if (ins->inst_c1 > 32) {
 458                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1 - 32);
 459                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_LS (ins->dreg), 0);
 460                 } else {
 461                         guint32 tmpreg = alloc_ireg (cfg);
 462                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, tmpreg, MONO_LVREG_LS (ins->sreg1), 32 - ins->inst_c1);
 463                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
 464                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
 465                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg), tmpreg);
 466                         allocated_vregs = TRUE;
 467                 }
 468                 break;
 469         }
 470 #endif
 471
 472         default:
 473                 break;
 474         }
 475
 476         *spec = INS_INFO (ins->opcode);
 477         return allocated_vregs;
 478 }
 479
 480 /*
 481  * mono_local_cprop:
 482  *
 483  *  A combined local copy and constant propagation pass.
 484  */
 485 void
 486 mono_local_cprop (MonoCompile *cfg)
 487 {
 488         MonoBasicBlock *bb, *bb_opt;
 489         MonoInst **defs;
 490         gint32 *def_index;
 491         int max;
 492         int filter = FILTER_IL_SEQ_POINT;
 493         int initial_max_vregs = cfg->next_vreg;
 494
 495         max = cfg->next_vreg;
 496         defs = (MonoInst **)mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * cfg->next_vreg);
 497         def_index = (gint32 *)mono_mempool_alloc (cfg->mempool, sizeof (guint32) * cfg->next_vreg);
 498         cfg->cbb = bb_opt = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoBasicBlock));
 499
 500         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
 501                 MonoInst *ins;
 502                 int ins_index;
 503                 int last_call_index;
 504
 505                 /* Manually init the defs entries used by the bblock */
 506                 MONO_BB_FOR_EACH_INS (bb, ins) {
 507                         int sregs [MONO_MAX_SRC_REGS];
 508                         int num_sregs, i;
 509
 510                         if (ins->dreg != -1) {
 511 #if SIZEOF_REGISTER == 4
 512                                 const char *spec = INS_INFO (ins->opcode);
 513                                 if (spec [MONO_INST_DEST] == 'l') {
 514                                         defs [ins->dreg + 1] = NULL;
 515                                         defs [ins->dreg + 2] = NULL;
 516                                 }
 517 #endif
 518                                 defs [ins->dreg] = NULL;
 519                         }
 520
 521                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 522                         for (i = 0; i < num_sregs; ++i) {
 523                                 int sreg = sregs [i];
 524 #if SIZEOF_REGISTER == 4
 525                                 const char *spec = INS_INFO (ins->opcode);
 526                                 if (spec [MONO_INST_SRC1 + i] == 'l') {
 527                                         defs [sreg + 1] = NULL;
 528                                         defs [sreg + 2] = NULL;
 529                                 }
 530 #endif
 531                                 defs [sreg] = NULL;
 532                         }
 533                 }
 534
 535                 ins_index = 0;
 536                 last_call_index = -1;
 537                 MONO_BB_FOR_EACH_INS (bb, ins) {
 538                         const char *spec = INS_INFO (ins->opcode);
 539                         int regtype, srcindex, sreg;
 540                         int num_sregs;
 541                         int sregs [MONO_MAX_SRC_REGS];
 542
 543                         if (ins->opcode == OP_NOP) {
 544                                 MONO_DELETE_INS (bb, ins);
 545                                 continue;
 546                         }
 547
 548                         g_assert (ins->opcode > MONO_CEE_LAST);
 549
 550                         /* FIXME: Optimize this */
 551                         if (ins->opcode == OP_LDADDR) {
 552                                 MonoInst *var = (MonoInst *)ins->inst_p0;
 553
 554                                 defs [var->dreg] = NULL;
 555                                 /*
 556                                 if (!MONO_TYPE_ISSTRUCT (var->inst_vtype))
 557                                         break;
 558                                 */
 559                         }
 560
 561                         if (MONO_IS_STORE_MEMBASE (ins)) {
 562                                 sreg = ins->dreg;
 563                                 regtype = 'i';
 564
 565                                 if ((regtype == 'i') && (sreg != -1) && defs [sreg]) {
 566                                         MonoInst *def = defs [sreg];
 567
 568                                         if ((def->opcode == OP_MOVE) && (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg])) && !vreg_is_volatile (cfg, def->sreg1)) {
 569                                                 int vreg = def->sreg1;
 570                                                 if (cfg->verbose_level > 2) printf ("CCOPY: R%d -> R%d\n", sreg, vreg);
 571                                                 ins->dreg = vreg;
 572                                         }
 573                                 }
 574                         }
 575
 576                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 577                         for (srcindex = 0; srcindex < num_sregs; ++srcindex) {
 578                                 MonoInst *def;
 579
 580                                 mono_inst_get_src_registers (ins, sregs);
 581
 582                                 regtype = spec [MONO_INST_SRC1 + srcindex];
 583                                 sreg = sregs [srcindex];
 584
 585                                 if ((regtype == ' ') || (sreg == -1) || (!defs [sreg]))
 586                                         continue;
 587
 588                                 def = defs [sreg];
 589
 590                                 /* Copy propagation */
 591                                 /*
 592                                  * The first check makes sure the source of the copy did not change since
 593                                  * the copy was made.
 594                                  * The second check avoids volatile variables.
 595                                  * The third check avoids copy propagating local vregs through a call,
 596                                  * since the lvreg will be spilled
 597                                  * The fourth check avoids copy propagating a vreg in cases where
 598                                  * it would be eliminated anyway by reverse copy propagation later,
 599                                  * because propagating it would create another use for it, thus making
 600                                  * it impossible to use reverse copy propagation.
 601                                  */
 602                                 /* Enabling this for floats trips up the fp stack */
 603                                 /*
 604                                  * Enabling this for floats on amd64 seems to cause a failure in
 605                                  * basic-math.cs, most likely because it gets rid of some r8->r4
 606                                  * conversions.
 607                                  */
 608                                 if (MONO_IS_MOVE (def) &&
 609                                         (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg])) &&
 610                                         !vreg_is_volatile (cfg, def->sreg1) &&
 611                                         /* This avoids propagating local vregs across calls */
 612                                         ((get_vreg_to_inst (cfg, def->sreg1) || !defs [def->sreg1] || (def_index [def->sreg1] >= last_call_index) || (def->opcode == OP_VMOVE))) &&
 613                                         !(defs [def->sreg1] && mono_inst_next (defs [def->sreg1], filter) == def) &&
 614                                         (!MONO_ARCH_USE_FPSTACK || (def->opcode != OP_FMOVE)) &&
 615                                         (def->opcode != OP_FMOVE)) {
 616                                         int vreg = def->sreg1;
 617
 618                                         if (cfg->verbose_level > 2) printf ("CCOPY/2: R%d -> R%d\n", sreg, vreg);
 619                                         sregs [srcindex] = vreg;
 620                                         mono_inst_set_src_registers (ins, sregs);
 621
 622                                         /* Allow further iterations */
 623                                         srcindex = -1;
 624                                         continue;
 625                                 }
 626
 627                                 /* Constant propagation */
 628                                 /* FIXME: Make is_inst_imm a macro */
 629                                 /* FIXME: Make is_inst_imm take an opcode argument */
 630                                 /* is_inst_imm is only needed for binops */
 631                                 if ((((def->opcode == OP_ICONST) || ((sizeof (gpointer) == 8) && (def->opcode == OP_I8CONST))) &&
 632                                          (((srcindex == 0) && (ins->sreg2 == -1)) || mono_arch_is_inst_imm (def->inst_c0))) ||
 633                                         (!MONO_ARCH_USE_FPSTACK && (def->opcode == OP_R8CONST))) {
 634                                         guint32 opcode2;
 635
 636                                         /* srcindex == 1 -> binop, ins->sreg2 == -1 -> unop */
 637                                         if ((srcindex == 1) && (ins->sreg1 != -1) && defs [ins->sreg1] && (defs [ins->sreg1]->opcode == OP_ICONST) && defs [ins->sreg2]) {
 638                                                 /* Both arguments are constants, perform cfold */
 639                                                 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
 640                                         } else if ((srcindex == 0) && (ins->sreg2 != -1) && defs [ins->sreg2]) {
 641                                                 /* Arg 1 is constant, swap arguments if possible */
 642                                                 int opcode = ins->opcode;
 643                                                 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
 644                                                 if (ins->opcode != opcode) {
 645                                                         /* Allow further iterations */
 646                                                         srcindex = -1;
 647                                                         continue;
 648                                                 }
 649                                         } else if ((srcindex == 0) && (ins->sreg2 == -1)) {
 650                                                 /* Constant unop, perform cfold */
 651                                                 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], NULL, TRUE);
 652                                         }
 653
 654                                         opcode2 = mono_op_to_op_imm (ins->opcode);
 655                                         if ((opcode2 != -1) && mono_arch_is_inst_imm (def->inst_c0) && ((srcindex == 1) || (ins->sreg2 == -1))) {
 656                                                 ins->opcode = opcode2;
 657                                                 if ((def->opcode == OP_I8CONST) && (sizeof (gpointer) == 4)) {
 658                                                         ins->inst_ls_word = def->inst_ls_word;
 659                                                         ins->inst_ms_word = def->inst_ms_word;
 660                                                 } else {
 661                                                         ins->inst_imm = def->inst_c0;
 662                                                 }
 663                                                 sregs [srcindex] = -1;
 664                                                 mono_inst_set_src_registers (ins, sregs);
 665
 666                                                 if ((opcode2 == OP_VOIDCALL) || (opcode2 == OP_CALL) || (opcode2 == OP_LCALL) || (opcode2 == OP_FCALL))
 667                                                         ((MonoCallInst*)ins)->fptr = (gpointer)ins->inst_imm;
 668
 669                                                 /* Allow further iterations */
 670                                                 srcindex = -1;
 671                                                 continue;
 672                                         }
 673                                         else {
 674                                                 /* Special cases */
 675 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 676                                                 if ((ins->opcode == OP_X86_LEA) && (srcindex == 1)) {
 677 #if SIZEOF_REGISTER == 8
 678                                                         /* FIXME: Use OP_PADD_IMM when the new JIT is done */
 679                                                         ins->opcode = OP_LADD_IMM;
 680 #else
 681                                                         ins->opcode = OP_ADD_IMM;
 682 #endif
 683                                                         ins->inst_imm += def->inst_c0 << ins->backend.shift_amount;
 684                                                         ins->sreg2 = -1;
 685                                                 }
 686 #endif
 687                                                 opcode2 = mono_load_membase_to_load_mem (ins->opcode);
 688                                                 if ((srcindex == 0) && (opcode2 != -1) && mono_arch_is_inst_imm (def->inst_c0)) {
 689                                                         ins->opcode = opcode2;
 690                                                         ins->inst_imm = def->inst_c0 + ins->inst_offset;
 691                                                         ins->sreg1 = -1;
 692                                                 }
 693                                         }
 694                                 }
 695                                 else if (((def->opcode == OP_ADD_IMM) || (def->opcode == OP_LADD_IMM)) && (MONO_IS_LOAD_MEMBASE (ins) || MONO_ARCH_IS_OP_MEMBASE (ins->opcode))) {
 696                                         /* ADD_IMM is created by spill_global_vars */
 697                                         /*
 698                                          * We have to guarantee that def->sreg1 haven't changed since def->dreg
 699                                          * was defined. cfg->frame_reg is assumed to remain constant.
 700                                          */
 701                                         if ((def->sreg1 == cfg->frame_reg) || ((mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1))) {
 702                                                 ins->inst_basereg = def->sreg1;
 703                                                 ins->inst_offset += def->inst_imm;
 704                                         }
 705                                 } else if ((ins->opcode == OP_ISUB_IMM) && (def->opcode == OP_IADD_IMM) && (mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1)) {
 706                                         ins->sreg1 = def->sreg1;
 707                                         ins->inst_imm -= def->inst_imm;
 708                                 } else if ((ins->opcode == OP_IADD_IMM) && (def->opcode == OP_ISUB_IMM) && (mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1)) {
 709                                         ins->sreg1 = def->sreg1;
 710                                         ins->inst_imm -= def->inst_imm;
 711                                 } else if (ins->opcode == OP_STOREI1_MEMBASE_REG &&
 712                                                    (def->opcode == OP_ICONV_TO_U1 || def->opcode == OP_ICONV_TO_I1 || def->opcode == OP_SEXT_I4 || (SIZEOF_REGISTER == 8 && def->opcode == OP_LCONV_TO_U1)) &&
 713                                                    (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg]))) {
 714                                         /* Avoid needless sign extension */
 715                                         ins->sreg1 = def->sreg1;
 716                                 } else if (ins->opcode == OP_STOREI2_MEMBASE_REG &&
 717                                                    (def->opcode == OP_ICONV_TO_U2 || def->opcode == OP_ICONV_TO_I2 || def->opcode == OP_SEXT_I4 || (SIZEOF_REGISTER == 8 && def->opcode == OP_LCONV_TO_I2)) &&
 718                                                    (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg]))) {
 719                                         /* Avoid needless sign extension */
 720                                         ins->sreg1 = def->sreg1;
 721                                 } else if (ins->opcode == OP_COMPARE_IMM && def->opcode == OP_LDADDR && ins->inst_imm == 0) {
 722                                         MonoInst dummy_arg1;
 723
 724                                         memset (&dummy_arg1, 0, sizeof (MonoInst));
 725                                         dummy_arg1.opcode = OP_ICONST;
 726                                         dummy_arg1.inst_c0 = 1;
 727
 728                                         mono_constant_fold_ins (cfg, ins, &dummy_arg1, NULL, TRUE);
 729                                 }
 730                         }
 731
 732                         g_assert (cfg->cbb == bb_opt);
 733                         g_assert (!bb_opt->code);
 734                         /* Do strength reduction here */
 735                         if (mono_strength_reduction_ins (cfg, ins, &spec) && max < cfg->next_vreg) {
 736                                 MonoInst **defs_prev = defs;
 737                                 gint32 *def_index_prev = def_index;
 738                                 guint32 prev_max = max;
 739                                 guint32 additional_vregs = cfg->next_vreg - initial_max_vregs;
 740
 741                                 /* We have more vregs so we need to reallocate defs and def_index arrays */
 742                                 max  = initial_max_vregs + additional_vregs * 2;
 743                                 defs = (MonoInst **)mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * max);
 744                                 def_index = (gint32 *)mono_mempool_alloc (cfg->mempool, sizeof (guint32) * max);
 745
 746                                 /* Keep the entries for the previous vregs, zero the rest */
 747                                 memcpy (defs, defs_prev, sizeof (MonoInst*) * prev_max);
 748                                 memset (defs + prev_max, 0, sizeof (MonoInst*) * (max - prev_max));
 749                                 memcpy (def_index, def_index_prev, sizeof (guint32) * prev_max);
 750                                 memset (def_index + prev_max, 0, sizeof (guint32) * (max - prev_max));
 751                         }
 752
 753                         if (cfg->cbb->code || (cfg->cbb != bb_opt)) {
 754                                 MonoInst *saved_prev = ins->prev;
 755
 756                                 /* If we have code in cbb, we need to replace ins with the decomposition */
 757                                 mono_replace_ins (cfg, bb, ins, &ins->prev, bb_opt, cfg->cbb);
 758                                 bb_opt->code = bb_opt->last_ins = NULL;
 759                                 bb_opt->in_count = bb_opt->out_count = 0;
 760                                 cfg->cbb = bb_opt;
 761
 762                                 /* ins is hanging, continue scanning the emitted code */
 763                                 ins = saved_prev;
 764                                 continue;
 765                         }
 766
 767                         if (spec [MONO_INST_DEST] != ' ') {
 768                                 MonoInst *def = defs [ins->dreg];
 769
 770                                 if (def && (def->opcode == OP_ADD_IMM) && (def->sreg1 == cfg->frame_reg) && (MONO_IS_STORE_MEMBASE (ins))) {
 771                                         /* ADD_IMM is created by spill_global_vars */
 772                                         /* cfg->frame_reg is assumed to remain constant */
 773                                         ins->inst_destbasereg = def->sreg1;
 774                                         ins->inst_offset += def->inst_imm;
 775                                 }
 776
 777                                 if (!MONO_IS_STORE_MEMBASE (ins) && !vreg_is_volatile (cfg, ins->dreg)) {
 778                                         defs [ins->dreg] = ins;
 779                                         def_index [ins->dreg] = ins_index;
 780                                 }
 781                         }
 782
 783                         if (MONO_IS_CALL (ins))
 784                                 last_call_index = ins_index;
 785
 786                         ins_index ++;
 787                 }
 788         }
 789 }
 790
 791 static inline gboolean
 792 reg_is_softreg_no_fpstack (int reg, const char spec)
 793 {
 794         return (spec == 'i' && reg >= MONO_MAX_IREGS)
 795                 || ((spec == 'f' && reg >= MONO_MAX_FREGS) && !MONO_ARCH_USE_FPSTACK)
 796 #ifdef MONO_ARCH_SIMD_INTRINSICS
 797                 || (spec == 'x' && reg >= MONO_MAX_XREGS)
 798 #endif
 799                 || (spec == 'v');
 800 }
 801
 802 static inline gboolean
 803 reg_is_softreg (int reg, const char spec)
 804 {
 805         return (spec == 'i' && reg >= MONO_MAX_IREGS)
 806                 || (spec == 'f' && reg >= MONO_MAX_FREGS)
 807 #ifdef MONO_ARCH_SIMD_INTRINSICS
 808                 || (spec == 'x' && reg >= MONO_MAX_XREGS)
 809 #endif
 810                 || (spec == 'v');
 811 }
 812
 813 static inline gboolean
 814 mono_is_simd_accessor (MonoInst *ins)
 815 {
 816         switch (ins->opcode) {
 817 #ifdef MONO_ARCH_SIMD_INTRINSICS
 818         case OP_INSERT_I1:
 819         case OP_INSERT_I2:
 820         case OP_INSERT_I4:
 821         case OP_INSERT_I8:
 822         case OP_INSERT_R4:
 823         case OP_INSERT_R8:
 824
 825         case OP_INSERTX_U1_SLOW:
 826         case OP_INSERTX_I4_SLOW:
 827         case OP_INSERTX_R4_SLOW:
 828         case OP_INSERTX_R8_SLOW:
 829         case OP_INSERTX_I8_SLOW:
 830                 return TRUE;
 831 #endif
 832         default:
 833                 return FALSE;
 834         }
 835 }
 836
 837 /**
 838  * mono_local_deadce:
 839  *
 840  *   Get rid of the dead assignments to local vregs like the ones created by the
 841  * copyprop pass.
 842  */
 843 void
 844 mono_local_deadce (MonoCompile *cfg)
 845 {
 846         MonoBasicBlock *bb;
 847         MonoInst *ins, *prev;
 848         MonoBitSet *used, *defined;
 849
 850         //mono_print_code (cfg, "BEFORE LOCAL-DEADCE");
 851
 852         /*
 853          * Assignments to global vregs can't be eliminated so this pass must come
 854          * after the handle_global_vregs () pass.
 855          */
 856
 857         used = mono_bitset_mp_new_noinit (cfg->mempool, cfg->next_vreg + 1);
 858         defined = mono_bitset_mp_new_noinit (cfg->mempool, cfg->next_vreg + 1);
 859
 860         /* First pass: collect liveness info */
 861         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
 862                 /* Manually init the defs entries used by the bblock */
 863                 MONO_BB_FOR_EACH_INS (bb, ins) {
 864                         const char *spec = INS_INFO (ins->opcode);
 865                         int sregs [MONO_MAX_SRC_REGS];
 866                         int num_sregs, i;
 867
 868                         if (spec [MONO_INST_DEST] != ' ') {
 869                                 mono_bitset_clear_fast (used, ins->dreg);
 870                                 mono_bitset_clear_fast (defined, ins->dreg);
 871 #if SIZEOF_REGISTER == 4
 872                                 /* Regpairs */
 873                                 mono_bitset_clear_fast (used, ins->dreg + 1);
 874                                 mono_bitset_clear_fast (defined, ins->dreg + 1);
 875 #endif
 876                         }
 877                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 878                         for (i = 0; i < num_sregs; ++i) {
 879                                 mono_bitset_clear_fast (used, sregs [i]);
 880 #if SIZEOF_REGISTER == 4
 881                                 mono_bitset_clear_fast (used, sregs [i] + 1);
 882 #endif
 883                         }
 884                 }
 885
 886                 /*
 887                  * Make a reverse pass over the instruction list
 888                  */
 889                 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
 890                         const char *spec = INS_INFO (ins->opcode);
 891                         int sregs [MONO_MAX_SRC_REGS];
 892                         int num_sregs, i;
 893                         MonoInst *prev_f = mono_inst_prev (ins, FILTER_NOP | FILTER_IL_SEQ_POINT);
 894
 895                         if (ins->opcode == OP_NOP) {
 896                                 MONO_DELETE_INS (bb, ins);
 897                                 continue;
 898                         }
 899
 900                         g_assert (ins->opcode > MONO_CEE_LAST);
 901
 902                         if (MONO_IS_NON_FP_MOVE (ins) && prev_f) {
 903                                 MonoInst *def;
 904                                 const char *spec2;
 905
 906                                 def = prev_f;
 907                                 spec2 = INS_INFO (def->opcode);
 908
 909                                 /*
 910                                  * Perform a limited kind of reverse copy propagation, i.e.
 911                                  * transform B <- FOO; A <- B into A <- FOO
 912                                  * This isn't copyprop, not deadce, but it can only be performed
 913                                  * after handle_global_vregs () has run.
 914                                  */
 915                                 if (!get_vreg_to_inst (cfg, ins->sreg1) && (spec2 [MONO_INST_DEST] != ' ') && (def->dreg == ins->sreg1) && !mono_bitset_test_fast (used, ins->sreg1) && !MONO_IS_STORE_MEMBASE (def) && reg_is_softreg (ins->sreg1, spec [MONO_INST_DEST]) && !mono_is_simd_accessor (def)) {
 916                                         if (cfg->verbose_level > 2) {
 917                                                 printf ("\tReverse copyprop in BB%d on ", bb->block_num);
 918                                                 mono_print_ins (ins);
 919                                         }
 920
 921                                         def->dreg = ins->dreg;
 922                                         MONO_DELETE_INS (bb, ins);
 923                                         spec = INS_INFO (ins->opcode);
 924                                 }
 925                         }
 926
 927                         /* Enabling this on x86 could screw up the fp stack */
 928                         if (reg_is_softreg_no_fpstack (ins->dreg, spec [MONO_INST_DEST])) {
 929                                 /*
 930                                  * Assignments to global vregs can only be eliminated if there is another
 931                                  * assignment to the same vreg later in the same bblock.
 932                                  */
 933                                 if (!mono_bitset_test_fast (used, ins->dreg) &&
 934                                         (!get_vreg_to_inst (cfg, ins->dreg) || (!bb->extended && !vreg_is_volatile (cfg, ins->dreg) && mono_bitset_test_fast (defined, ins->dreg))) &&
 935                                         MONO_INS_HAS_NO_SIDE_EFFECT (ins)) {
 936                                         /* Happens with CMOV instructions */
 937                                         if (prev_f && prev_f->opcode == OP_ICOMPARE_IMM) {
 938                                                 MonoInst *prev = prev_f;
 939                                                 /*
 940                                                  * Can't use DELETE_INS since that would interfere with the
 941                                                  * FOR_EACH_INS loop.
 942                                                  */
 943                                                 NULLIFY_INS (prev);
 944                                         }
 945                                         //printf ("DEADCE: "); mono_print_ins (ins);
 946                                         MONO_DELETE_INS (bb, ins);
 947                                         spec = INS_INFO (ins->opcode);
 948                                 }
 949
 950                                 if (spec [MONO_INST_DEST] != ' ')
 951                                         mono_bitset_clear_fast (used, ins->dreg);
 952                         }
 953
 954                         if (spec [MONO_INST_DEST] != ' ')
 955                                 mono_bitset_set_fast (defined, ins->dreg);
 956                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 957                         for (i = 0; i < num_sregs; ++i)
 958                                 mono_bitset_set_fast (used, sregs [i]);
 959                         if (MONO_IS_STORE_MEMBASE (ins))
 960                                 mono_bitset_set_fast (used, ins->dreg);
 961
 962                         if (MONO_IS_CALL (ins)) {
 963                                 MonoCallInst *call = (MonoCallInst*)ins;
 964                                 GSList *l;
 965
 966                                 if (call->out_ireg_args) {
 967                                         for (l = call->out_ireg_args; l; l = l->next) {
 968                                                 guint32 regpair, reg;
 969
 970                                                 regpair = (guint32)(gssize)(l->data);
 971                                                 reg = regpair & 0xffffff;
 972
 973                                                 mono_bitset_set_fast (used, reg);
 974                                         }
 975                                 }
 976
 977                                 if (call->out_freg_args) {
 978                                         for (l = call->out_freg_args; l; l = l->next) {
 979                                                 guint32 regpair, reg;
 980
 981                                                 regpair = (guint32)(gssize)(l->data);
 982                                                 reg = regpair & 0xffffff;
 983
 984                                                 mono_bitset_set_fast (used, reg);
 985                                         }
 986                                 }
 987                         }
 988                 }
 989         }
 990
 991         //mono_print_code (cfg, "AFTER LOCAL-DEADCE");
 992 }
 993
 994 #endif /* DISABLE_JIT */