2 * local-propagation.c: Local constant, copy and tree propagation.
4 * To make some sense of the tree mover, read mono/docs/tree-mover.txt
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
9 * Massimiliano Mantione (massi@ximian.com)
11 * (C) 2006 Novell, Inc. http://www.novell.com
12 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/mempool.h>
27 #include <mono/metadata/opcodes.h>
31 #ifndef MONO_ARCH_IS_OP_MEMBASE
32 #define MONO_ARCH_IS_OP_MEMBASE(opcode) FALSE
35 static inline MonoBitSet*
36 mono_bitset_mp_new_noinit (MonoMemPool *mp, guint32 max_size)
38 int size = mono_bitset_alloc_size (max_size, 0);
41 mem = mono_mempool_alloc (mp, size);
42 return mono_bitset_mem_new (mem, max_size, MONO_BITSET_DONT_FREE);
45 struct magic_unsigned {
56 /* http://www.hackersdelight.org/hdcodetxt/magicu.c.txt */
57 static struct magic_unsigned
58 compute_magic_unsigned (guint32 divisor) {
59 guint32 nc, delta, q1, r1, q2, r2;
60 struct magic_unsigned magu;
65 nc = -1 - (-divisor) % divisor;
68 r1 = 0x80000000 - q1 * nc;
69 q2 = 0x7FFFFFFF / divisor;
70 r2 = 0x7FFFFFFF - q2 * divisor;
82 if (r2 + 1 >= divisor - r2) {
86 r2 = 2 * r2 + 1 - divisor;
93 delta = divisor - 1 - r2;
94 } while (!gt && (q1 < delta || (q1 == delta && r1 == 0)));
96 magu.magic_number = q2 + 1;
101 /* http://www.hackersdelight.org/hdcodetxt/magic.c.txt */
102 static struct magic_signed
103 compute_magic_signed (gint32 divisor) {
105 guint32 ad, anc, delta, q1, r1, q2, r2, t;
106 const guint32 two31 = 0x80000000;
107 struct magic_signed mag;
110 t = two31 + ((unsigned)divisor >> 31);
111 anc = t - 1 - t % ad;
114 r1 = two31 - q1 * anc;
116 r2 = two31 - q2 * ad;
135 } while (q1 < delta || (q1 == delta && r1 == 0));
137 mag.magic_number = q2 + 1;
139 mag.magic_number = -mag.magic_number;
145 mono_strength_reduction_division (MonoCompile *cfg, MonoInst *ins)
147 gboolean allocated_vregs = FALSE;
149 * We don't use it on 32bit systems because on those
150 * platforms we emulate long multiplication, driving the
151 * performance back down.
153 switch (ins->opcode) {
154 case OP_IDIV_UN_IMM: {
156 #if SIZEOF_REGISTER == 8
157 guint32 dividend_reg;
161 struct magic_unsigned mag;
162 int power2 = mono_is_power_of_two (ins->inst_imm);
164 /* The decomposition doesn't handle exception throwing */
165 if (ins->inst_imm == 0)
169 ins->opcode = OP_ISHR_UN_IMM;
171 ins->inst_imm = power2;
174 allocated_vregs = TRUE;
176 * Replacement of unsigned division with multiplication,
177 * shifts and additions Hacker's Delight, chapter 10-10.
179 mag = compute_magic_unsigned (ins->inst_imm);
180 tmp_regl = alloc_lreg (cfg);
181 #if SIZEOF_REGISTER == 8
182 dividend_reg = alloc_lreg (cfg);
183 MONO_EMIT_NEW_I8CONST (cfg, tmp_regl, mag.magic_number);
184 MONO_EMIT_NEW_UNALU (cfg, OP_ZEXT_I4, dividend_reg, ins->sreg1);
185 MONO_EMIT_NEW_BIALU (cfg, OP_LMUL, tmp_regl, dividend_reg, tmp_regl);
187 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32);
188 MONO_EMIT_NEW_BIALU (cfg, OP_LADD, tmp_regl, tmp_regl, dividend_reg);
189 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, mag.shift);
191 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, 32 + mag.shift);
194 tmp_regi = alloc_ireg (cfg);
195 MONO_EMIT_NEW_ICONST (cfg, tmp_regi, mag.magic_number);
196 MONO_EMIT_NEW_BIALU (cfg, OP_BIGMUL_UN, tmp_regl, ins->sreg1, tmp_regi);
197 /* Long shifts below will be decomposed during cprop */
199 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32);
200 MONO_EMIT_NEW_BIALU (cfg, OP_IADDCC, MONO_LVREG_LS (tmp_regl), MONO_LVREG_LS (tmp_regl), ins->sreg1);
201 /* MONO_LVREG_MS (tmp_reg) is 0, save in it the carry */
202 MONO_EMIT_NEW_BIALU (cfg, OP_IADC, MONO_LVREG_MS (tmp_regl), MONO_LVREG_MS (tmp_regl), MONO_LVREG_MS (tmp_regl));
203 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, mag.shift);
205 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32 + mag.shift);
207 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ins->dreg, MONO_LVREG_LS (tmp_regl));
209 mono_jit_stats.optimized_divisions++;
214 #if SIZEOF_REGISTER == 8
215 guint32 dividend_reg;
219 struct magic_signed mag;
220 int power2 = mono_is_power_of_two (ins->inst_imm);
221 /* The decomposition doesn't handle exception throwing */
222 /* Optimization with MUL does not apply for -1, 0 and 1 divisors */
223 if (ins->inst_imm == 0 || ins->inst_imm == -1) {
225 } else if (ins->inst_imm == 1) {
226 ins->opcode = OP_MOVE;
230 allocated_vregs = TRUE;
232 guint32 r1 = alloc_ireg (cfg);
233 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, r1, ins->sreg1, 31);
234 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, r1, r1, ins->sreg1);
235 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, ins->dreg, r1, 1);
237 } else if (power2 > 0 && power2 < 31) {
238 guint32 r1 = alloc_ireg (cfg);
239 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, r1, ins->sreg1, 31);
240 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, r1, r1, (32 - power2));
241 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, r1, r1, ins->sreg1);
242 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, ins->dreg, r1, power2);
247 * Replacement of signed division with multiplication,
248 * shifts and additions Hacker's Delight, chapter 10-6.
250 mag = compute_magic_signed (ins->inst_imm);
251 tmp_regl = alloc_lreg (cfg);
252 #if SIZEOF_REGISTER == 8
253 dividend_reg = alloc_lreg (cfg);
254 MONO_EMIT_NEW_I8CONST (cfg, tmp_regl, mag.magic_number);
255 MONO_EMIT_NEW_UNALU (cfg, OP_SEXT_I4, dividend_reg, ins->sreg1);
256 MONO_EMIT_NEW_BIALU (cfg, OP_LMUL, tmp_regl, dividend_reg, tmp_regl);
257 if ((ins->inst_imm > 0 && mag.magic_number < 0) || (ins->inst_imm < 0 && mag.magic_number > 0)) {
258 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, 32);
259 if (ins->inst_imm > 0 && mag.magic_number < 0) {
260 MONO_EMIT_NEW_BIALU (cfg, OP_LADD, tmp_regl, tmp_regl, dividend_reg);
261 } else if (ins->inst_imm < 0 && mag.magic_number > 0) {
262 MONO_EMIT_NEW_BIALU (cfg, OP_LSUB, tmp_regl, tmp_regl, dividend_reg);
264 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, mag.shift);
266 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, 32 + mag.shift);
268 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, SIZEOF_REGISTER * 8 - 1);
269 MONO_EMIT_NEW_BIALU (cfg, OP_LADD, ins->dreg, ins->dreg, tmp_regl);
271 tmp_regi = alloc_ireg (cfg);
272 MONO_EMIT_NEW_ICONST (cfg, tmp_regi, mag.magic_number);
273 MONO_EMIT_NEW_BIALU (cfg, OP_BIGMUL, tmp_regl, ins->sreg1, tmp_regi);
274 if ((ins->inst_imm > 0 && mag.magic_number < 0) || (ins->inst_imm < 0 && mag.magic_number > 0)) {
275 if (ins->inst_imm > 0 && mag.magic_number < 0) {
276 /* Opposite sign, cannot overflow */
277 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, tmp_regi, MONO_LVREG_MS (tmp_regl), ins->sreg1);
278 } else if (ins->inst_imm < 0 && mag.magic_number > 0) {
279 /* Same sign, cannot overflow */
280 MONO_EMIT_NEW_BIALU (cfg, OP_ISUB, tmp_regi, MONO_LVREG_MS (tmp_regl), ins->sreg1);
282 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, tmp_regi, tmp_regi, mag.shift);
284 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, tmp_regi, MONO_LVREG_MS (tmp_regl), mag.shift);
286 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, ins->dreg, tmp_regi, SIZEOF_REGISTER * 8 - 1);
287 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, ins->dreg, ins->dreg, tmp_regi);
289 mono_jit_stats.optimized_divisions++;
293 return allocated_vregs;
297 * Replaces ins with optimized opcodes.
299 * We can emit to cbb the equivalent instructions which will be used as
300 * replacement for ins, or simply change the fields of ins. Spec needs to
301 * be updated if we silently change the opcode of ins.
303 * Returns TRUE if additional vregs were allocated.
306 mono_strength_reduction_ins (MonoCompile *cfg, MonoInst *ins, const char **spec)
308 gboolean allocated_vregs = FALSE;
310 /* FIXME: Add long/float */
311 switch (ins->opcode) {
314 if (ins->dreg == ins->sreg1) {
322 #if SIZEOF_REGISTER == 8
326 if (ins->inst_imm == 0) {
327 ins->opcode = OP_MOVE;
332 #if SIZEOF_REGISTER == 8
335 if (ins->inst_imm == 0) {
336 ins->opcode = (ins->opcode == OP_LMUL_IMM) ? OP_I8CONST : OP_ICONST;
339 } else if (ins->inst_imm == 1) {
340 ins->opcode = OP_MOVE;
341 } else if ((ins->opcode == OP_IMUL_IMM) && (ins->inst_imm == -1)) {
342 ins->opcode = OP_INEG;
343 } else if ((ins->opcode == OP_LMUL_IMM) && (ins->inst_imm == -1)) {
344 ins->opcode = OP_LNEG;
346 int power2 = mono_is_power_of_two (ins->inst_imm);
348 ins->opcode = (ins->opcode == OP_MUL_IMM) ? OP_SHL_IMM : ((ins->opcode == OP_LMUL_IMM) ? OP_LSHL_IMM : OP_ISHL_IMM);
349 ins->inst_imm = power2;
353 case OP_IREM_UN_IMM: {
354 int power2 = mono_is_power_of_two (ins->inst_imm);
357 ins->opcode = OP_IAND_IMM;
359 ins->inst_imm = (1 << power2) - 1;
365 if (!COMPILE_LLVM (cfg))
366 allocated_vregs = mono_strength_reduction_division (cfg, ins);
369 #if SIZEOF_REGISTER == 8
373 int power = mono_is_power_of_two (ins->inst_imm);
374 if (ins->inst_imm == 1) {
375 ins->opcode = OP_ICONST;
376 MONO_INST_NULLIFY_SREGS (ins);
381 } else if ((ins->inst_imm > 0) && (ins->inst_imm < (1LL << 32)) && (power != -1)) {
382 gboolean is_long = ins->opcode == OP_LREM_IMM;
383 int compensator_reg = alloc_ireg (cfg);
384 int intermediate_reg;
386 /* Based on gcc code */
388 /* Add compensation for negative numerators */
391 intermediate_reg = compensator_reg;
392 MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LSHR_IMM : OP_ISHR_IMM, intermediate_reg, ins->sreg1, is_long ? 63 : 31);
394 intermediate_reg = ins->sreg1;
397 MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LSHR_UN_IMM : OP_ISHR_UN_IMM, compensator_reg, intermediate_reg, (is_long ? 64 : 32) - power);
398 MONO_EMIT_NEW_BIALU (cfg, is_long ? OP_LADD : OP_IADD, ins->dreg, ins->sreg1, compensator_reg);
399 /* Compute remainder */
400 MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LAND_IMM : OP_AND_IMM, ins->dreg, ins->dreg, (1 << power) - 1);
401 /* Remove compensation */
402 MONO_EMIT_NEW_BIALU (cfg, is_long ? OP_LSUB : OP_ISUB, ins->dreg, ins->dreg, compensator_reg);
404 allocated_vregs = TRUE;
409 #if SIZEOF_REGISTER == 4
411 if (COMPILE_LLVM (cfg))
413 if (ins->inst_c1 == 32) {
414 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
415 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 31);
416 } else if (ins->inst_c1 == 0) {
417 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
418 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
419 } else if (ins->inst_c1 > 32) {
420 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1 - 32);
421 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 31);
423 guint32 tmpreg = alloc_ireg (cfg);
424 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, tmpreg, MONO_LVREG_MS (ins->sreg1), 32 - ins->inst_c1);
425 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
426 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
427 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->dreg), tmpreg);
428 allocated_vregs = TRUE;
432 case OP_LSHR_UN_IMM: {
433 if (COMPILE_LLVM (cfg))
435 if (ins->inst_c1 == 32) {
436 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
437 MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_MS (ins->dreg), 0);
438 } else if (ins->inst_c1 == 0) {
439 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
440 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
441 } else if (ins->inst_c1 > 32) {
442 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1 - 32);
443 MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_MS (ins->dreg), 0);
445 guint32 tmpreg = alloc_ireg (cfg);
446 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, tmpreg, MONO_LVREG_MS (ins->sreg1), 32 - ins->inst_c1);
447 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
448 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
449 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->dreg), tmpreg);
450 allocated_vregs = TRUE;
455 if (COMPILE_LLVM (cfg))
457 if (ins->inst_c1 == 32) {
458 /* just move the lower half to the upper and zero the lower word */
459 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
460 MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_LS (ins->dreg), 0);
461 } else if (ins->inst_c1 == 0) {
462 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
463 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
464 } else if (ins->inst_c1 > 32) {
465 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1 - 32);
466 MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_LS (ins->dreg), 0);
468 guint32 tmpreg = alloc_ireg (cfg);
469 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, tmpreg, MONO_LVREG_LS (ins->sreg1), 32 - ins->inst_c1);
470 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
471 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
472 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg), tmpreg);
473 allocated_vregs = TRUE;
483 *spec = INS_INFO (ins->opcode);
484 return allocated_vregs;
490 * A combined local copy and constant propagation pass.
493 mono_local_cprop (MonoCompile *cfg)
495 MonoBasicBlock *bb, *bb_opt;
499 int filter = FILTER_IL_SEQ_POINT;
500 int initial_max_vregs = cfg->next_vreg;
502 max = cfg->next_vreg;
503 defs = (MonoInst **)mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * cfg->next_vreg);
504 def_index = (gint32 *)mono_mempool_alloc (cfg->mempool, sizeof (guint32) * cfg->next_vreg);
505 cfg->cbb = bb_opt = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoBasicBlock));
507 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
512 /* Manually init the defs entries used by the bblock */
513 MONO_BB_FOR_EACH_INS (bb, ins) {
514 int sregs [MONO_MAX_SRC_REGS];
517 if (ins->dreg != -1) {
518 #if SIZEOF_REGISTER == 4
519 const char *spec = INS_INFO (ins->opcode);
520 if (spec [MONO_INST_DEST] == 'l') {
521 defs [ins->dreg + 1] = NULL;
522 defs [ins->dreg + 2] = NULL;
525 defs [ins->dreg] = NULL;
528 num_sregs = mono_inst_get_src_registers (ins, sregs);
529 for (i = 0; i < num_sregs; ++i) {
530 int sreg = sregs [i];
531 #if SIZEOF_REGISTER == 4
532 const char *spec = INS_INFO (ins->opcode);
533 if (spec [MONO_INST_SRC1 + i] == 'l') {
534 defs [sreg + 1] = NULL;
535 defs [sreg + 2] = NULL;
543 last_call_index = -1;
544 MONO_BB_FOR_EACH_INS (bb, ins) {
545 const char *spec = INS_INFO (ins->opcode);
546 int regtype, srcindex, sreg;
548 int sregs [MONO_MAX_SRC_REGS];
550 if (ins->opcode == OP_NOP) {
551 MONO_DELETE_INS (bb, ins);
555 g_assert (ins->opcode > MONO_CEE_LAST);
557 /* FIXME: Optimize this */
558 if (ins->opcode == OP_LDADDR) {
559 MonoInst *var = (MonoInst *)ins->inst_p0;
561 defs [var->dreg] = NULL;
563 if (!MONO_TYPE_ISSTRUCT (var->inst_vtype))
568 if (MONO_IS_STORE_MEMBASE (ins)) {
572 if ((regtype == 'i') && (sreg != -1) && defs [sreg]) {
573 MonoInst *def = defs [sreg];
575 if ((def->opcode == OP_MOVE) && (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg])) && !vreg_is_volatile (cfg, def->sreg1)) {
576 int vreg = def->sreg1;
577 if (cfg->verbose_level > 2) printf ("CCOPY: R%d -> R%d\n", sreg, vreg);
583 num_sregs = mono_inst_get_src_registers (ins, sregs);
584 for (srcindex = 0; srcindex < num_sregs; ++srcindex) {
587 mono_inst_get_src_registers (ins, sregs);
589 regtype = spec [MONO_INST_SRC1 + srcindex];
590 sreg = sregs [srcindex];
592 if ((regtype == ' ') || (sreg == -1) || (!defs [sreg]))
597 /* Copy propagation */
599 * The first check makes sure the source of the copy did not change since
601 * The second check avoids volatile variables.
602 * The third check avoids copy propagating local vregs through a call,
603 * since the lvreg will be spilled
604 * The fourth check avoids copy propagating a vreg in cases where
605 * it would be eliminated anyway by reverse copy propagation later,
606 * because propagating it would create another use for it, thus making
607 * it impossible to use reverse copy propagation.
609 /* Enabling this for floats trips up the fp stack */
611 * Enabling this for floats on amd64 seems to cause a failure in
612 * basic-math.cs, most likely because it gets rid of some r8->r4
615 if (MONO_IS_MOVE (def) &&
616 (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg])) &&
617 !vreg_is_volatile (cfg, def->sreg1) &&
618 /* This avoids propagating local vregs across calls */
619 ((get_vreg_to_inst (cfg, def->sreg1) || !defs [def->sreg1] || (def_index [def->sreg1] >= last_call_index) || (def->opcode == OP_VMOVE))) &&
620 !(defs [def->sreg1] && mono_inst_next (defs [def->sreg1], filter) == def) &&
621 (!MONO_ARCH_USE_FPSTACK || (def->opcode != OP_FMOVE)) &&
622 (def->opcode != OP_FMOVE)) {
623 int vreg = def->sreg1;
625 if (cfg->verbose_level > 2) printf ("CCOPY/2: R%d -> R%d\n", sreg, vreg);
626 sregs [srcindex] = vreg;
627 mono_inst_set_src_registers (ins, sregs);
629 /* Allow further iterations */
634 /* Constant propagation */
635 /* FIXME: Make is_inst_imm a macro */
636 /* FIXME: Make is_inst_imm take an opcode argument */
637 /* is_inst_imm is only needed for binops */
638 if ((((def->opcode == OP_ICONST) || ((sizeof (gpointer) == 8) && (def->opcode == OP_I8CONST))) &&
639 (((srcindex == 0) && (ins->sreg2 == -1)) || mono_arch_is_inst_imm (def->inst_c0))) ||
640 (!MONO_ARCH_USE_FPSTACK && (def->opcode == OP_R8CONST))) {
643 /* srcindex == 1 -> binop, ins->sreg2 == -1 -> unop */
644 if ((srcindex == 1) && (ins->sreg1 != -1) && defs [ins->sreg1] && (defs [ins->sreg1]->opcode == OP_ICONST) && defs [ins->sreg2]) {
645 /* Both arguments are constants, perform cfold */
646 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
647 } else if ((srcindex == 0) && (ins->sreg2 != -1) && defs [ins->sreg2]) {
648 /* Arg 1 is constant, swap arguments if possible */
649 int opcode = ins->opcode;
650 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
651 if (ins->opcode != opcode) {
652 /* Allow further iterations */
656 } else if ((srcindex == 0) && (ins->sreg2 == -1)) {
657 /* Constant unop, perform cfold */
658 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], NULL, TRUE);
661 opcode2 = mono_op_to_op_imm (ins->opcode);
662 if ((opcode2 != -1) && mono_arch_is_inst_imm (def->inst_c0) && ((srcindex == 1) || (ins->sreg2 == -1))) {
663 ins->opcode = opcode2;
664 if ((def->opcode == OP_I8CONST) && (sizeof (gpointer) == 4)) {
665 ins->inst_ls_word = def->inst_ls_word;
666 ins->inst_ms_word = def->inst_ms_word;
668 ins->inst_imm = def->inst_c0;
670 sregs [srcindex] = -1;
671 mono_inst_set_src_registers (ins, sregs);
673 if ((opcode2 == OP_VOIDCALL) || (opcode2 == OP_CALL) || (opcode2 == OP_LCALL) || (opcode2 == OP_FCALL))
674 ((MonoCallInst*)ins)->fptr = (gpointer)ins->inst_imm;
676 /* Allow further iterations */
682 #if defined(TARGET_X86) || defined(TARGET_AMD64)
683 if ((ins->opcode == OP_X86_LEA) && (srcindex == 1)) {
684 #if SIZEOF_REGISTER == 8
685 /* FIXME: Use OP_PADD_IMM when the new JIT is done */
686 ins->opcode = OP_LADD_IMM;
688 ins->opcode = OP_ADD_IMM;
690 ins->inst_imm += def->inst_c0 << ins->backend.shift_amount;
694 opcode2 = mono_load_membase_to_load_mem (ins->opcode);
695 if ((srcindex == 0) && (opcode2 != -1) && mono_arch_is_inst_imm (def->inst_c0)) {
696 ins->opcode = opcode2;
697 ins->inst_imm = def->inst_c0 + ins->inst_offset;
702 else if (((def->opcode == OP_ADD_IMM) || (def->opcode == OP_LADD_IMM)) && (MONO_IS_LOAD_MEMBASE (ins) || MONO_ARCH_IS_OP_MEMBASE (ins->opcode))) {
703 /* ADD_IMM is created by spill_global_vars */
705 * We have to guarantee that def->sreg1 haven't changed since def->dreg
706 * was defined. cfg->frame_reg is assumed to remain constant.
708 if ((def->sreg1 == cfg->frame_reg) || ((mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1))) {
709 ins->inst_basereg = def->sreg1;
710 ins->inst_offset += def->inst_imm;
712 } else if ((ins->opcode == OP_ISUB_IMM) && (def->opcode == OP_IADD_IMM) && (mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1)) {
713 ins->sreg1 = def->sreg1;
714 ins->inst_imm -= def->inst_imm;
715 } else if ((ins->opcode == OP_IADD_IMM) && (def->opcode == OP_ISUB_IMM) && (mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1)) {
716 ins->sreg1 = def->sreg1;
717 ins->inst_imm -= def->inst_imm;
718 } else if (ins->opcode == OP_STOREI1_MEMBASE_REG &&
719 (def->opcode == OP_ICONV_TO_U1 || def->opcode == OP_ICONV_TO_I1 || def->opcode == OP_SEXT_I4 || (SIZEOF_REGISTER == 8 && def->opcode == OP_LCONV_TO_U1)) &&
720 (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg]))) {
721 /* Avoid needless sign extension */
722 ins->sreg1 = def->sreg1;
723 } else if (ins->opcode == OP_STOREI2_MEMBASE_REG &&
724 (def->opcode == OP_ICONV_TO_U2 || def->opcode == OP_ICONV_TO_I2 || def->opcode == OP_SEXT_I4 || (SIZEOF_REGISTER == 8 && def->opcode == OP_LCONV_TO_I2)) &&
725 (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg]))) {
726 /* Avoid needless sign extension */
727 ins->sreg1 = def->sreg1;
728 } else if (ins->opcode == OP_COMPARE_IMM && def->opcode == OP_LDADDR && ins->inst_imm == 0) {
731 memset (&dummy_arg1, 0, sizeof (MonoInst));
732 dummy_arg1.opcode = OP_ICONST;
733 dummy_arg1.inst_c0 = 1;
735 mono_constant_fold_ins (cfg, ins, &dummy_arg1, NULL, TRUE);
739 g_assert (cfg->cbb == bb_opt);
740 g_assert (!bb_opt->code);
741 /* Do strength reduction here */
742 if (mono_strength_reduction_ins (cfg, ins, &spec) && max < cfg->next_vreg) {
743 MonoInst **defs_prev = defs;
744 gint32 *def_index_prev = def_index;
745 guint32 prev_max = max;
746 guint32 additional_vregs = cfg->next_vreg - initial_max_vregs;
748 /* We have more vregs so we need to reallocate defs and def_index arrays */
749 max = initial_max_vregs + additional_vregs * 2;
750 defs = (MonoInst **)mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * max);
751 def_index = (gint32 *)mono_mempool_alloc (cfg->mempool, sizeof (guint32) * max);
753 /* Keep the entries for the previous vregs, zero the rest */
754 memcpy (defs, defs_prev, sizeof (MonoInst*) * prev_max);
755 memset (defs + prev_max, 0, sizeof (MonoInst*) * (max - prev_max));
756 memcpy (def_index, def_index_prev, sizeof (guint32) * prev_max);
757 memset (def_index + prev_max, 0, sizeof (guint32) * (max - prev_max));
760 if (cfg->cbb->code || (cfg->cbb != bb_opt)) {
761 MonoInst *saved_prev = ins->prev;
763 /* If we have code in cbb, we need to replace ins with the decomposition */
764 mono_replace_ins (cfg, bb, ins, &ins->prev, bb_opt, cfg->cbb);
765 bb_opt->code = bb_opt->last_ins = NULL;
766 bb_opt->in_count = bb_opt->out_count = 0;
769 /* ins is hanging, continue scanning the emitted code */
774 if (spec [MONO_INST_DEST] != ' ') {
775 MonoInst *def = defs [ins->dreg];
777 if (def && (def->opcode == OP_ADD_IMM) && (def->sreg1 == cfg->frame_reg) && (MONO_IS_STORE_MEMBASE (ins))) {
778 /* ADD_IMM is created by spill_global_vars */
779 /* cfg->frame_reg is assumed to remain constant */
780 ins->inst_destbasereg = def->sreg1;
781 ins->inst_offset += def->inst_imm;
784 if (!MONO_IS_STORE_MEMBASE (ins) && !vreg_is_volatile (cfg, ins->dreg)) {
785 defs [ins->dreg] = ins;
786 def_index [ins->dreg] = ins_index;
790 if (MONO_IS_CALL (ins))
791 last_call_index = ins_index;
798 static inline gboolean
799 reg_is_softreg_no_fpstack (int reg, const char spec)
801 return (spec == 'i' && reg >= MONO_MAX_IREGS)
802 || ((spec == 'f' && reg >= MONO_MAX_FREGS) && !MONO_ARCH_USE_FPSTACK)
803 #ifdef MONO_ARCH_SIMD_INTRINSICS
804 || (spec == 'x' && reg >= MONO_MAX_XREGS)
809 static inline gboolean
810 reg_is_softreg (int reg, const char spec)
812 return (spec == 'i' && reg >= MONO_MAX_IREGS)
813 || (spec == 'f' && reg >= MONO_MAX_FREGS)
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 || (spec == 'x' && reg >= MONO_MAX_XREGS)
820 static inline gboolean
821 mono_is_simd_accessor (MonoInst *ins)
823 switch (ins->opcode) {
824 #ifdef MONO_ARCH_SIMD_INTRINSICS
832 case OP_INSERTX_U1_SLOW:
833 case OP_INSERTX_I4_SLOW:
834 case OP_INSERTX_R4_SLOW:
835 case OP_INSERTX_R8_SLOW:
836 case OP_INSERTX_I8_SLOW:
847 * Get rid of the dead assignments to local vregs like the ones created by the
851 mono_local_deadce (MonoCompile *cfg)
854 MonoInst *ins, *prev;
855 MonoBitSet *used, *defined;
857 //mono_print_code (cfg, "BEFORE LOCAL-DEADCE");
860 * Assignments to global vregs can't be eliminated so this pass must come
861 * after the handle_global_vregs () pass.
864 used = mono_bitset_mp_new_noinit (cfg->mempool, cfg->next_vreg + 1);
865 defined = mono_bitset_mp_new_noinit (cfg->mempool, cfg->next_vreg + 1);
867 /* First pass: collect liveness info */
868 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
869 /* Manually init the defs entries used by the bblock */
870 MONO_BB_FOR_EACH_INS (bb, ins) {
871 const char *spec = INS_INFO (ins->opcode);
872 int sregs [MONO_MAX_SRC_REGS];
875 if (spec [MONO_INST_DEST] != ' ') {
876 mono_bitset_clear_fast (used, ins->dreg);
877 mono_bitset_clear_fast (defined, ins->dreg);
878 #if SIZEOF_REGISTER == 4
880 mono_bitset_clear_fast (used, ins->dreg + 1);
881 mono_bitset_clear_fast (defined, ins->dreg + 1);
884 num_sregs = mono_inst_get_src_registers (ins, sregs);
885 for (i = 0; i < num_sregs; ++i) {
886 mono_bitset_clear_fast (used, sregs [i]);
887 #if SIZEOF_REGISTER == 4
888 mono_bitset_clear_fast (used, sregs [i] + 1);
894 * Make a reverse pass over the instruction list
896 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
897 const char *spec = INS_INFO (ins->opcode);
898 int sregs [MONO_MAX_SRC_REGS];
900 MonoInst *prev_f = mono_inst_prev (ins, FILTER_NOP | FILTER_IL_SEQ_POINT);
902 if (ins->opcode == OP_NOP) {
903 MONO_DELETE_INS (bb, ins);
907 g_assert (ins->opcode > MONO_CEE_LAST);
909 if (MONO_IS_NON_FP_MOVE (ins) && prev_f) {
914 spec2 = INS_INFO (def->opcode);
917 * Perform a limited kind of reverse copy propagation, i.e.
918 * transform B <- FOO; A <- B into A <- FOO
919 * This isn't copyprop, not deadce, but it can only be performed
920 * after handle_global_vregs () has run.
922 if (!get_vreg_to_inst (cfg, ins->sreg1) && (spec2 [MONO_INST_DEST] != ' ') && (def->dreg == ins->sreg1) && !mono_bitset_test_fast (used, ins->sreg1) && !MONO_IS_STORE_MEMBASE (def) && reg_is_softreg (ins->sreg1, spec [MONO_INST_DEST]) && !mono_is_simd_accessor (def)) {
923 if (cfg->verbose_level > 2) {
924 printf ("\tReverse copyprop in BB%d on ", bb->block_num);
925 mono_print_ins (ins);
928 def->dreg = ins->dreg;
929 MONO_DELETE_INS (bb, ins);
930 spec = INS_INFO (ins->opcode);
934 /* Enabling this on x86 could screw up the fp stack */
935 if (reg_is_softreg_no_fpstack (ins->dreg, spec [MONO_INST_DEST])) {
937 * Assignments to global vregs can only be eliminated if there is another
938 * assignment to the same vreg later in the same bblock.
940 if (!mono_bitset_test_fast (used, ins->dreg) &&
941 (!get_vreg_to_inst (cfg, ins->dreg) || (!bb->extended && !vreg_is_volatile (cfg, ins->dreg) && mono_bitset_test_fast (defined, ins->dreg))) &&
942 MONO_INS_HAS_NO_SIDE_EFFECT (ins)) {
943 /* Happens with CMOV instructions */
944 if (prev_f && prev_f->opcode == OP_ICOMPARE_IMM) {
945 MonoInst *prev = prev_f;
947 * Can't use DELETE_INS since that would interfere with the
952 //printf ("DEADCE: "); mono_print_ins (ins);
953 MONO_DELETE_INS (bb, ins);
954 spec = INS_INFO (ins->opcode);
957 if (spec [MONO_INST_DEST] != ' ')
958 mono_bitset_clear_fast (used, ins->dreg);
961 if (spec [MONO_INST_DEST] != ' ')
962 mono_bitset_set_fast (defined, ins->dreg);
963 num_sregs = mono_inst_get_src_registers (ins, sregs);
964 for (i = 0; i < num_sregs; ++i)
965 mono_bitset_set_fast (used, sregs [i]);
966 if (MONO_IS_STORE_MEMBASE (ins))
967 mono_bitset_set_fast (used, ins->dreg);
969 if (MONO_IS_CALL (ins)) {
970 MonoCallInst *call = (MonoCallInst*)ins;
973 if (call->out_ireg_args) {
974 for (l = call->out_ireg_args; l; l = l->next) {
975 guint32 regpair, reg;
977 regpair = (guint32)(gssize)(l->data);
978 reg = regpair & 0xffffff;
980 mono_bitset_set_fast (used, reg);
984 if (call->out_freg_args) {
985 for (l = call->out_freg_args; l; l = l->next) {
986 guint32 regpair, reg;
988 regpair = (guint32)(gssize)(l->data);
989 reg = regpair & 0xffffff;
991 mono_bitset_set_fast (used, reg);
998 //mono_print_code (cfg, "AFTER LOCAL-DEADCE");
1001 #endif /* DISABLE_JIT */