mono/mini/inssel-amd64.brg

   1 #define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG(cfg,basereg,offset,operand) do { \
   2                 MonoInst *inst; \
   3                 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
   4                 inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG; \
   5                 inst->inst_basereg = basereg; \
   6                 inst->inst_offset = offset; \
   7                 inst->sreg2 = operand; \
   8                 mono_bblock_add_inst (cfg->cbb, inst); \
   9         } while (0)
  10
  11 #define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM(cfg,basereg,offset,operand) do { \
  12                 MonoInst *inst; \
  13                 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
  14                 inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM; \
  15                 inst->inst_basereg = basereg; \
  16                 inst->inst_offset = offset; \
  17                 inst->inst_imm = operand; \
  18                 mono_bblock_add_inst (cfg->cbb, inst); \
  19         } while (0)
  20
  21 /* override the arch independant versions with fast x86 versions */
  22
  23 #undef MONO_EMIT_BOUNDS_CHECK
  24 #undef MONO_EMIT_BOUNDS_CHECK_IMM
  25
  26 #define MONO_EMIT_BOUNDS_CHECK(cfg, array_reg, array_type, array_length_field, index_reg) do { \
  27                 if (! (state->tree->flags & MONO_INST_NORANGECHECK)) { \
  28                         MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG (cfg, array_reg, G_STRUCT_OFFSET (array_type, array_length_field), index_reg); \
  29                         MONO_EMIT_NEW_COND_EXC (cfg, LE_UN, "IndexOutOfRangeException"); \
  30                 } \
  31         } while (0)
  32
  33 #define MONO_EMIT_BOUNDS_CHECK_IMM(cfg, array_reg, array_type, array_length_field, index_imm) do { \
  34                 if (! (state->tree->flags & MONO_INST_NORANGECHECK)) { \
  35                         MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM (cfg, array_reg, G_STRUCT_OFFSET (array_type, array_length_field), index_imm); \
  36                         MONO_EMIT_NEW_COND_EXC (cfg, LE_UN, "IndexOutOfRangeException"); \
  37                 } \
  38         } while (0)
  39
  40 %%
  41
  42 #
  43 # inssel-amd64.brg: burg file for special AMD64 instructions
  44 #
  45 # Author:
  46 #   Dietmar Maurer (dietmar@ximian.com)
  47 #   Paolo Molaro (lupus@ximian.com)
  48 #
  49 # (C) 2002 Ximian, Inc.
  50 #
  51
  52 stmt: OP_START_HANDLER {
  53         MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
  54         MONO_EMIT_NEW_STORE_MEMBASE (s, OP_STORE_MEMBASE_REG, spvar->inst_basereg, spvar->inst_offset, X86_ESP);
  55 }
  56
  57 stmt: CEE_ENDFINALLY {
  58         MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
  59         MONO_EMIT_NEW_LOAD_MEMBASE (s, X86_ESP, spvar->inst_basereg, spvar->inst_offset);
  60         tree->opcode = CEE_RET;
  61         mono_bblock_add_inst (s->cbb, tree);
  62 }
  63
  64 stmt: OP_ENDFILTER (reg) {
  65         MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
  66         MONO_EMIT_NEW_UNALU (s, OP_MOVE, X86_EAX, state->left->reg1);
  67         MONO_EMIT_NEW_LOAD_MEMBASE (s, X86_ESP, spvar->inst_basereg, spvar->inst_offset);
  68         tree->opcode = CEE_RET;
  69         mono_bblock_add_inst (s->cbb, tree);
  70 }
  71
  72 freg: OP_LCONV_TO_R8 (reg) {
  73         tree->sreg1 = state->left->reg1;
  74         tree->dreg = state->reg1;
  75         mono_bblock_add_inst (s->cbb, tree);
  76 }
  77
  78 freg: OP_LCONV_TO_R4 (reg) {
  79         tree->sreg1 = state->left->reg1;
  80         tree->dreg = state->reg1;
  81         mono_bblock_add_inst (s->cbb, tree);
  82 }
  83
  84 cflags: OP_COMPARE (CEE_LDIND_I4 (base), reg) {
  85         tree->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG;
  86         tree->inst_basereg = state->left->left->tree->inst_basereg;
  87         tree->inst_offset = state->left->left->tree->inst_offset;
  88         tree->sreg2 = state->right->reg1;
  89         mono_bblock_add_inst (s->cbb, tree);
  90 }
  91
  92 cflags: OP_COMPARE (CEE_LDIND_I4 (base), OP_ICONST) {
  93         tree->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM;
  94         tree->inst_basereg = state->left->left->tree->inst_basereg;
  95         tree->inst_offset = state->left->left->tree->inst_offset;
  96         tree->inst_imm = state->right->tree->inst_c0;
  97         mono_bblock_add_inst (s->cbb, tree);
  98 }
  99
 100 cflags: OP_COMPARE (reg, CEE_LDIND_I4 (base)) {
 101         tree->opcode = OP_AMD64_ICOMPARE_REG_MEMBASE;
 102         tree->sreg2 = state->right->left->tree->inst_basereg;
 103         tree->inst_offset = state->right->left->tree->inst_offset;
 104         tree->sreg1 = state->left->reg1;
 105         mono_bblock_add_inst (s->cbb, tree);
 106 }
 107
 108 stmt: CEE_STIND_I1 (base, OP_CEQ (cflags)) {
 109         tree->opcode = OP_X86_SETEQ_MEMBASE;
 110         tree->inst_offset = state->left->tree->inst_offset;
 111         tree->inst_basereg = state->left->tree->inst_basereg;
 112         mono_bblock_add_inst (s->cbb, tree);
 113 }
 114
 115 reg: OP_LOCALLOC (OP_ICONST) {
 116         if (tree->flags & MONO_INST_INIT) {
 117                 /* microcoded in mini-x86.c */
 118                 tree->sreg1 = mono_regstate_next_int (s->rs);
 119                 tree->dreg = state->reg1;
 120                 MONO_EMIT_NEW_ICONST (s, tree->sreg1, state->left->tree->inst_c0);
 121                 mono_bblock_add_inst (s->cbb, tree);
 122         } else {
 123                 guint32 size = state->left->tree->inst_c0;
 124                 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
 125                 MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, size);
 126                 MONO_EMIT_UNALU (s, tree, OP_MOVE, state->reg1, X86_ESP);
 127         }
 128 }
 129
 130 reg: OP_LOCALLOC (reg) {
 131         tree->sreg1 = state->left->tree->dreg;
 132         tree->dreg = state->reg1;
 133         mono_bblock_add_inst (s->cbb, tree);
 134 }
 135
 136 stmt: OP_SETRET (reg) {
 137         tree->opcode = OP_MOVE;
 138         tree->sreg1 = state->left->reg1;
 139         tree->dreg = X86_EAX;
 140         mono_bblock_add_inst (s->cbb, tree);
 141 }
 142
 143 stmt: OP_SETRET (reg) {
 144         MONO_EMIT_NEW_UNALU (s, OP_MOVE, X86_EDX, state->left->reg2);
 145         tree->opcode = OP_MOVE;
 146         tree->sreg1 = state->left->reg1;
 147         tree->dreg = X86_EAX;
 148         mono_bblock_add_inst (s->cbb, tree);
 149 }
 150
 151 reg: CEE_LDIND_REF (OP_REGVAR),
 152 reg: CEE_LDIND_I (OP_REGVAR),
 153 reg: CEE_LDIND_I4 (OP_REGVAR),
 154 reg: CEE_LDIND_U4 (OP_REGVAR) "0" {
 155         /* This rule might not work on all archs */
 156         state->reg1 = state->left->tree->dreg;
 157         tree->dreg = state->reg1;
 158 }
 159
 160 stmt: OP_SETRET (CEE_LDIND_REF (OP_REGVAR)),
 161 stmt: OP_SETRET (CEE_LDIND_I4 (OP_REGVAR)),
 162 stmt: OP_SETRET (CEE_LDIND_U4 (OP_REGVAR)),
 163 stmt: OP_SETRET (CEE_LDIND_I (OP_REGVAR)) {
 164         tree->opcode = OP_MOVE;
 165         tree->sreg1 = state->left->left->tree->dreg;
 166         tree->dreg = X86_EAX;
 167         mono_bblock_add_inst (s->cbb, tree);
 168 }
 169
 170 stmt: OP_SETRET (freg) {
 171         if (mono_method_signature (s->method)->ret->type == MONO_TYPE_R4)
 172                 tree->opcode = OP_AMD64_SET_XMMREG_R4;
 173         else
 174                 tree->opcode = OP_AMD64_SET_XMMREG_R8;
 175         tree->sreg1 = state->left->reg1;
 176         tree->dreg = 0; /* %xmm0 */
 177         mono_bblock_add_inst (s->cbb, tree);
 178         /* nothing to do */
 179 }
 180
 181 stmt: OP_SETRET (OP_ICONST) {
 182         if (state->left->tree->inst_c0 == 0) {
 183                 MONO_EMIT_BIALU (s, tree, CEE_XOR, AMD64_RAX, AMD64_RAX, AMD64_RAX);
 184         }
 185         else {
 186                 tree->opcode = OP_ICONST;
 187                 tree->inst_c0 = state->left->tree->inst_c0;
 188                 tree->dreg = X86_EAX;
 189                 mono_bblock_add_inst (s->cbb, tree);
 190         }
 191 }
 192
 193 stmt: OP_OUTARG (reg) {
 194         tree->opcode = OP_X86_PUSH;
 195         tree->sreg1 = state->left->reg1;
 196         mono_bblock_add_inst (s->cbb, tree);
 197 }
 198
 199 stmt: OP_OUTARG_REG (reg) {
 200         MonoCallInst *call = tree->inst_call;
 201
 202         tree->opcode = OP_MOVE;
 203         tree->sreg1 = state->left->reg1;
 204         tree->dreg = mono_regstate_next_int (s->rs);
 205         mono_bblock_add_inst (s->cbb, tree);
 206
 207         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, FALSE);
 208 }
 209
 210 # we need to reduce this code duplication with some burg syntax extension
 211 stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
 212         tree->opcode = OP_X86_PUSH;
 213         tree->sreg1 = state->left->left->tree->dreg;
 214         mono_bblock_add_inst (s->cbb, tree);
 215 }
 216
 217 stmt: OP_OUTARG (CEE_LDIND_I4 (OP_REGVAR)) {
 218         tree->opcode = OP_X86_PUSH;
 219         tree->sreg1 = state->left->left->tree->dreg;
 220         mono_bblock_add_inst (s->cbb, tree);
 221 }
 222
 223 stmt: OP_OUTARG (CEE_LDIND_U4 (OP_REGVAR)) {
 224         tree->opcode = OP_X86_PUSH;
 225         tree->sreg1 = state->left->left->tree->dreg;
 226         mono_bblock_add_inst (s->cbb, tree);
 227 }
 228
 229 stmt: OP_OUTARG (CEE_LDIND_I (OP_REGVAR)) {
 230         tree->opcode = OP_X86_PUSH;
 231         tree->sreg1 = state->left->left->tree->dreg;
 232         mono_bblock_add_inst (s->cbb, tree);
 233 }
 234
 235 stmt: OP_OUTARG (CEE_LDIND_I (base)) {
 236         tree->opcode = OP_X86_PUSH_MEMBASE;
 237         tree->inst_basereg = state->left->left->tree->inst_basereg;
 238         tree->inst_offset = state->left->left->tree->inst_offset;
 239         mono_bblock_add_inst (s->cbb, tree);
 240 }
 241
 242 stmt: OP_OUTARG (CEE_LDIND_REF (base)) {
 243         tree->opcode = OP_X86_PUSH_MEMBASE;
 244         tree->inst_basereg = state->left->left->tree->inst_basereg;
 245         tree->inst_offset = state->left->left->tree->inst_offset;
 246         mono_bblock_add_inst (s->cbb, tree);
 247 }
 248
 249 stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
 250         tree->opcode = OP_X86_PUSH;
 251         tree->sreg1 = state->left->left->tree->dreg;
 252         mono_bblock_add_inst (s->cbb, tree);
 253 }
 254
 255 stmt: OP_OUTARG (CEE_LDOBJ (reg)) {
 256         tree->opcode = OP_X86_PUSH;
 257         tree->sreg1 = state->left->reg1;
 258         mono_bblock_add_inst (s->cbb, tree);
 259 }
 260
 261 stmt: OP_OUTARG (freg) {
 262         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 263         tree->opcode = OP_STORER8_MEMBASE_REG;
 264         tree->sreg1 = state->left->reg1;
 265         tree->inst_destbasereg = X86_ESP;
 266         tree->inst_offset = 0;
 267         mono_bblock_add_inst (s->cbb, tree);
 268 }
 269
 270 stmt: OP_OUTARG_R4 (freg) {
 271         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 272         tree->opcode = OP_STORER4_MEMBASE_REG;
 273         tree->sreg1 = state->left->reg1;
 274         tree->inst_destbasereg = X86_ESP;
 275         tree->inst_offset = 0;
 276         mono_bblock_add_inst (s->cbb, tree);
 277 }
 278
 279 stmt: OP_OUTARG_R8 (freg) {
 280         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 281         tree->opcode = OP_STORER8_MEMBASE_REG;
 282         tree->sreg1 = state->left->reg1;
 283         tree->inst_destbasereg = X86_ESP;
 284         tree->inst_offset = 0;
 285         mono_bblock_add_inst (s->cbb, tree);
 286 }
 287
 288 stmt: OP_AMD64_OUTARG_XMMREG_R4 (freg) {
 289         MonoCallInst *call = tree->inst_call;
 290
 291         tree->opcode = OP_AMD64_SET_XMMREG_R4;
 292         tree->sreg1 = state->left->reg1;
 293         tree->dreg = mono_regstate_next_float (s->rs);
 294         mono_bblock_add_inst (s->cbb, tree);
 295
 296         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
 297 }
 298
 299 stmt: OP_AMD64_OUTARG_XMMREG_R8 (freg) {
 300         MonoCallInst *call = tree->inst_call;
 301
 302         tree->opcode = OP_AMD64_SET_XMMREG_R8;
 303         tree->sreg1 = state->left->reg1;
 304         tree->dreg = mono_regstate_next_float (s->rs);
 305         mono_bblock_add_inst (s->cbb, tree);
 306
 307         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
 308 }
 309
 310 stmt: OP_OUTARG_VT (CEE_LDOBJ (base)) {
 311         MonoInst *vt = state->left->left->tree;
 312         //g_print ("vt size: %d at R%d + %d\n", tree->inst_imm, vt->inst_basereg, vt->inst_offset);
 313
 314         if (!tree->inst_imm)
 315                 return;
 316
 317         if (tree->inst_imm == 8) {
 318                 /* Can't use this for < 8 since it does an 8 byte memory load */
 319                 tree->opcode = OP_X86_PUSH_MEMBASE;
 320                 tree->inst_basereg = vt->inst_basereg;
 321                 tree->inst_offset = vt->inst_offset;
 322                 mono_bblock_add_inst (s->cbb, tree);
 323         } else if (tree->inst_imm <= 20) {
 324                 int sz = tree->inst_imm;
 325                 sz += 7;
 326                 sz &= ~7;
 327                 MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, sz);
 328                 mini_emit_memcpy (s, X86_ESP, 0, vt->inst_basereg, vt->inst_offset, tree->inst_imm, 0);
 329         } else {
 330                 tree->opcode = OP_X86_PUSH_OBJ;
 331                 tree->inst_basereg = vt->inst_basereg;
 332                 tree->inst_offset = vt->inst_offset;
 333                 mono_bblock_add_inst (s->cbb, tree);
 334         }
 335 }
 336
 337 stmt: OP_OUTARG_VT (OP_ICONST) {
 338         tree->opcode = OP_X86_PUSH_IMM;
 339         tree->inst_imm = state->left->tree->inst_c0;
 340         mono_bblock_add_inst (s->cbb, tree);
 341 }
 342
 343 stmt: OP_OUTARG_VT (reg) {
 344         tree->opcode = OP_X86_PUSH;
 345         tree->sreg1 = state->left->tree->dreg;
 346         mono_bblock_add_inst (s->cbb, tree);
 347 }
 348
 349 stmt: OP_AMD64_OUTARG_ALIGN_STACK {
 350         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 351 }
 352
 353 base: OP_INARG_VT (base) {
 354         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->tree->inst_basereg,
 355                                         state->left->tree->inst_offset);
 356 }
 357
 358 reg: OP_LDADDR (OP_INARG_VT (base)) {
 359         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->left->tree->inst_basereg,
 360                                         state->left->left->tree->inst_offset);
 361 }
 362
 363 reg: CEE_LDOBJ (OP_INARG_VT (base)) {
 364         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->left->tree->inst_basereg,
 365                                         state->left->left->tree->inst_offset);
 366 }
 367
 368 reg: OP_LDADDR (OP_REGOFFSET) "1" {
 369         if (state->left->tree->inst_offset) {
 370                 tree->opcode = OP_X86_LEA_MEMBASE;
 371                 tree->sreg1 = state->left->tree->inst_basereg;
 372                 tree->inst_imm = state->left->tree->inst_offset;
 373                 tree->dreg = state->reg1;
 374         } else {
 375                 tree->opcode = OP_MOVE;
 376                 tree->sreg1 = state->left->tree->inst_basereg;
 377                 tree->dreg = state->reg1;
 378         }
 379         mono_bblock_add_inst (s->cbb, tree);
 380 }
 381
 382 reg: CEE_LDOBJ (OP_REGOFFSET) "1" {
 383         if (state->left->tree->inst_offset) {
 384                 tree->opcode = OP_X86_LEA_MEMBASE;
 385                 tree->sreg1 = state->left->tree->inst_basereg;
 386                 tree->inst_imm = state->left->tree->inst_offset;
 387                 tree->dreg = state->reg1;
 388         } else {
 389                 tree->opcode = OP_MOVE;
 390                 tree->sreg1 = state->left->tree->inst_basereg;
 391                 tree->dreg = state->reg1;
 392         }
 393         mono_bblock_add_inst (s->cbb, tree);
 394 }
 395
 396 reg: CEE_LDELEMA (reg, reg) "15" {
 397         guint32 size = mono_class_array_element_size (tree->klass);
 398
 399         MONO_EMIT_BOUNDS_CHECK (s, state->left->reg1, MonoArray, max_length, state->right->reg1);
 400
 401         if (size == 1 || size == 2 || size == 4 || size == 8) {
 402                 static const int fast_log2 [] = { 1, 0, 1, -1, 2, -1, -1, -1, 3 };
 403                 int reg;
 404
 405                 /* The array reg is 64 bits but the index reg is only 32 */
 406                 tree->dreg = mono_regstate_next_float (s->rs);
 407                 reg = mono_regstate_next_int (s->rs);
 408                 MONO_EMIT_NEW_UNALU (s, OP_SEXT_I4, reg, state->right->reg1);
 409
 410                 tree->opcode = OP_X86_LEA;
 411                 tree->dreg = state->reg1;
 412                 tree->sreg1 = state->left->reg1;
 413                 tree->sreg2 = reg;
 414                 tree->inst_imm = G_STRUCT_OFFSET (MonoArray, vector);
 415                 tree->backend.shift_amount = fast_log2 [size];
 416                 mono_bblock_add_inst (s->cbb, tree);
 417         } else {
 418                 int mult_reg = mono_regstate_next_int (s->rs);
 419                 int add_reg = mono_regstate_next_int (s->rs);
 420                 MONO_EMIT_NEW_BIALU_IMM (s, OP_MUL_IMM, mult_reg, state->right->reg1, size);
 421                 MONO_EMIT_NEW_BIALU (s, CEE_ADD, add_reg, mult_reg, state->left->reg1);
 422                 MONO_EMIT_NEW_BIALU_IMM (s, OP_ADD_IMM, state->reg1, add_reg, G_STRUCT_OFFSET (MonoArray, vector));
 423         }
 424 }
 425
 426 stmt: CEE_STIND_R8 (OP_REGVAR, freg) {
 427         /* nothing to do: the value is already on the FP stack */
 428 }
 429
 430 stmt: CEE_STIND_I4 (base, CEE_ADD (CEE_LDIND_I4 (base), OP_ICONST)) {
 431         int con = state->right->right->tree->inst_c0;
 432
 433         if (con == 1) {
 434                 tree->opcode = OP_X86_INC_MEMBASE;
 435         } else {
 436                 tree->opcode = OP_X86_ADD_MEMBASE_IMM;
 437                 tree->inst_imm = con;
 438         }
 439
 440         tree->inst_basereg = state->left->tree->inst_basereg;
 441         tree->inst_offset = state->left->tree->inst_offset;
 442         mono_bblock_add_inst (s->cbb, tree);
 443 } cost {
 444         MBTREE_TYPE *t1 = state->right->left->left->tree;
 445         MBTREE_TYPE *t2 = state->left->tree;
 446         MBCOND (t1->inst_basereg == t2->inst_basereg &&
 447                 t1->inst_offset == t2->inst_offset);
 448         return 2;
 449 }
 450
 451 stmt: CEE_STIND_I4 (base, CEE_SUB (CEE_LDIND_I4 (base), OP_ICONST)) {
 452         int con = state->right->right->tree->inst_c0;
 453
 454         if (con == 1) {
 455                 tree->opcode = OP_X86_DEC_MEMBASE;
 456         } else {
 457                 tree->opcode = OP_X86_SUB_MEMBASE_IMM;
 458                 tree->inst_imm = con;
 459         }
 460
 461         tree->inst_basereg = state->left->tree->inst_basereg;
 462         tree->inst_offset = state->left->tree->inst_offset;
 463         mono_bblock_add_inst (s->cbb, tree);
 464 } cost {
 465         MBTREE_TYPE *t1 = state->right->left->left->tree;
 466         MBTREE_TYPE *t2 = state->left->tree;
 467         MBCOND (t1->inst_basereg == t2->inst_basereg &&
 468                 t1->inst_offset == t2->inst_offset);
 469         return 2;
 470 }
 471
 472 stmt: CEE_STIND_I4 (OP_REGVAR, CEE_SUB (CEE_LDIND_I4 (OP_REGVAR), OP_ICONST)) {
 473         int con = state->right->right->tree->inst_c0;
 474         int dreg = state->left->tree->dreg;
 475         int sreg = state->right->left->left->tree->dreg;
 476
 477         if (con == 1) {
 478                 if (dreg != sreg)
 479                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 480                 tree->opcode = OP_X86_DEC_REG;
 481                 tree->dreg = tree->sreg1 = dreg;
 482         } else if (con == -1) {
 483                 if (dreg != sreg)
 484                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 485                 tree->opcode = OP_X86_INC_REG;
 486                 tree->dreg = tree->sreg1 = dreg;
 487         } else {
 488                 tree->opcode = OP_SUB_IMM;
 489                 tree->inst_imm = con;
 490                 tree->sreg1 = sreg;
 491                 tree->dreg = dreg;
 492         }
 493         mono_bblock_add_inst (s->cbb, tree);
 494 }
 495
 496 stmt: CEE_STIND_I (OP_REGVAR, CEE_ADD (CEE_LDIND_I (OP_REGVAR), OP_ICONST)),
 497 stmt: CEE_STIND_I4 (OP_REGVAR, CEE_ADD (CEE_LDIND_I4 (OP_REGVAR), OP_ICONST)) {
 498         int con = state->right->right->tree->inst_c0;
 499         int dreg = state->left->tree->dreg;
 500         int sreg = state->right->left->left->tree->dreg;
 501
 502         if (con == 1) {
 503                 if (dreg != sreg)
 504                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 505                 tree->opcode = OP_X86_INC_REG;
 506                 tree->dreg = tree->sreg1 = dreg;
 507         } else if (con == -1) {
 508                 if (dreg != sreg)
 509                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 510                 tree->opcode = OP_X86_DEC_REG;
 511                 tree->dreg = tree->sreg1 = dreg;
 512         } else {
 513                 tree->opcode = OP_ADD_IMM;
 514                 tree->inst_imm = con;
 515                 tree->sreg1 = sreg;
 516                 tree->dreg = dreg;
 517         }
 518         mono_bblock_add_inst (s->cbb, tree);
 519 }
 520
 521 reg: CEE_LDIND_I2 (OP_REGVAR) {
 522         MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);
 523 }
 524
 525 # The XOR rule
 526 stmt: CEE_STIND_I8 (OP_REGVAR, OP_ICONST),
 527 stmt: CEE_STIND_I4 (OP_REGVAR, OP_ICONST),
 528 stmt: CEE_STIND_I2 (OP_REGVAR, OP_ICONST),
 529 stmt: CEE_STIND_I1 (OP_REGVAR, OP_ICONST),
 530 stmt: CEE_STIND_REF (OP_REGVAR, OP_ICONST),
 531 stmt: CEE_STIND_I (OP_REGVAR, OP_ICONST),
 532 stmt: CEE_STIND_I8 (OP_REGVAR, OP_I8CONST),
 533 stmt: CEE_STIND_I4 (OP_REGVAR, OP_I8CONST),
 534 stmt: CEE_STIND_I2 (OP_REGVAR, OP_I8CONST),
 535 stmt: CEE_STIND_I1 (OP_REGVAR, OP_I8CONST),
 536 stmt: CEE_STIND_REF (OP_REGVAR, OP_I8CONST),
 537 stmt: CEE_STIND_I (OP_REGVAR, OP_I8CONST) {
 538         int r = state->left->tree->dreg;
 539         MONO_EMIT_BIALU (s, tree, CEE_XOR, r, r, r);
 540 } cost {
 541         MBCOND (!state->right->tree->inst_c0);
 542
 543         return 0;
 544 }
 545
 546 # on x86, fp compare overwrites EAX, so we must
 547 # either improve the local register allocator or
 548 # emit coarse opcodes which saves EAX for us.
 549
 550 reg: OP_CEQ (OP_COMPARE (freg, freg)),
 551 reg: OP_CLT (OP_COMPARE (freg, freg)),
 552 reg: OP_CGT (OP_COMPARE (freg, freg)),
 553 reg: OP_CLT_UN (OP_COMPARE (freg, freg)),
 554 reg: OP_CGT_UN (OP_COMPARE (freg, freg)) {
 555         MONO_EMIT_BIALU (s, tree, ceq_to_fceq (tree->opcode), state->reg1, state->left->left->reg1,
 556                          state->left->right->reg1);
 557 }
 558
 559 # fpcflags overwrites EAX, but this does not matter for statements
 560 # because we are the last operation in the tree.
 561
 562 stmt: CEE_BNE_UN (fpcflags),
 563 stmt: CEE_BEQ (fpcflags),
 564 stmt: CEE_BLT (fpcflags),
 565 stmt: CEE_BLT_UN (fpcflags),
 566 stmt: CEE_BGT (fpcflags),
 567 stmt: CEE_BGT_UN (fpcflags),
 568 stmt: CEE_BGE  (fpcflags),
 569 stmt: CEE_BGE_UN (fpcflags),
 570 stmt: CEE_BLE  (fpcflags),
 571 stmt: CEE_BLE_UN (fpcflags) {
 572         tree->opcode = cbranch_to_fcbranch (tree->opcode);
 573         mono_bblock_add_inst (s->cbb, tree);
 574 }
 575
 576 stmt: CEE_POP (freg) "0" {
 577         /* we need to pop the value from the x86 FP stack */
 578         MONO_EMIT_UNALU (s, tree, OP_X86_FPOP, -1, state->left->reg1);
 579 }
 580
 581 # override the rules in inssel-float.brg that work for machines with FP registers
 582
 583 freg: OP_FCONV_TO_R8 (freg) "0" {
 584         tree->opcode = OP_FMOVE;
 585         tree->sreg1 = state->left->reg1;
 586         tree->dreg = state->reg1;
 587         mono_bblock_add_inst (s->cbb, tree);
 588 }
 589
 590 freg: OP_FCONV_TO_R4 (freg) "0" {
 591         tree->opcode = OP_FMOVE;
 592         tree->sreg1 = state->left->reg1;
 593         tree->dreg = state->reg1;
 594         mono_bblock_add_inst (s->cbb, tree);
 595 }
 596
 597 reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
 598         MonoInst *base = state->right->left->tree;
 599
 600         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 601 }
 602
 603 reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
 604         MonoInst *base = state->right->left->tree;
 605
 606         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 607 }
 608
 609 reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
 610         MonoInst *base = state->right->left->tree;
 611
 612         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 613 }
 614
 615 reg: OP_LSHL (reg, reg),
 616 reg: OP_LSHR (reg, reg),
 617 reg: OP_LSHR_UN (reg, reg),
 618 reg: OP_LMUL (reg, reg),
 619 reg: OP_LDIV (reg, reg),
 620 reg: OP_LDIV_UN (reg, reg),
 621 reg: OP_LREM (reg, reg),
 622 reg: OP_LREM_UN (reg, reg),
 623 reg: OP_LMUL_OVF (reg, reg),
 624 reg: OP_LMUL_OVF_UN (reg, reg) "0" {
 625         MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
 626 }
 627
 628 reg: OP_LMUL (reg, OP_I8CONST),
 629 reg: OP_LSHL (reg, OP_ICONST),
 630 reg: OP_LSHR (reg, OP_ICONST),
 631 reg: OP_LSHR_UN (reg, OP_ICONST) {
 632         MONO_EMIT_BIALU_IMM (s, tree, bialu_to_bialu_imm (tree->opcode), state->reg1, state->left->reg1, state->right->tree->inst_c0);
 633 } cost {
 634         MBCOND (mono_arch_is_inst_imm (state->right->tree->inst_c0));
 635         return 0;
 636 }
 637
 638 reg: OP_ATOMIC_ADD_NEW_I4 (base, reg),
 639 reg: OP_ATOMIC_ADD_NEW_I8 (base, reg),
 640 reg: OP_ATOMIC_ADD_I4 (base, reg),
 641 reg: OP_ATOMIC_ADD_I8 (base, reg),
 642 reg: OP_ATOMIC_EXCHANGE_I4 (base, reg),
 643 reg: OP_ATOMIC_EXCHANGE_I8 (base, reg) {
 644         tree->opcode = tree->opcode;
 645         tree->dreg = state->reg1;
 646         tree->sreg2 = state->right->reg1;
 647         tree->inst_basereg = state->left->tree->inst_basereg;
 648         tree->inst_offset = state->left->tree->inst_offset;
 649
 650         mono_bblock_add_inst (s->cbb, tree);
 651 }
 652
 653 # Optimized call instructions
 654 # mono_arch_patch_delegate_trampoline depends on these
 655 reg: OP_CALL_REG (CEE_LDIND_I (base)),
 656 freg: OP_FCALL_REG (CEE_LDIND_I (base)),
 657 reg: OP_LCALL_REG (CEE_LDIND_I (base)) {
 658         tree->opcode = call_reg_to_call_membase (tree->opcode);
 659         tree->inst_basereg = state->left->left->tree->inst_basereg;
 660         tree->inst_offset = state->left->left->tree->inst_offset;
 661         tree->dreg = state->reg1;
 662         mono_bblock_add_inst (s->cbb, tree);
 663 }
 664
 665 stmt: OP_VOIDCALL_REG (CEE_LDIND_I (base)) {
 666         tree->opcode = call_reg_to_call_membase (tree->opcode);
 667         tree->inst_basereg = state->left->left->tree->inst_basereg;
 668         tree->inst_offset = state->left->left->tree->inst_offset;
 669         mono_bblock_add_inst (s->cbb, tree);
 670 }
 671
 672 stmt: OP_VCALL_REG (CEE_LDIND_I (base), reg) {
 673         mono_arch_emit_this_vret_args (s, (MonoCallInst*)tree, -1, -1, state->right->reg1);
 674
 675         tree->opcode = call_reg_to_call_membase (tree->opcode);
 676         tree->inst_basereg = state->left->left->tree->inst_basereg;
 677         tree->inst_offset = state->left->left->tree->inst_offset;
 678         tree->dreg = state->reg1;
 679         mono_bblock_add_inst (s->cbb, tree);
 680 }
 681
 682 %%
 683
 684 static int
 685 bialu_to_bialu_imm (int opcode)
 686 {
 687         switch (opcode) {
 688         case OP_LMUL:
 689                 return OP_LMUL_IMM;
 690         case OP_LSHL:
 691                 return OP_LSHL_IMM;
 692         case OP_LSHR:
 693                 return OP_LSHR_IMM;
 694         case OP_LSHR_UN:
 695                 return OP_LSHR_UN_IMM;
 696         default:
 697                 g_assert_not_reached ();
 698         }
 699
 700         return -1;
 701 }
 702
 703 static int
 704 cbranch_to_fcbranch (int opcode)
 705 {
 706         switch (opcode) {
 707         case CEE_BNE_UN:
 708                 return OP_FBNE_UN;
 709         case CEE_BEQ:
 710                 return OP_FBEQ;
 711         case CEE_BLT:
 712                 return OP_FBLT;
 713         case CEE_BLT_UN:
 714                 return OP_FBLT_UN;
 715         case CEE_BGT:
 716                 return OP_FBGT;
 717         case CEE_BGT_UN:
 718                 return OP_FBGT_UN;
 719         case CEE_BGE:
 720                 return OP_FBGE;
 721         case CEE_BGE_UN:
 722                 return OP_FBGE_UN;
 723         case CEE_BLE:
 724                 return OP_FBLE;
 725         case CEE_BLE_UN:
 726                 return OP_FBLE_UN;
 727         default:
 728                 g_assert_not_reached ();
 729         }
 730
 731         return -1;
 732 }
 733
 734 static int
 735 ceq_to_fceq (int opcode)
 736 {
 737         switch (opcode) {
 738         case OP_CEQ:
 739                 return OP_FCEQ;
 740         case OP_CLT:
 741                 return OP_FCLT;
 742         case OP_CGT:
 743                 return OP_FCGT;
 744         case OP_CLT_UN:
 745                 return OP_FCLT_UN;
 746         case OP_CGT_UN:
 747                 return OP_FCGT_UN;
 748         default:
 749                 g_assert_not_reached ();
 750         }
 751
 752         return -1;
 753 }
 754
 755 static int
 756 call_reg_to_call_membase (int opcode)
 757 {
 758         switch (opcode) {
 759         case OP_CALL_REG:
 760                 return OP_CALL_MEMBASE;
 761         case OP_FCALL_REG:
 762                 return OP_FCALL_MEMBASE;
 763         case OP_VCALL_REG:
 764                 return OP_VCALL_MEMBASE;
 765         case OP_LCALL_REG:
 766                 return OP_LCALL_MEMBASE;
 767         case OP_VOIDCALL_REG:
 768                 return OP_VOIDCALL_MEMBASE;
 769         default:
 770                 g_assert_not_reached ();
 771         }
 772
 773         return -1;
 774 }