mono/mini/inssel-amd64.brg

   1 #define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG(cfg,basereg,offset,operand) do { \
   2                 MonoInst *inst; \
   3                 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
   4                 inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG; \
   5                 inst->inst_basereg = basereg; \
   6                 inst->inst_offset = offset; \
   7                 inst->sreg2 = operand; \
   8                 mono_bblock_add_inst (cfg->cbb, inst); \
   9         } while (0)
  10
  11 #define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM(cfg,basereg,offset,operand) do { \
  12                 MonoInst *inst; \
  13                 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
  14                 inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM; \
  15                 inst->inst_basereg = basereg; \
  16                 inst->inst_offset = offset; \
  17                 inst->inst_imm = operand; \
  18                 mono_bblock_add_inst (cfg->cbb, inst); \
  19         } while (0)
  20
  21 /* override the arch independant versions with fast x86 versions */
  22
  23 #undef MONO_EMIT_BOUNDS_CHECK
  24 #undef MONO_EMIT_BOUNDS_CHECK_IMM
  25
  26 #define MONO_EMIT_BOUNDS_CHECK(cfg, array_reg, array_type, array_length_field, index_reg) do { \
  27                 if (! (state->tree->flags & MONO_INST_NORANGECHECK)) { \
  28                         MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG (cfg, array_reg, G_STRUCT_OFFSET (array_type, array_length_field), index_reg); \
  29                         MONO_EMIT_NEW_COND_EXC (cfg, LE_UN, "IndexOutOfRangeException"); \
  30                 } \
  31         } while (0)
  32
  33 #define MONO_EMIT_BOUNDS_CHECK_IMM(cfg, array_reg, array_type, array_length_field, index_imm) do { \
  34                 if (! (state->tree->flags & MONO_INST_NORANGECHECK)) { \
  35                         MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM (cfg, array_reg, G_STRUCT_OFFSET (array_type, array_length_field), index_imm); \
  36                         MONO_EMIT_NEW_COND_EXC (cfg, LE_UN, "IndexOutOfRangeException"); \
  37                 } \
  38         } while (0)
  39
  40 %%
  41
  42 #
  43 # inssel-amd64.brg: burg file for special AMD64 instructions
  44 #
  45 # Author:
  46 #   Dietmar Maurer (dietmar@ximian.com)
  47 #   Paolo Molaro (lupus@ximian.com)
  48 #
  49 # (C) 2002 Ximian, Inc.
  50 #
  51
  52 reg: CEE_LDIND_I8 (OP_REGVAR) {
  53         state->reg1 = state->left->tree->dreg;
  54 }
  55
  56 stmt: CEE_STIND_I8 (OP_REGVAR, reg) {
  57         MONO_EMIT_NEW_UNALU (s, OP_MOVE, state->left->tree->dreg, state->right->reg1);
  58 }
  59
  60 reg: CEE_LDIND_I1 (OP_REGVAR) {
  61         MONO_EMIT_UNALU (s, tree, OP_SEXT_I1, state->reg1, state->left->tree->dreg);}
  62
  63 reg: CEE_LDIND_I2 (OP_REGVAR) {
  64         MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);}
  65
  66 stmt: OP_START_HANDLER,
  67 stmt: OP_ENDFINALLY {
  68         mono_bblock_add_inst (s->cbb, tree);
  69 }
  70
  71 stmt: OP_ENDFILTER (reg) {
  72         tree->sreg1 = state->left->reg1;
  73         mono_bblock_add_inst (s->cbb, tree);
  74 }
  75
  76 freg: OP_LCONV_TO_R_UN (reg),
  77 freg: OP_LCONV_TO_R8 (reg) {
  78         tree->sreg1 = state->left->reg1;
  79         tree->dreg = state->reg1;
  80         mono_bblock_add_inst (s->cbb, tree);
  81 }
  82
  83 freg: OP_LCONV_TO_R4 (reg) {
  84         tree->sreg1 = state->left->reg1;
  85         tree->dreg = state->reg1;
  86         mono_bblock_add_inst (s->cbb, tree);
  87 }
  88
  89 cflags: OP_COMPARE (CEE_LDIND_I4 (base), reg) {
  90         tree->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG;
  91         tree->inst_basereg = state->left->left->tree->inst_basereg;
  92         tree->inst_offset = state->left->left->tree->inst_offset;
  93         tree->sreg2 = state->right->reg1;
  94         mono_bblock_add_inst (s->cbb, tree);
  95 }
  96
  97 cflags: OP_COMPARE (CEE_LDIND_I4 (base), OP_ICONST) {
  98         tree->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM;
  99         tree->inst_basereg = state->left->left->tree->inst_basereg;
 100         tree->inst_offset = state->left->left->tree->inst_offset;
 101         tree->inst_imm = state->right->tree->inst_c0;
 102         mono_bblock_add_inst (s->cbb, tree);
 103 }
 104
 105 cflags: OP_COMPARE (reg, CEE_LDIND_I4 (base)) {
 106         tree->opcode = OP_AMD64_ICOMPARE_REG_MEMBASE;
 107         tree->sreg2 = state->right->left->tree->inst_basereg;
 108         tree->inst_offset = state->right->left->tree->inst_offset;
 109         tree->sreg1 = state->left->reg1;
 110         mono_bblock_add_inst (s->cbb, tree);
 111 }
 112
 113 stmt: CEE_STIND_I1 (base, OP_CEQ (cflags)) {
 114         tree->opcode = OP_X86_SETEQ_MEMBASE;
 115         tree->inst_offset = state->left->tree->inst_offset;
 116         tree->inst_basereg = state->left->tree->inst_basereg;
 117         mono_bblock_add_inst (s->cbb, tree);
 118 }
 119
 120 reg: OP_LOCALLOC (OP_ICONST) {
 121         if (tree->flags & MONO_INST_INIT) {
 122                 /* microcoded in mini-x86.c */
 123                 tree->sreg1 = mono_regstate_next_int (s->rs);
 124                 tree->dreg = state->reg1;
 125                 MONO_EMIT_NEW_ICONST (s, tree->sreg1, state->left->tree->inst_c0);
 126                 mono_bblock_add_inst (s->cbb, tree);
 127         } else {
 128                 guint32 size = state->left->tree->inst_c0;
 129                 size = (size + (MONO_ARCH_LOCALLOC_ALIGNMENT - 1)) & ~ (MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
 130                 MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, size);
 131                 MONO_EMIT_UNALU (s, tree, OP_MOVE, state->reg1, X86_ESP);
 132         }
 133 }
 134
 135 reg: OP_LOCALLOC (reg) {
 136         tree->sreg1 = state->left->tree->dreg;
 137         tree->dreg = state->reg1;
 138         mono_bblock_add_inst (s->cbb, tree);
 139 }
 140
 141 stmt: OP_SETRET (reg) {
 142         tree->opcode = OP_MOVE;
 143         tree->sreg1 = state->left->reg1;
 144         tree->dreg = X86_EAX;
 145         mono_bblock_add_inst (s->cbb, tree);
 146 }
 147
 148 stmt: OP_SETRET (reg) {
 149         MONO_EMIT_NEW_UNALU (s, OP_MOVE, X86_EDX, state->left->reg2);
 150         tree->opcode = OP_MOVE;
 151         tree->sreg1 = state->left->reg1;
 152         tree->dreg = X86_EAX;
 153         mono_bblock_add_inst (s->cbb, tree);
 154 }
 155
 156 reg: CEE_LDIND_REF (OP_REGVAR),
 157 reg: CEE_LDIND_I (OP_REGVAR),
 158 reg: CEE_LDIND_I4 (OP_REGVAR),
 159 reg: CEE_LDIND_U4 (OP_REGVAR) "0" {
 160         /* This rule might not work on all archs */
 161         state->reg1 = state->left->tree->dreg;
 162         tree->dreg = state->reg1;
 163 }
 164
 165 stmt: OP_SETRET (CEE_LDIND_REF (OP_REGVAR)),
 166 stmt: OP_SETRET (CEE_LDIND_I4 (OP_REGVAR)),
 167 stmt: OP_SETRET (CEE_LDIND_U4 (OP_REGVAR)),
 168 stmt: OP_SETRET (CEE_LDIND_I (OP_REGVAR)) {
 169         tree->opcode = OP_MOVE;
 170         tree->sreg1 = state->left->left->tree->dreg;
 171         tree->dreg = X86_EAX;
 172         mono_bblock_add_inst (s->cbb, tree);
 173 }
 174
 175 stmt: OP_SETRET (freg) {
 176         if (mono_method_signature (s->method)->ret->type == MONO_TYPE_R4)
 177                 tree->opcode = OP_AMD64_SET_XMMREG_R4;
 178         else
 179                 tree->opcode = OP_AMD64_SET_XMMREG_R8;
 180         tree->sreg1 = state->left->reg1;
 181         tree->dreg = 0; /* %xmm0 */
 182         mono_bblock_add_inst (s->cbb, tree);
 183         /* nothing to do */
 184 }
 185
 186 stmt: OP_SETRET (OP_ICONST) {
 187         if (state->left->tree->inst_c0 == 0) {
 188                 MONO_EMIT_BIALU (s, tree, CEE_XOR, AMD64_RAX, AMD64_RAX, AMD64_RAX);
 189         }
 190         else {
 191                 tree->opcode = OP_ICONST;
 192                 tree->inst_c0 = state->left->tree->inst_c0;
 193                 tree->dreg = X86_EAX;
 194                 mono_bblock_add_inst (s->cbb, tree);
 195         }
 196 }
 197
 198 stmt: OP_OUTARG (reg) {
 199         tree->opcode = OP_X86_PUSH;
 200         tree->sreg1 = state->left->reg1;
 201         mono_bblock_add_inst (s->cbb, tree);
 202 }
 203
 204 stmt: OP_OUTARG_REG (reg) {
 205         MonoCallInst *call = tree->inst_call;
 206
 207         tree->opcode = OP_MOVE;
 208         tree->sreg1 = state->left->reg1;
 209         tree->dreg = mono_regstate_next_int (s->rs);
 210         mono_bblock_add_inst (s->cbb, tree);
 211
 212         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, FALSE);
 213 }
 214
 215 # we need to reduce this code duplication with some burg syntax extension
 216 stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
 217         tree->opcode = OP_X86_PUSH;
 218         tree->sreg1 = state->left->left->tree->dreg;
 219         mono_bblock_add_inst (s->cbb, tree);
 220 }
 221
 222 stmt: OP_OUTARG (CEE_LDIND_I4 (OP_REGVAR)) {
 223         tree->opcode = OP_X86_PUSH;
 224         tree->sreg1 = state->left->left->tree->dreg;
 225         mono_bblock_add_inst (s->cbb, tree);
 226 }
 227
 228 stmt: OP_OUTARG (CEE_LDIND_U4 (OP_REGVAR)) {
 229         tree->opcode = OP_X86_PUSH;
 230         tree->sreg1 = state->left->left->tree->dreg;
 231         mono_bblock_add_inst (s->cbb, tree);
 232 }
 233
 234 stmt: OP_OUTARG (CEE_LDIND_I (OP_REGVAR)) {
 235         tree->opcode = OP_X86_PUSH;
 236         tree->sreg1 = state->left->left->tree->dreg;
 237         mono_bblock_add_inst (s->cbb, tree);
 238 }
 239
 240 stmt: OP_OUTARG (CEE_LDIND_I (base)) {
 241         tree->opcode = OP_X86_PUSH_MEMBASE;
 242         tree->inst_basereg = state->left->left->tree->inst_basereg;
 243         tree->inst_offset = state->left->left->tree->inst_offset;
 244         mono_bblock_add_inst (s->cbb, tree);
 245 }
 246
 247 stmt: OP_OUTARG (CEE_LDIND_REF (base)) {
 248         tree->opcode = OP_X86_PUSH_MEMBASE;
 249         tree->inst_basereg = state->left->left->tree->inst_basereg;
 250         tree->inst_offset = state->left->left->tree->inst_offset;
 251         mono_bblock_add_inst (s->cbb, tree);
 252 }
 253
 254 stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
 255         tree->opcode = OP_X86_PUSH;
 256         tree->sreg1 = state->left->left->tree->dreg;
 257         mono_bblock_add_inst (s->cbb, tree);
 258 }
 259
 260 stmt: OP_OUTARG (CEE_LDOBJ (reg)) {
 261         tree->opcode = OP_X86_PUSH;
 262         tree->sreg1 = state->left->reg1;
 263         mono_bblock_add_inst (s->cbb, tree);
 264 }
 265
 266 stmt: OP_OUTARG (freg) {
 267         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 268         tree->opcode = OP_STORER8_MEMBASE_REG;
 269         tree->sreg1 = state->left->reg1;
 270         tree->inst_destbasereg = X86_ESP;
 271         tree->inst_offset = 0;
 272         mono_bblock_add_inst (s->cbb, tree);
 273 }
 274
 275 stmt: OP_OUTARG_R4 (freg) {
 276         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 277         tree->opcode = OP_STORER4_MEMBASE_REG;
 278         tree->sreg1 = state->left->reg1;
 279         tree->inst_destbasereg = X86_ESP;
 280         tree->inst_offset = 0;
 281         mono_bblock_add_inst (s->cbb, tree);
 282 }
 283
 284 stmt: OP_OUTARG_R8 (freg) {
 285         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 286         tree->opcode = OP_STORER8_MEMBASE_REG;
 287         tree->sreg1 = state->left->reg1;
 288         tree->inst_destbasereg = X86_ESP;
 289         tree->inst_offset = 0;
 290         mono_bblock_add_inst (s->cbb, tree);
 291 }
 292
 293 stmt: OP_AMD64_OUTARG_XMMREG_R4 (freg) {
 294         MonoCallInst *call = tree->inst_call;
 295
 296         tree->opcode = OP_AMD64_SET_XMMREG_R4;
 297         tree->sreg1 = state->left->reg1;
 298         tree->dreg = mono_regstate_next_float (s->rs);
 299         mono_bblock_add_inst (s->cbb, tree);
 300
 301         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
 302 }
 303
 304 stmt: OP_AMD64_OUTARG_XMMREG_R8 (freg) {
 305         MonoCallInst *call = tree->inst_call;
 306
 307         tree->opcode = OP_AMD64_SET_XMMREG_R8;
 308         tree->sreg1 = state->left->reg1;
 309         tree->dreg = mono_regstate_next_float (s->rs);
 310         mono_bblock_add_inst (s->cbb, tree);
 311
 312         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
 313 }
 314
 315 stmt: OP_OUTARG_VT (CEE_LDOBJ (base)) {
 316         MonoInst *vt = state->left->left->tree;
 317         //g_print ("vt size: %d at R%d + %d\n", tree->inst_imm, vt->inst_basereg, vt->inst_offset);
 318
 319         if (!tree->inst_imm)
 320                 return;
 321
 322         if (tree->inst_imm == 8) {
 323                 /* Can't use this for < 8 since it does an 8 byte memory load */
 324                 tree->opcode = OP_X86_PUSH_MEMBASE;
 325                 tree->inst_basereg = vt->inst_basereg;
 326                 tree->inst_offset = vt->inst_offset;
 327                 mono_bblock_add_inst (s->cbb, tree);
 328         } else if (tree->inst_imm <= 20) {
 329                 int sz = tree->inst_imm;
 330                 sz += 7;
 331                 sz &= ~7;
 332                 MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, sz);
 333                 mini_emit_memcpy (s, X86_ESP, 0, vt->inst_basereg, vt->inst_offset, tree->inst_imm, 0);
 334         } else {
 335                 tree->opcode = OP_X86_PUSH_OBJ;
 336                 tree->inst_basereg = vt->inst_basereg;
 337                 tree->inst_offset = vt->inst_offset;
 338                 mono_bblock_add_inst (s->cbb, tree);
 339         }
 340 }
 341
 342 stmt: OP_OUTARG_VT (OP_ICONST) {
 343         tree->opcode = OP_X86_PUSH_IMM;
 344         tree->inst_imm = state->left->tree->inst_c0;
 345         mono_bblock_add_inst (s->cbb, tree);
 346 }
 347
 348 stmt: OP_OUTARG_VT (reg) {
 349         tree->opcode = OP_X86_PUSH;
 350         tree->sreg1 = state->left->tree->dreg;
 351         mono_bblock_add_inst (s->cbb, tree);
 352 }
 353
 354 stmt: OP_AMD64_OUTARG_ALIGN_STACK {
 355         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 356 }
 357
 358 stmt: OP_AMD64_SAVE_SP_TO_LMF {
 359         mono_bblock_add_inst (s->cbb, tree);
 360 }
 361
 362 base: OP_INARG_VT (base) {
 363         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->tree->inst_basereg,
 364                                         state->left->tree->inst_offset);
 365 }
 366
 367 reg: OP_LDADDR (OP_INARG_VT (base)) {
 368         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->left->tree->inst_basereg,
 369                                         state->left->left->tree->inst_offset);
 370 }
 371
 372 reg: CEE_LDOBJ (OP_INARG_VT (base)) {
 373         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->left->tree->inst_basereg,
 374                                         state->left->left->tree->inst_offset);
 375 }
 376
 377 reg: OP_LDADDR (OP_REGOFFSET) "1" {
 378         if (state->left->tree->inst_offset) {
 379                 tree->opcode = OP_X86_LEA_MEMBASE;
 380                 tree->sreg1 = state->left->tree->inst_basereg;
 381                 tree->inst_imm = state->left->tree->inst_offset;
 382                 tree->dreg = state->reg1;
 383         } else {
 384                 tree->opcode = OP_MOVE;
 385                 tree->sreg1 = state->left->tree->inst_basereg;
 386                 tree->dreg = state->reg1;
 387         }
 388         mono_bblock_add_inst (s->cbb, tree);
 389 }
 390
 391 reg: CEE_LDOBJ (OP_REGOFFSET) "1" {
 392         if (state->left->tree->inst_offset) {
 393                 tree->opcode = OP_X86_LEA_MEMBASE;
 394                 tree->sreg1 = state->left->tree->inst_basereg;
 395                 tree->inst_imm = state->left->tree->inst_offset;
 396                 tree->dreg = state->reg1;
 397         } else {
 398                 tree->opcode = OP_MOVE;
 399                 tree->sreg1 = state->left->tree->inst_basereg;
 400                 tree->dreg = state->reg1;
 401         }
 402         mono_bblock_add_inst (s->cbb, tree);
 403 }
 404
 405 reg: CEE_LDELEMA (reg, reg) "15" {
 406         guint32 size = mono_class_array_element_size (tree->klass);
 407
 408         MONO_EMIT_BOUNDS_CHECK (s, state->left->reg1, MonoArray, max_length, state->right->reg1);
 409
 410         if (size == 1 || size == 2 || size == 4 || size == 8) {
 411                 static const int fast_log2 [] = { 1, 0, 1, -1, 2, -1, -1, -1, 3 };
 412                 int reg;
 413
 414                 /* The array reg is 64 bits but the index reg is only 32 */
 415                 tree->dreg = mono_regstate_next_float (s->rs);
 416                 reg = mono_regstate_next_int (s->rs);
 417                 MONO_EMIT_NEW_UNALU (s, OP_SEXT_I4, reg, state->right->reg1);
 418
 419                 tree->opcode = OP_X86_LEA;
 420                 tree->dreg = state->reg1;
 421                 tree->sreg1 = state->left->reg1;
 422                 tree->sreg2 = reg;
 423                 tree->inst_imm = G_STRUCT_OFFSET (MonoArray, vector);
 424                 tree->backend.shift_amount = fast_log2 [size];
 425                 mono_bblock_add_inst (s->cbb, tree);
 426         } else {
 427                 int mult_reg = mono_regstate_next_int (s->rs);
 428                 int add_reg = mono_regstate_next_int (s->rs);
 429                 MONO_EMIT_NEW_BIALU_IMM (s, OP_MUL_IMM, mult_reg, state->right->reg1, size);
 430                 MONO_EMIT_NEW_BIALU (s, CEE_ADD, add_reg, mult_reg, state->left->reg1);
 431                 MONO_EMIT_NEW_BIALU_IMM (s, OP_ADD_IMM, state->reg1, add_reg, G_STRUCT_OFFSET (MonoArray, vector));
 432         }
 433 }
 434
 435 stmt: CEE_STIND_R8 (OP_REGVAR, freg) {
 436         /* nothing to do: the value is already on the FP stack */
 437 }
 438
 439 stmt: CEE_STIND_I4 (base, CEE_ADD (CEE_LDIND_I4 (base), OP_ICONST)) {
 440         int con = state->right->right->tree->inst_c0;
 441
 442         if (con == 1) {
 443                 tree->opcode = OP_X86_INC_MEMBASE;
 444         } else {
 445                 tree->opcode = OP_X86_ADD_MEMBASE_IMM;
 446                 tree->inst_imm = con;
 447         }
 448
 449         tree->inst_basereg = state->left->tree->inst_basereg;
 450         tree->inst_offset = state->left->tree->inst_offset;
 451         mono_bblock_add_inst (s->cbb, tree);
 452 } cost {
 453         MBTREE_TYPE *t1 = state->right->left->left->tree;
 454         MBTREE_TYPE *t2 = state->left->tree;
 455         MBCOND (t1->inst_basereg == t2->inst_basereg &&
 456                 t1->inst_offset == t2->inst_offset);
 457         return 2;
 458 }
 459
 460 stmt: CEE_STIND_I4 (base, CEE_SUB (CEE_LDIND_I4 (base), OP_ICONST)) {
 461         int con = state->right->right->tree->inst_c0;
 462
 463         if (con == 1) {
 464                 tree->opcode = OP_X86_DEC_MEMBASE;
 465         } else {
 466                 tree->opcode = OP_X86_SUB_MEMBASE_IMM;
 467                 tree->inst_imm = con;
 468         }
 469
 470         tree->inst_basereg = state->left->tree->inst_basereg;
 471         tree->inst_offset = state->left->tree->inst_offset;
 472         mono_bblock_add_inst (s->cbb, tree);
 473 } cost {
 474         MBTREE_TYPE *t1 = state->right->left->left->tree;
 475         MBTREE_TYPE *t2 = state->left->tree;
 476         MBCOND (t1->inst_basereg == t2->inst_basereg &&
 477                 t1->inst_offset == t2->inst_offset);
 478         return 2;
 479 }
 480
 481 stmt: CEE_STIND_I4 (OP_REGVAR, CEE_SUB (CEE_LDIND_I4 (OP_REGVAR), OP_ICONST)) {
 482         int con = state->right->right->tree->inst_c0;
 483         int dreg = state->left->tree->dreg;
 484         int sreg = state->right->left->left->tree->dreg;
 485
 486         if (con == 1) {
 487                 if (dreg != sreg)
 488                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 489                 tree->opcode = OP_X86_DEC_REG;
 490                 tree->dreg = tree->sreg1 = dreg;
 491         } else if (con == -1) {
 492                 if (dreg != sreg)
 493                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 494                 tree->opcode = OP_X86_INC_REG;
 495                 tree->dreg = tree->sreg1 = dreg;
 496         } else {
 497                 tree->opcode = OP_SUB_IMM;
 498                 tree->inst_imm = con;
 499                 tree->sreg1 = sreg;
 500                 tree->dreg = dreg;
 501         }
 502         mono_bblock_add_inst (s->cbb, tree);
 503 }
 504
 505 stmt: CEE_STIND_I (OP_REGVAR, CEE_ADD (CEE_LDIND_I (OP_REGVAR), OP_ICONST)),
 506 stmt: CEE_STIND_I4 (OP_REGVAR, CEE_ADD (CEE_LDIND_I4 (OP_REGVAR), OP_ICONST)) {
 507         int con = state->right->right->tree->inst_c0;
 508         int dreg = state->left->tree->dreg;
 509         int sreg = state->right->left->left->tree->dreg;
 510
 511         if (con == 1) {
 512                 if (dreg != sreg)
 513                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 514                 tree->opcode = OP_X86_INC_REG;
 515                 tree->dreg = tree->sreg1 = dreg;
 516         } else if (con == -1) {
 517                 if (dreg != sreg)
 518                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 519                 tree->opcode = OP_X86_DEC_REG;
 520                 tree->dreg = tree->sreg1 = dreg;
 521         } else {
 522                 tree->opcode = OP_ADD_IMM;
 523                 tree->inst_imm = con;
 524                 tree->sreg1 = sreg;
 525                 tree->dreg = dreg;
 526         }
 527         mono_bblock_add_inst (s->cbb, tree);
 528 }
 529
 530 reg: CEE_LDIND_I2 (OP_REGVAR) {
 531         MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);
 532 }
 533
 534 # The XOR rule
 535 stmt: CEE_STIND_I8 (OP_REGVAR, OP_ICONST),
 536 stmt: CEE_STIND_I4 (OP_REGVAR, OP_ICONST),
 537 stmt: CEE_STIND_I2 (OP_REGVAR, OP_ICONST),
 538 stmt: CEE_STIND_I1 (OP_REGVAR, OP_ICONST),
 539 stmt: CEE_STIND_REF (OP_REGVAR, OP_ICONST),
 540 stmt: CEE_STIND_I (OP_REGVAR, OP_ICONST),
 541 stmt: CEE_STIND_I8 (OP_REGVAR, OP_I8CONST),
 542 stmt: CEE_STIND_I4 (OP_REGVAR, OP_I8CONST),
 543 stmt: CEE_STIND_I2 (OP_REGVAR, OP_I8CONST),
 544 stmt: CEE_STIND_I1 (OP_REGVAR, OP_I8CONST),
 545 stmt: CEE_STIND_REF (OP_REGVAR, OP_I8CONST),
 546 stmt: CEE_STIND_I (OP_REGVAR, OP_I8CONST) {
 547         int r = state->left->tree->dreg;
 548         MONO_EMIT_BIALU (s, tree, CEE_XOR, r, r, r);
 549 } cost {
 550         MBCOND (!state->right->tree->inst_c0);
 551
 552         return 0;
 553 }
 554
 555 # on x86, fp compare overwrites EAX, so we must
 556 # either improve the local register allocator or
 557 # emit coarse opcodes which saves EAX for us.
 558
 559 reg: OP_CEQ (OP_COMPARE (freg, freg)),
 560 reg: OP_CLT (OP_COMPARE (freg, freg)),
 561 reg: OP_CGT (OP_COMPARE (freg, freg)),
 562 reg: OP_CLT_UN (OP_COMPARE (freg, freg)),
 563 reg: OP_CGT_UN (OP_COMPARE (freg, freg)) {
 564         MONO_EMIT_BIALU (s, tree, ceq_to_fceq (tree->opcode), state->reg1, state->left->left->reg1,
 565                          state->left->right->reg1);
 566 }
 567
 568 # fpcflags overwrites EAX, but this does not matter for statements
 569 # because we are the last operation in the tree.
 570
 571 stmt: CEE_BNE_UN (fpcflags),
 572 stmt: CEE_BEQ (fpcflags),
 573 stmt: CEE_BLT (fpcflags),
 574 stmt: CEE_BLT_UN (fpcflags),
 575 stmt: CEE_BGT (fpcflags),
 576 stmt: CEE_BGT_UN (fpcflags),
 577 stmt: CEE_BGE  (fpcflags),
 578 stmt: CEE_BGE_UN (fpcflags),
 579 stmt: CEE_BLE  (fpcflags),
 580 stmt: CEE_BLE_UN (fpcflags) {
 581         tree->opcode = cbranch_to_fcbranch (tree->opcode);
 582         mono_bblock_add_inst (s->cbb, tree);
 583 }
 584
 585 stmt: CEE_POP (freg) "0" {
 586         /* we need to pop the value from the x86 FP stack */
 587         MONO_EMIT_UNALU (s, tree, OP_X86_FPOP, -1, state->left->reg1);
 588 }
 589
 590 # override the rules in inssel-float.brg that work for machines with FP registers
 591
 592 freg: OP_FCONV_TO_R8 (freg) "0" {
 593         tree->opcode = OP_FMOVE;
 594         tree->sreg1 = state->left->reg1;
 595         tree->dreg = state->reg1;
 596         mono_bblock_add_inst (s->cbb, tree);
 597 }
 598
 599 freg: OP_FCONV_TO_R4 (freg) "0" {
 600         tree->opcode = OP_FMOVE;
 601         tree->sreg1 = state->left->reg1;
 602         tree->dreg = state->reg1;
 603         mono_bblock_add_inst (s->cbb, tree);
 604 }
 605
 606 reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
 607         MonoInst *base = state->right->left->tree;
 608
 609         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 610 }
 611
 612 reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
 613         MonoInst *base = state->right->left->tree;
 614
 615         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 616 }
 617
 618 reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
 619         MonoInst *base = state->right->left->tree;
 620
 621         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 622 }
 623
 624 reg: OP_LSHL (reg, reg),
 625 reg: OP_LSHR (reg, reg),
 626 reg: OP_LSHR_UN (reg, reg),
 627 reg: OP_LMUL (reg, reg),
 628 reg: OP_LDIV (reg, reg),
 629 reg: OP_LDIV_UN (reg, reg),
 630 reg: OP_LREM (reg, reg),
 631 reg: OP_LREM_UN (reg, reg),
 632 reg: OP_LMUL_OVF (reg, reg),
 633 reg: OP_LMUL_OVF_UN (reg, reg),
 634 reg: OP_IMIN (reg, reg),
 635 reg: OP_IMAX (reg, reg),
 636 reg: OP_LMIN (reg, reg),
 637 reg: OP_LMAX (reg, reg) "0" {
 638         MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
 639 }
 640
 641 reg: OP_LMUL (reg, OP_I8CONST),
 642 reg: OP_LSHL (reg, OP_ICONST),
 643 reg: OP_LSHR (reg, OP_ICONST),
 644 reg: OP_LSHR_UN (reg, OP_ICONST) {
 645         MONO_EMIT_BIALU_IMM (s, tree, bialu_to_bialu_imm (tree->opcode), state->reg1, state->left->reg1, state->right->tree->inst_c0);
 646 } cost {
 647         MBCOND (mono_arch_is_inst_imm (state->right->tree->inst_c0));
 648         return 0;
 649 }
 650
 651 reg: OP_ATOMIC_ADD_NEW_I4 (base, reg),
 652 reg: OP_ATOMIC_ADD_NEW_I8 (base, reg),
 653 reg: OP_ATOMIC_ADD_I4 (base, reg),
 654 reg: OP_ATOMIC_ADD_I8 (base, reg),
 655 reg: OP_ATOMIC_EXCHANGE_I4 (base, reg),
 656 reg: OP_ATOMIC_EXCHANGE_I8 (base, reg) {
 657         tree->opcode = tree->opcode;
 658         tree->dreg = state->reg1;
 659         tree->sreg2 = state->right->reg1;
 660         tree->inst_basereg = state->left->tree->inst_basereg;
 661         tree->inst_offset = state->left->tree->inst_offset;
 662
 663         mono_bblock_add_inst (s->cbb, tree);
 664 }
 665
 666 # Optimized call instructions
 667 reg: OP_CALL_REG (CEE_LDIND_I (base)),
 668 freg: OP_FCALL_REG (CEE_LDIND_I (base)),
 669 reg: OP_LCALL_REG (CEE_LDIND_I (base)) {
 670         tree->opcode = call_reg_to_call_membase (tree->opcode);
 671         tree->inst_basereg = state->left->left->tree->inst_basereg;
 672         tree->inst_offset = state->left->left->tree->inst_offset;
 673         tree->dreg = state->reg1;
 674         mono_bblock_add_inst (s->cbb, tree);
 675 }
 676
 677 stmt: OP_VOIDCALL_REG (CEE_LDIND_I (base)) {
 678         tree->opcode = call_reg_to_call_membase (tree->opcode);
 679         tree->inst_basereg = state->left->left->tree->inst_basereg;
 680         tree->inst_offset = state->left->left->tree->inst_offset;
 681         mono_bblock_add_inst (s->cbb, tree);
 682 }
 683
 684 stmt: OP_VCALL_REG (CEE_LDIND_I (base), reg) {
 685         mono_arch_emit_this_vret_args (s, (MonoCallInst*)tree, -1, -1, state->right->reg1);
 686
 687         tree->opcode = call_reg_to_call_membase (tree->opcode);
 688         tree->inst_basereg = state->left->left->tree->inst_basereg;
 689         tree->inst_offset = state->left->left->tree->inst_offset;
 690         tree->dreg = state->reg1;
 691         mono_bblock_add_inst (s->cbb, tree);
 692 }
 693
 694 %%
 695
 696 static int
 697 bialu_to_bialu_imm (int opcode)
 698 {
 699         switch (opcode) {
 700         case OP_LMUL:
 701                 return OP_LMUL_IMM;
 702         case OP_LSHL:
 703                 return OP_LSHL_IMM;
 704         case OP_LSHR:
 705                 return OP_LSHR_IMM;
 706         case OP_LSHR_UN:
 707                 return OP_LSHR_UN_IMM;
 708         default:
 709                 g_assert_not_reached ();
 710         }
 711
 712         return -1;
 713 }
 714
 715 static int
 716 cbranch_to_fcbranch (int opcode)
 717 {
 718         switch (opcode) {
 719         case CEE_BNE_UN:
 720                 return OP_FBNE_UN;
 721         case CEE_BEQ:
 722                 return OP_FBEQ;
 723         case CEE_BLT:
 724                 return OP_FBLT;
 725         case CEE_BLT_UN:
 726                 return OP_FBLT_UN;
 727         case CEE_BGT:
 728                 return OP_FBGT;
 729         case CEE_BGT_UN:
 730                 return OP_FBGT_UN;
 731         case CEE_BGE:
 732                 return OP_FBGE;
 733         case CEE_BGE_UN:
 734                 return OP_FBGE_UN;
 735         case CEE_BLE:
 736                 return OP_FBLE;
 737         case CEE_BLE_UN:
 738                 return OP_FBLE_UN;
 739         default:
 740                 g_assert_not_reached ();
 741         }
 742
 743         return -1;
 744 }
 745
 746 static int
 747 ceq_to_fceq (int opcode)
 748 {
 749         switch (opcode) {
 750         case OP_CEQ:
 751                 return OP_FCEQ;
 752         case OP_CLT:
 753                 return OP_FCLT;
 754         case OP_CGT:
 755                 return OP_FCGT;
 756         case OP_CLT_UN:
 757                 return OP_FCLT_UN;
 758         case OP_CGT_UN:
 759                 return OP_FCGT_UN;
 760         default:
 761                 g_assert_not_reached ();
 762         }
 763
 764         return -1;
 765 }
 766
 767 static int
 768 call_reg_to_call_membase (int opcode)
 769 {
 770         switch (opcode) {
 771         case OP_CALL_REG:
 772                 return OP_CALL_MEMBASE;
 773         case OP_FCALL_REG:
 774                 return OP_FCALL_MEMBASE;
 775         case OP_VCALL_REG:
 776                 return OP_VCALL_MEMBASE;
 777         case OP_LCALL_REG:
 778                 return OP_LCALL_MEMBASE;
 779         case OP_VOIDCALL_REG:
 780                 return OP_VOIDCALL_MEMBASE;
 781         default:
 782                 g_assert_not_reached ();
 783         }
 784
 785         return -1;
 786 }