mono/mini/inssel-amd64.brg

   1 #define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG(cfg,basereg,offset,operand) do { \
   2                 MonoInst *inst; \
   3                 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
   4                 inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG; \
   5                 inst->inst_basereg = basereg; \
   6                 inst->inst_offset = offset; \
   7                 inst->sreg2 = operand; \
   8                 mono_bblock_add_inst (cfg->cbb, inst); \
   9         } while (0)
  10
  11 #define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM(cfg,basereg,offset,operand) do { \
  12                 MonoInst *inst; \
  13                 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
  14                 inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM; \
  15                 inst->inst_basereg = basereg; \
  16                 inst->inst_offset = offset; \
  17                 inst->inst_imm = operand; \
  18                 mono_bblock_add_inst (cfg->cbb, inst); \
  19         } while (0)
  20
  21 /* override the arch independant versions with fast x86 versions */
  22
  23 #undef MONO_EMIT_BOUNDS_CHECK
  24 #undef MONO_EMIT_BOUNDS_CHECK_IMM
  25
  26 #define MONO_EMIT_BOUNDS_CHECK(cfg, array_reg, array_type, array_length_field, index_reg) do { \
  27                 if (! (state->tree->flags & MONO_INST_NORANGECHECK)) { \
  28                         MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG (cfg, array_reg, G_STRUCT_OFFSET (array_type, array_length_field), index_reg); \
  29                         MONO_EMIT_NEW_COND_EXC (cfg, LE_UN, "IndexOutOfRangeException"); \
  30                 } \
  31         } while (0)
  32
  33 #define MONO_EMIT_BOUNDS_CHECK_IMM(cfg, array_reg, array_type, array_length_field, index_imm) do { \
  34                 if (! (state->tree->flags & MONO_INST_NORANGECHECK)) { \
  35                         MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM (cfg, array_reg, G_STRUCT_OFFSET (array_type, array_length_field), index_imm); \
  36                         MONO_EMIT_NEW_COND_EXC (cfg, LE_UN, "IndexOutOfRangeException"); \
  37                 } \
  38         } while (0)
  39
  40 %%
  41
  42 #
  43 # inssel-amd64.brg: burg file for special AMD64 instructions
  44 #
  45 # Author:
  46 #   Dietmar Maurer (dietmar@ximian.com)
  47 #   Paolo Molaro (lupus@ximian.com)
  48 #
  49 # (C) 2002 Ximian, Inc.
  50 #
  51
  52 reg: CEE_LDIND_I8 (OP_REGVAR) {
  53         state->reg1 = state->left->tree->dreg;
  54 }
  55
  56 stmt: CEE_STIND_I8 (OP_REGVAR, reg) {
  57         MONO_EMIT_NEW_UNALU (s, OP_MOVE, state->left->tree->dreg, state->right->reg1);
  58 }
  59
  60 reg: CEE_LDIND_I1 (OP_REGVAR) {
  61         MONO_EMIT_UNALU (s, tree, OP_SEXT_I1, state->reg1, state->left->tree->dreg);}
  62
  63 reg: CEE_LDIND_I2 (OP_REGVAR) {
  64         MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);}
  65
  66 stmt: OP_START_HANDLER,
  67 stmt: OP_ENDFINALLY {
  68         mono_bblock_add_inst (s->cbb, tree);
  69 }
  70
  71 stmt: OP_ENDFILTER (reg) {
  72         tree->sreg1 = state->left->reg1;
  73         mono_bblock_add_inst (s->cbb, tree);
  74 }
  75
  76 freg: OP_LCONV_TO_R_UN (reg),
  77 freg: OP_LCONV_TO_R8 (reg) {
  78         tree->sreg1 = state->left->reg1;
  79         tree->dreg = state->reg1;
  80         mono_bblock_add_inst (s->cbb, tree);
  81 }
  82
  83 freg: OP_LCONV_TO_R4 (reg) {
  84         tree->sreg1 = state->left->reg1;
  85         tree->dreg = state->reg1;
  86         mono_bblock_add_inst (s->cbb, tree);
  87 }
  88
  89 cflags: OP_COMPARE (CEE_LDIND_I4 (base), reg) {
  90         tree->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG;
  91         tree->inst_basereg = state->left->left->tree->inst_basereg;
  92         tree->inst_offset = state->left->left->tree->inst_offset;
  93         tree->sreg2 = state->right->reg1;
  94         mono_bblock_add_inst (s->cbb, tree);
  95 }
  96
  97 cflags: OP_COMPARE (CEE_LDIND_I4 (base), OP_ICONST) {
  98         tree->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM;
  99         tree->inst_basereg = state->left->left->tree->inst_basereg;
 100         tree->inst_offset = state->left->left->tree->inst_offset;
 101         tree->inst_imm = state->right->tree->inst_c0;
 102         mono_bblock_add_inst (s->cbb, tree);
 103 }
 104
 105 cflags: OP_COMPARE (reg, CEE_LDIND_I4 (base)) {
 106         tree->opcode = OP_AMD64_ICOMPARE_REG_MEMBASE;
 107         tree->sreg2 = state->right->left->tree->inst_basereg;
 108         tree->inst_offset = state->right->left->tree->inst_offset;
 109         tree->sreg1 = state->left->reg1;
 110         mono_bblock_add_inst (s->cbb, tree);
 111 }
 112
 113 stmt: CEE_STIND_I1 (base, OP_CEQ (cflags)) {
 114         tree->opcode = OP_X86_SETEQ_MEMBASE;
 115         tree->inst_offset = state->left->tree->inst_offset;
 116         tree->inst_basereg = state->left->tree->inst_basereg;
 117         mono_bblock_add_inst (s->cbb, tree);
 118 }
 119
 120 reg: OP_LOCALLOC (OP_ICONST) {
 121         if (tree->flags & MONO_INST_INIT) {
 122                 /* microcoded in mini-x86.c */
 123                 tree->sreg1 = mono_regstate_next_int (s->rs);
 124                 tree->dreg = state->reg1;
 125                 MONO_EMIT_NEW_ICONST (s, tree->sreg1, state->left->tree->inst_c0);
 126                 mono_bblock_add_inst (s->cbb, tree);
 127         } else {
 128                 guint32 size = state->left->tree->inst_c0;
 129                 size = (size + (MONO_ARCH_LOCALLOC_ALIGNMENT - 1)) & ~ (MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
 130                 MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, size);
 131                 MONO_EMIT_UNALU (s, tree, OP_MOVE, state->reg1, X86_ESP);
 132         }
 133 }
 134
 135 reg: OP_LOCALLOC (reg) {
 136         tree->sreg1 = state->left->tree->dreg;
 137         tree->dreg = state->reg1;
 138         mono_bblock_add_inst (s->cbb, tree);
 139 }
 140
 141 stmt: OP_SETRET (reg) {
 142         tree->opcode = OP_MOVE;
 143         tree->sreg1 = state->left->reg1;
 144         tree->dreg = X86_EAX;
 145         mono_bblock_add_inst (s->cbb, tree);
 146 }
 147
 148 stmt: OP_SETRET (reg) {
 149         MONO_EMIT_NEW_UNALU (s, OP_MOVE, X86_EDX, state->left->reg2);
 150         tree->opcode = OP_MOVE;
 151         tree->sreg1 = state->left->reg1;
 152         tree->dreg = X86_EAX;
 153         mono_bblock_add_inst (s->cbb, tree);
 154 }
 155
 156 reg: CEE_LDIND_REF (OP_REGVAR),
 157 reg: CEE_LDIND_I (OP_REGVAR),
 158 reg: CEE_LDIND_I4 (OP_REGVAR),
 159 reg: CEE_LDIND_U4 (OP_REGVAR) "0" {
 160         /* This rule might not work on all archs */
 161         state->reg1 = state->left->tree->dreg;
 162         tree->dreg = state->reg1;
 163 }
 164
 165 stmt: OP_SETRET (CEE_LDIND_REF (OP_REGVAR)),
 166 stmt: OP_SETRET (CEE_LDIND_I4 (OP_REGVAR)),
 167 stmt: OP_SETRET (CEE_LDIND_U4 (OP_REGVAR)),
 168 stmt: OP_SETRET (CEE_LDIND_I (OP_REGVAR)) {
 169         tree->opcode = OP_MOVE;
 170         tree->sreg1 = state->left->left->tree->dreg;
 171         tree->dreg = X86_EAX;
 172         mono_bblock_add_inst (s->cbb, tree);
 173 }
 174
 175 stmt: OP_SETRET (freg) {
 176         if (mono_method_signature (s->method)->ret->type == MONO_TYPE_R4)
 177                 tree->opcode = OP_AMD64_SET_XMMREG_R4;
 178         else
 179                 tree->opcode = OP_AMD64_SET_XMMREG_R8;
 180         tree->sreg1 = state->left->reg1;
 181         tree->dreg = 0; /* %xmm0 */
 182         mono_bblock_add_inst (s->cbb, tree);
 183         /* nothing to do */
 184 }
 185
 186 stmt: OP_SETRET (OP_ICONST) {
 187         if (state->left->tree->inst_c0 == 0) {
 188                 MONO_EMIT_BIALU (s, tree, CEE_XOR, AMD64_RAX, AMD64_RAX, AMD64_RAX);
 189         }
 190         else {
 191                 tree->opcode = OP_ICONST;
 192                 tree->inst_c0 = state->left->tree->inst_c0;
 193                 tree->dreg = X86_EAX;
 194                 mono_bblock_add_inst (s->cbb, tree);
 195         }
 196 }
 197
 198 stmt: OP_OUTARG (reg) {
 199         tree->opcode = OP_X86_PUSH;
 200         tree->sreg1 = state->left->reg1;
 201         mono_bblock_add_inst (s->cbb, tree);
 202 }
 203
 204 stmt: OP_OUTARG_REG (reg) {
 205         MonoCallInst *call = tree->inst_call;
 206
 207         tree->opcode = OP_MOVE;
 208         tree->sreg1 = state->left->reg1;
 209         tree->dreg = mono_regstate_next_int (s->rs);
 210         mono_bblock_add_inst (s->cbb, tree);
 211
 212         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, FALSE);
 213 }
 214
 215 # we need to reduce this code duplication with some burg syntax extension
 216 stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
 217         tree->opcode = OP_X86_PUSH;
 218         tree->sreg1 = state->left->left->tree->dreg;
 219         mono_bblock_add_inst (s->cbb, tree);
 220 }
 221
 222 stmt: OP_OUTARG (CEE_LDIND_I4 (OP_REGVAR)) {
 223         tree->opcode = OP_X86_PUSH;
 224         tree->sreg1 = state->left->left->tree->dreg;
 225         mono_bblock_add_inst (s->cbb, tree);
 226 }
 227
 228 stmt: OP_OUTARG (CEE_LDIND_U4 (OP_REGVAR)) {
 229         tree->opcode = OP_X86_PUSH;
 230         tree->sreg1 = state->left->left->tree->dreg;
 231         mono_bblock_add_inst (s->cbb, tree);
 232 }
 233
 234 stmt: OP_OUTARG (CEE_LDIND_I (OP_REGVAR)) {
 235         tree->opcode = OP_X86_PUSH;
 236         tree->sreg1 = state->left->left->tree->dreg;
 237         mono_bblock_add_inst (s->cbb, tree);
 238 }
 239
 240 stmt: OP_OUTARG (CEE_LDIND_I (base)) {
 241         tree->opcode = OP_X86_PUSH_MEMBASE;
 242         tree->inst_basereg = state->left->left->tree->inst_basereg;
 243         tree->inst_offset = state->left->left->tree->inst_offset;
 244         mono_bblock_add_inst (s->cbb, tree);
 245 }
 246
 247 stmt: OP_OUTARG (CEE_LDIND_REF (base)) {
 248         tree->opcode = OP_X86_PUSH_MEMBASE;
 249         tree->inst_basereg = state->left->left->tree->inst_basereg;
 250         tree->inst_offset = state->left->left->tree->inst_offset;
 251         mono_bblock_add_inst (s->cbb, tree);
 252 }
 253
 254 stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
 255         tree->opcode = OP_X86_PUSH;
 256         tree->sreg1 = state->left->left->tree->dreg;
 257         mono_bblock_add_inst (s->cbb, tree);
 258 }
 259
 260 stmt: OP_OUTARG (CEE_LDOBJ (reg)) {
 261         tree->opcode = OP_X86_PUSH;
 262         tree->sreg1 = state->left->reg1;
 263         mono_bblock_add_inst (s->cbb, tree);
 264 }
 265
 266 stmt: OP_OUTARG (freg) {
 267         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 268         tree->opcode = OP_STORER8_MEMBASE_REG;
 269         tree->sreg1 = state->left->reg1;
 270         tree->inst_destbasereg = X86_ESP;
 271         tree->inst_offset = 0;
 272         mono_bblock_add_inst (s->cbb, tree);
 273 }
 274
 275 stmt: OP_OUTARG_R4 (freg) {
 276         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 277         tree->opcode = OP_STORER4_MEMBASE_REG;
 278         tree->sreg1 = state->left->reg1;
 279         tree->inst_destbasereg = X86_ESP;
 280         tree->inst_offset = 0;
 281         mono_bblock_add_inst (s->cbb, tree);
 282 }
 283
 284 stmt: OP_OUTARG_R8 (freg) {
 285         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 286         tree->opcode = OP_STORER8_MEMBASE_REG;
 287         tree->sreg1 = state->left->reg1;
 288         tree->inst_destbasereg = X86_ESP;
 289         tree->inst_offset = 0;
 290         mono_bblock_add_inst (s->cbb, tree);
 291 }
 292
 293 stmt: OP_AMD64_OUTARG_XMMREG_R4 (freg) {
 294         MonoCallInst *call = tree->inst_call;
 295
 296         tree->opcode = OP_AMD64_SET_XMMREG_R4;
 297         tree->sreg1 = state->left->reg1;
 298         tree->dreg = mono_regstate_next_float (s->rs);
 299         mono_bblock_add_inst (s->cbb, tree);
 300
 301         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
 302 }
 303
 304 stmt: OP_AMD64_OUTARG_XMMREG_R8 (freg) {
 305         MonoCallInst *call = tree->inst_call;
 306
 307         tree->opcode = OP_AMD64_SET_XMMREG_R8;
 308         tree->sreg1 = state->left->reg1;
 309         tree->dreg = mono_regstate_next_float (s->rs);
 310         mono_bblock_add_inst (s->cbb, tree);
 311
 312         mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
 313 }
 314
 315 stmt: OP_OUTARG_VT (CEE_LDOBJ (base)) {
 316         MonoInst *vt = state->left->left->tree;
 317         //g_print ("vt size: %d at R%d + %d\n", tree->inst_imm, vt->inst_basereg, vt->inst_offset);
 318
 319         if (!tree->inst_imm)
 320                 return;
 321
 322         if (tree->inst_imm == 8) {
 323                 /* Can't use this for < 8 since it does an 8 byte memory load */
 324                 tree->opcode = OP_X86_PUSH_MEMBASE;
 325                 tree->inst_basereg = vt->inst_basereg;
 326                 tree->inst_offset = vt->inst_offset;
 327                 mono_bblock_add_inst (s->cbb, tree);
 328         } else if (tree->inst_imm <= 20) {
 329                 int sz = tree->inst_imm;
 330                 sz += 7;
 331                 sz &= ~7;
 332                 MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, sz);
 333                 mini_emit_memcpy (s, X86_ESP, 0, vt->inst_basereg, vt->inst_offset, tree->inst_imm, 0);
 334         } else {
 335                 tree->opcode = OP_X86_PUSH_OBJ;
 336                 tree->inst_basereg = vt->inst_basereg;
 337                 tree->inst_offset = vt->inst_offset;
 338                 mono_bblock_add_inst (s->cbb, tree);
 339         }
 340 }
 341
 342 stmt: OP_OUTARG_VT (OP_ICONST) {
 343         tree->opcode = OP_X86_PUSH_IMM;
 344         tree->inst_imm = state->left->tree->inst_c0;
 345         mono_bblock_add_inst (s->cbb, tree);
 346 }
 347
 348 stmt: OP_OUTARG_VT (reg) {
 349         tree->opcode = OP_X86_PUSH;
 350         tree->sreg1 = state->left->tree->dreg;
 351         mono_bblock_add_inst (s->cbb, tree);
 352 }
 353
 354 stmt: OP_AMD64_OUTARG_ALIGN_STACK {
 355         MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
 356 }
 357
 358 base: OP_INARG_VT (base) {
 359         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->tree->inst_basereg,
 360                                         state->left->tree->inst_offset);
 361 }
 362
 363 reg: OP_LDADDR (OP_INARG_VT (base)) {
 364         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->left->tree->inst_basereg,
 365                                         state->left->left->tree->inst_offset);
 366 }
 367
 368 reg: CEE_LDOBJ (OP_INARG_VT (base)) {
 369         MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->left->tree->inst_basereg,
 370                                         state->left->left->tree->inst_offset);
 371 }
 372
 373 reg: OP_LDADDR (OP_REGOFFSET) "1" {
 374         if (state->left->tree->inst_offset) {
 375                 tree->opcode = OP_X86_LEA_MEMBASE;
 376                 tree->sreg1 = state->left->tree->inst_basereg;
 377                 tree->inst_imm = state->left->tree->inst_offset;
 378                 tree->dreg = state->reg1;
 379         } else {
 380                 tree->opcode = OP_MOVE;
 381                 tree->sreg1 = state->left->tree->inst_basereg;
 382                 tree->dreg = state->reg1;
 383         }
 384         mono_bblock_add_inst (s->cbb, tree);
 385 }
 386
 387 reg: CEE_LDOBJ (OP_REGOFFSET) "1" {
 388         if (state->left->tree->inst_offset) {
 389                 tree->opcode = OP_X86_LEA_MEMBASE;
 390                 tree->sreg1 = state->left->tree->inst_basereg;
 391                 tree->inst_imm = state->left->tree->inst_offset;
 392                 tree->dreg = state->reg1;
 393         } else {
 394                 tree->opcode = OP_MOVE;
 395                 tree->sreg1 = state->left->tree->inst_basereg;
 396                 tree->dreg = state->reg1;
 397         }
 398         mono_bblock_add_inst (s->cbb, tree);
 399 }
 400
 401 reg: CEE_LDELEMA (reg, reg) "15" {
 402         guint32 size = mono_class_array_element_size (tree->klass);
 403
 404         MONO_EMIT_BOUNDS_CHECK (s, state->left->reg1, MonoArray, max_length, state->right->reg1);
 405
 406         if (size == 1 || size == 2 || size == 4 || size == 8) {
 407                 static const int fast_log2 [] = { 1, 0, 1, -1, 2, -1, -1, -1, 3 };
 408                 int reg;
 409
 410                 /* The array reg is 64 bits but the index reg is only 32 */
 411                 tree->dreg = mono_regstate_next_float (s->rs);
 412                 reg = mono_regstate_next_int (s->rs);
 413                 MONO_EMIT_NEW_UNALU (s, OP_SEXT_I4, reg, state->right->reg1);
 414
 415                 tree->opcode = OP_X86_LEA;
 416                 tree->dreg = state->reg1;
 417                 tree->sreg1 = state->left->reg1;
 418                 tree->sreg2 = reg;
 419                 tree->inst_imm = G_STRUCT_OFFSET (MonoArray, vector);
 420                 tree->backend.shift_amount = fast_log2 [size];
 421                 mono_bblock_add_inst (s->cbb, tree);
 422         } else {
 423                 int mult_reg = mono_regstate_next_int (s->rs);
 424                 int add_reg = mono_regstate_next_int (s->rs);
 425                 MONO_EMIT_NEW_BIALU_IMM (s, OP_MUL_IMM, mult_reg, state->right->reg1, size);
 426                 MONO_EMIT_NEW_BIALU (s, CEE_ADD, add_reg, mult_reg, state->left->reg1);
 427                 MONO_EMIT_NEW_BIALU_IMM (s, OP_ADD_IMM, state->reg1, add_reg, G_STRUCT_OFFSET (MonoArray, vector));
 428         }
 429 }
 430
 431 stmt: CEE_STIND_R8 (OP_REGVAR, freg) {
 432         /* nothing to do: the value is already on the FP stack */
 433 }
 434
 435 stmt: CEE_STIND_I4 (base, CEE_ADD (CEE_LDIND_I4 (base), OP_ICONST)) {
 436         int con = state->right->right->tree->inst_c0;
 437
 438         if (con == 1) {
 439                 tree->opcode = OP_X86_INC_MEMBASE;
 440         } else {
 441                 tree->opcode = OP_X86_ADD_MEMBASE_IMM;
 442                 tree->inst_imm = con;
 443         }
 444
 445         tree->inst_basereg = state->left->tree->inst_basereg;
 446         tree->inst_offset = state->left->tree->inst_offset;
 447         mono_bblock_add_inst (s->cbb, tree);
 448 } cost {
 449         MBTREE_TYPE *t1 = state->right->left->left->tree;
 450         MBTREE_TYPE *t2 = state->left->tree;
 451         MBCOND (t1->inst_basereg == t2->inst_basereg &&
 452                 t1->inst_offset == t2->inst_offset);
 453         return 2;
 454 }
 455
 456 stmt: CEE_STIND_I4 (base, CEE_SUB (CEE_LDIND_I4 (base), OP_ICONST)) {
 457         int con = state->right->right->tree->inst_c0;
 458
 459         if (con == 1) {
 460                 tree->opcode = OP_X86_DEC_MEMBASE;
 461         } else {
 462                 tree->opcode = OP_X86_SUB_MEMBASE_IMM;
 463                 tree->inst_imm = con;
 464         }
 465
 466         tree->inst_basereg = state->left->tree->inst_basereg;
 467         tree->inst_offset = state->left->tree->inst_offset;
 468         mono_bblock_add_inst (s->cbb, tree);
 469 } cost {
 470         MBTREE_TYPE *t1 = state->right->left->left->tree;
 471         MBTREE_TYPE *t2 = state->left->tree;
 472         MBCOND (t1->inst_basereg == t2->inst_basereg &&
 473                 t1->inst_offset == t2->inst_offset);
 474         return 2;
 475 }
 476
 477 stmt: CEE_STIND_I4 (OP_REGVAR, CEE_SUB (CEE_LDIND_I4 (OP_REGVAR), OP_ICONST)) {
 478         int con = state->right->right->tree->inst_c0;
 479         int dreg = state->left->tree->dreg;
 480         int sreg = state->right->left->left->tree->dreg;
 481
 482         if (con == 1) {
 483                 if (dreg != sreg)
 484                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 485                 tree->opcode = OP_X86_DEC_REG;
 486                 tree->dreg = tree->sreg1 = dreg;
 487         } else if (con == -1) {
 488                 if (dreg != sreg)
 489                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 490                 tree->opcode = OP_X86_INC_REG;
 491                 tree->dreg = tree->sreg1 = dreg;
 492         } else {
 493                 tree->opcode = OP_SUB_IMM;
 494                 tree->inst_imm = con;
 495                 tree->sreg1 = sreg;
 496                 tree->dreg = dreg;
 497         }
 498         mono_bblock_add_inst (s->cbb, tree);
 499 }
 500
 501 stmt: CEE_STIND_I (OP_REGVAR, CEE_ADD (CEE_LDIND_I (OP_REGVAR), OP_ICONST)),
 502 stmt: CEE_STIND_I4 (OP_REGVAR, CEE_ADD (CEE_LDIND_I4 (OP_REGVAR), OP_ICONST)) {
 503         int con = state->right->right->tree->inst_c0;
 504         int dreg = state->left->tree->dreg;
 505         int sreg = state->right->left->left->tree->dreg;
 506
 507         if (con == 1) {
 508                 if (dreg != sreg)
 509                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 510                 tree->opcode = OP_X86_INC_REG;
 511                 tree->dreg = tree->sreg1 = dreg;
 512         } else if (con == -1) {
 513                 if (dreg != sreg)
 514                         MONO_EMIT_NEW_UNALU (s, OP_MOVE, dreg, sreg);
 515                 tree->opcode = OP_X86_DEC_REG;
 516                 tree->dreg = tree->sreg1 = dreg;
 517         } else {
 518                 tree->opcode = OP_ADD_IMM;
 519                 tree->inst_imm = con;
 520                 tree->sreg1 = sreg;
 521                 tree->dreg = dreg;
 522         }
 523         mono_bblock_add_inst (s->cbb, tree);
 524 }
 525
 526 reg: CEE_LDIND_I2 (OP_REGVAR) {
 527         MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);
 528 }
 529
 530 # The XOR rule
 531 stmt: CEE_STIND_I8 (OP_REGVAR, OP_ICONST),
 532 stmt: CEE_STIND_I4 (OP_REGVAR, OP_ICONST),
 533 stmt: CEE_STIND_I2 (OP_REGVAR, OP_ICONST),
 534 stmt: CEE_STIND_I1 (OP_REGVAR, OP_ICONST),
 535 stmt: CEE_STIND_REF (OP_REGVAR, OP_ICONST),
 536 stmt: CEE_STIND_I (OP_REGVAR, OP_ICONST),
 537 stmt: CEE_STIND_I8 (OP_REGVAR, OP_I8CONST),
 538 stmt: CEE_STIND_I4 (OP_REGVAR, OP_I8CONST),
 539 stmt: CEE_STIND_I2 (OP_REGVAR, OP_I8CONST),
 540 stmt: CEE_STIND_I1 (OP_REGVAR, OP_I8CONST),
 541 stmt: CEE_STIND_REF (OP_REGVAR, OP_I8CONST),
 542 stmt: CEE_STIND_I (OP_REGVAR, OP_I8CONST) {
 543         int r = state->left->tree->dreg;
 544         MONO_EMIT_BIALU (s, tree, CEE_XOR, r, r, r);
 545 } cost {
 546         MBCOND (!state->right->tree->inst_c0);
 547
 548         return 0;
 549 }
 550
 551 # on x86, fp compare overwrites EAX, so we must
 552 # either improve the local register allocator or
 553 # emit coarse opcodes which saves EAX for us.
 554
 555 reg: OP_CEQ (OP_COMPARE (freg, freg)),
 556 reg: OP_CLT (OP_COMPARE (freg, freg)),
 557 reg: OP_CGT (OP_COMPARE (freg, freg)),
 558 reg: OP_CLT_UN (OP_COMPARE (freg, freg)),
 559 reg: OP_CGT_UN (OP_COMPARE (freg, freg)) {
 560         MONO_EMIT_BIALU (s, tree, ceq_to_fceq (tree->opcode), state->reg1, state->left->left->reg1,
 561                          state->left->right->reg1);
 562 }
 563
 564 # fpcflags overwrites EAX, but this does not matter for statements
 565 # because we are the last operation in the tree.
 566
 567 stmt: CEE_BNE_UN (fpcflags),
 568 stmt: CEE_BEQ (fpcflags),
 569 stmt: CEE_BLT (fpcflags),
 570 stmt: CEE_BLT_UN (fpcflags),
 571 stmt: CEE_BGT (fpcflags),
 572 stmt: CEE_BGT_UN (fpcflags),
 573 stmt: CEE_BGE  (fpcflags),
 574 stmt: CEE_BGE_UN (fpcflags),
 575 stmt: CEE_BLE  (fpcflags),
 576 stmt: CEE_BLE_UN (fpcflags) {
 577         tree->opcode = cbranch_to_fcbranch (tree->opcode);
 578         mono_bblock_add_inst (s->cbb, tree);
 579 }
 580
 581 stmt: CEE_POP (freg) "0" {
 582         /* we need to pop the value from the x86 FP stack */
 583         MONO_EMIT_UNALU (s, tree, OP_X86_FPOP, -1, state->left->reg1);
 584 }
 585
 586 # override the rules in inssel-float.brg that work for machines with FP registers
 587
 588 freg: OP_FCONV_TO_R8 (freg) "0" {
 589         tree->opcode = OP_FMOVE;
 590         tree->sreg1 = state->left->reg1;
 591         tree->dreg = state->reg1;
 592         mono_bblock_add_inst (s->cbb, tree);
 593 }
 594
 595 freg: OP_FCONV_TO_R4 (freg) "0" {
 596         tree->opcode = OP_FMOVE;
 597         tree->sreg1 = state->left->reg1;
 598         tree->dreg = state->reg1;
 599         mono_bblock_add_inst (s->cbb, tree);
 600 }
 601
 602 reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
 603         MonoInst *base = state->right->left->tree;
 604
 605         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 606 }
 607
 608 reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
 609         MonoInst *base = state->right->left->tree;
 610
 611         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 612 }
 613
 614 reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
 615         MonoInst *base = state->right->left->tree;
 616
 617         MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
 618 }
 619
 620 reg: OP_LSHL (reg, reg),
 621 reg: OP_LSHR (reg, reg),
 622 reg: OP_LSHR_UN (reg, reg),
 623 reg: OP_LMUL (reg, reg),
 624 reg: OP_LDIV (reg, reg),
 625 reg: OP_LDIV_UN (reg, reg),
 626 reg: OP_LREM (reg, reg),
 627 reg: OP_LREM_UN (reg, reg),
 628 reg: OP_LMUL_OVF (reg, reg),
 629 reg: OP_LMUL_OVF_UN (reg, reg),
 630 reg: OP_IMIN (reg, reg),
 631 reg: OP_IMAX (reg, reg),
 632 reg: OP_LMIN (reg, reg),
 633 reg: OP_LMAX (reg, reg) "0" {
 634         MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
 635 }
 636
 637 reg: OP_LMUL (reg, OP_I8CONST),
 638 reg: OP_LSHL (reg, OP_ICONST),
 639 reg: OP_LSHR (reg, OP_ICONST),
 640 reg: OP_LSHR_UN (reg, OP_ICONST) {
 641         MONO_EMIT_BIALU_IMM (s, tree, bialu_to_bialu_imm (tree->opcode), state->reg1, state->left->reg1, state->right->tree->inst_c0);
 642 } cost {
 643         MBCOND (mono_arch_is_inst_imm (state->right->tree->inst_c0));
 644         return 0;
 645 }
 646
 647 reg: OP_ATOMIC_ADD_NEW_I4 (base, reg),
 648 reg: OP_ATOMIC_ADD_NEW_I8 (base, reg),
 649 reg: OP_ATOMIC_ADD_I4 (base, reg),
 650 reg: OP_ATOMIC_ADD_I8 (base, reg),
 651 reg: OP_ATOMIC_EXCHANGE_I4 (base, reg),
 652 reg: OP_ATOMIC_EXCHANGE_I8 (base, reg) {
 653         tree->opcode = tree->opcode;
 654         tree->dreg = state->reg1;
 655         tree->sreg2 = state->right->reg1;
 656         tree->inst_basereg = state->left->tree->inst_basereg;
 657         tree->inst_offset = state->left->tree->inst_offset;
 658
 659         mono_bblock_add_inst (s->cbb, tree);
 660 }
 661
 662 # Optimized call instructions
 663 # mono_arch_patch_delegate_trampoline depends on these
 664 reg: OP_CALL_REG (CEE_LDIND_I (base)),
 665 freg: OP_FCALL_REG (CEE_LDIND_I (base)),
 666 reg: OP_LCALL_REG (CEE_LDIND_I (base)) {
 667         tree->opcode = call_reg_to_call_membase (tree->opcode);
 668         tree->inst_basereg = state->left->left->tree->inst_basereg;
 669         tree->inst_offset = state->left->left->tree->inst_offset;
 670         tree->dreg = state->reg1;
 671         mono_bblock_add_inst (s->cbb, tree);
 672 }
 673
 674 stmt: OP_VOIDCALL_REG (CEE_LDIND_I (base)) {
 675         tree->opcode = call_reg_to_call_membase (tree->opcode);
 676         tree->inst_basereg = state->left->left->tree->inst_basereg;
 677         tree->inst_offset = state->left->left->tree->inst_offset;
 678         mono_bblock_add_inst (s->cbb, tree);
 679 }
 680
 681 stmt: OP_VCALL_REG (CEE_LDIND_I (base), reg) {
 682         mono_arch_emit_this_vret_args (s, (MonoCallInst*)tree, -1, -1, state->right->reg1);
 683
 684         tree->opcode = call_reg_to_call_membase (tree->opcode);
 685         tree->inst_basereg = state->left->left->tree->inst_basereg;
 686         tree->inst_offset = state->left->left->tree->inst_offset;
 687         tree->dreg = state->reg1;
 688         mono_bblock_add_inst (s->cbb, tree);
 689 }
 690
 691 %%
 692
 693 static int
 694 bialu_to_bialu_imm (int opcode)
 695 {
 696         switch (opcode) {
 697         case OP_LMUL:
 698                 return OP_LMUL_IMM;
 699         case OP_LSHL:
 700                 return OP_LSHL_IMM;
 701         case OP_LSHR:
 702                 return OP_LSHR_IMM;
 703         case OP_LSHR_UN:
 704                 return OP_LSHR_UN_IMM;
 705         default:
 706                 g_assert_not_reached ();
 707         }
 708
 709         return -1;
 710 }
 711
 712 static int
 713 cbranch_to_fcbranch (int opcode)
 714 {
 715         switch (opcode) {
 716         case CEE_BNE_UN:
 717                 return OP_FBNE_UN;
 718         case CEE_BEQ:
 719                 return OP_FBEQ;
 720         case CEE_BLT:
 721                 return OP_FBLT;
 722         case CEE_BLT_UN:
 723                 return OP_FBLT_UN;
 724         case CEE_BGT:
 725                 return OP_FBGT;
 726         case CEE_BGT_UN:
 727                 return OP_FBGT_UN;
 728         case CEE_BGE:
 729                 return OP_FBGE;
 730         case CEE_BGE_UN:
 731                 return OP_FBGE_UN;
 732         case CEE_BLE:
 733                 return OP_FBLE;
 734         case CEE_BLE_UN:
 735                 return OP_FBLE_UN;
 736         default:
 737                 g_assert_not_reached ();
 738         }
 739
 740         return -1;
 741 }
 742
 743 static int
 744 ceq_to_fceq (int opcode)
 745 {
 746         switch (opcode) {
 747         case OP_CEQ:
 748                 return OP_FCEQ;
 749         case OP_CLT:
 750                 return OP_FCLT;
 751         case OP_CGT:
 752                 return OP_FCGT;
 753         case OP_CLT_UN:
 754                 return OP_FCLT_UN;
 755         case OP_CGT_UN:
 756                 return OP_FCGT_UN;
 757         default:
 758                 g_assert_not_reached ();
 759         }
 760
 761         return -1;
 762 }
 763
 764 static int
 765 call_reg_to_call_membase (int opcode)
 766 {
 767         switch (opcode) {
 768         case OP_CALL_REG:
 769                 return OP_CALL_MEMBASE;
 770         case OP_FCALL_REG:
 771                 return OP_FCALL_MEMBASE;
 772         case OP_VCALL_REG:
 773                 return OP_VCALL_MEMBASE;
 774         case OP_LCALL_REG:
 775                 return OP_LCALL_MEMBASE;
 776         case OP_VOIDCALL_REG:
 777                 return OP_VOIDCALL_MEMBASE;
 778         default:
 779                 g_assert_not_reached ();
 780         }
 781
 782         return -1;
 783 }