1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
21 # l long reg (forced eax:edx)
22 # L long reg (dynamic)
23 # y the reg needs to be one of EAX,EBX,ECX,EDX (sete opcodes)
25 # len:number describe the maximun length in bytes of the instruction
26 # number is a positive integer. If the length is not specified
27 # it defaults to zero. But lengths are only checked if the given opcode
28 # is encountered during compilation. Some opcodes, like CONV_U4 are
29 # transformed into other opcodes in the brg files, so they do not show up
30 # during code generation.
32 # cost:number describe how many cycles are needed to complete the instruction (unused)
34 # clob:spec describe if the instruction clobbers registers or has special needs
36 # spec can be one of the following characters:
37 # c clobbers caller-save registers
38 # 1 clobbers the first source register
41 # x both the source operands are clobbered (xchg)
43 # flags:spec describe if the instruction uses or sets the flags (unused)
45 # spec can be one of the following chars:
48 # m uses and modifies the flags
50 # res:spec describe what units are used in the processor (unused)
52 # delay: describe delay slots (unused)
54 # the required specifiers are: len, clob (if registers are clobbered), the registers
55 # specifiers if the registers are actually used, flags (when scheduling is implemented).
57 # See the code in mini-x86.c for more details on how the specifiers are used.
61 call: dest:a clob:c len:17
75 add: dest:i src1:i src2:i len:2 clob:1
76 sub: dest:i src1:i src2:i len:2 clob:1
77 mul: dest:i src1:i src2:i len:3 clob:1
78 div: dest:a src1:a src2:i len:15 clob:d
79 div.un: dest:a src1:a src2:i len:15 clob:d
80 rem: dest:d src1:a src2:i len:15 clob:a
81 rem.un: dest:d src1:a src2:i len:15 clob:a
82 and: dest:i src1:i src2:i len:2 clob:1
83 or: dest:i src1:i src2:i len:2 clob:1
84 xor: dest:i src1:i src2:i len:2 clob:1
85 shl: dest:i src1:i src2:s clob:1 len:2
86 shr: dest:i src1:i src2:s clob:1 len:2
87 shr.un: dest:i src1:i src2:s clob:1 len:2
88 neg: dest:i src1:i len:2 clob:1
89 not: dest:i src1:i len:2 clob:1
90 conv.i1: dest:i src1:y len:3
91 conv.i2: dest:i src1:i len:3
92 conv.i4: dest:i src1:i len:2
93 conv.r4: dest:f src1:i len:7
94 conv.r8: dest:f src1:i len:7
95 conv.u4: dest:i src1:i
96 conv.u2: dest:i src1:i len:3
97 conv.u1: dest:i src1:y len:3
98 conv.i: dest:i src1:i len:3
100 int_xor: dest:i src1:i src2:i len:2 clob:1
103 rethrow: src1:i len:13
104 start_handler: len:16
106 endfilter: src1:a len:16
108 ckfinite: dest:f src1:f len:32
109 mul.ovf: dest:i src1:i src2:i clob:1 len:9
110 # this opcode is handled specially in the code generator
111 mul.ovf.un: dest:i src1:i src2:i len:16
112 conv.u: dest:i src1:i len:3
119 localloc: dest:i src1:i len:120
120 compare: src1:i src2:i len:2
121 compare_imm: src1:i len:6
122 fcompare: src1:f src2:f clob:a len:9
123 oparglist: src1:b len:10
126 setret: dest:a src1:i len:2
127 setlret: dest:l src1:i src2:i len:4
128 checkthis: src1:b len:2
129 voidcall: len:17 clob:c
130 voidcall_reg: src1:i len:11 clob:c
131 voidcall_membase: src1:b len:16 clob:c
132 fcall: dest:f len:17 clob:c
133 fcall_reg: dest:f src1:i len:11 clob:c
134 fcall_membase: dest:f src1:b len:16 clob:c
135 lcall: dest:l len:17 clob:c
136 lcall_reg: dest:l src1:i len:11 clob:c
137 lcall_membase: dest:l src1:b len:16 clob:c
139 vcall_reg: src1:i len:11 clob:c
140 vcall_membase: src1:b len:16 clob:c
141 call_reg: dest:a src1:i len:11 clob:c
142 call_membase: dest:a src1:b len:16 clob:c
144 r4const: dest:f len:15
145 r8const: dest:f len:16
146 store_membase_imm: dest:b len:10
147 store_membase_reg: dest:b src1:i len:7
148 storei1_membase_imm: dest:b len:10
149 storei1_membase_reg: dest:b src1:y len:7
150 storei2_membase_imm: dest:b len:11
151 storei2_membase_reg: dest:b src1:i len:7
152 storei4_membase_imm: dest:b len:10
153 storei4_membase_reg: dest:b src1:i len:7
154 storei8_membase_imm: dest:b
155 storei8_membase_reg: dest:b src1:i
156 storer4_membase_reg: dest:b src1:f len:7
157 storer8_membase_reg: dest:b src1:f len:7
158 load_membase: dest:i src1:b len:7
159 loadi1_membase: dest:y src1:b len:7
160 loadu1_membase: dest:y src1:b len:7
161 loadi2_membase: dest:i src1:b len:7
162 loadu2_membase: dest:i src1:b len:7
163 loadi4_membase: dest:i src1:b len:7
164 loadu4_membase: dest:i src1:b len:7
165 loadi8_membase: dest:i src1:b
166 loadr4_membase: dest:f src1:b len:7
167 loadr8_membase: dest:f src1:b len:7
168 loadr8_spill_membase: src1:b len:9
169 loadu4_mem: dest:i len:9
170 move: dest:i src1:i len:2
171 addcc_imm: dest:i src1:i len:6 clob:1
172 add_imm: dest:i src1:i len:6 clob:1
173 subcc_imm: dest:i src1:i len:6 clob:1
174 sub_imm: dest:i src1:i len:6 clob:1
175 mul_imm: dest:i src1:i len:9
176 # there is no actual support for division or reminder by immediate
177 # we simulate them, though (but we need to change the burg rules
178 # to allocate a symbolic reg for src2)
179 div_imm: dest:a src1:a src2:i len:15 clob:d
180 div_un_imm: dest:a src1:a src2:i len:15 clob:d
181 rem_imm: dest:d src1:a src2:i len:15 clob:a
182 rem_un_imm: dest:d src1:a src2:i len:15 clob:a
183 and_imm: dest:i src1:i len:6 clob:1
184 or_imm: dest:i src1:i len:6 clob:1
185 xor_imm: dest:i src1:i len:6 clob:1
186 shl_imm: dest:i src1:i len:6 clob:1
187 shr_imm: dest:i src1:i len:6 clob:1
188 shr_un_imm: dest:i src1:i len:6 clob:1
190 cond_exc_ne_un: len:6
192 cond_exc_lt_un: len:6
194 cond_exc_gt_un: len:6
196 cond_exc_ge_un: len:6
198 cond_exc_le_un: len:6
203 long_shl: dest:L src1:L src2:s clob:1 len:21
204 long_shr: dest:L src1:L src2:s clob:1 len:22
205 long_shr_un: dest:L src1:L src2:s clob:1 len:22
206 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
208 long_conv_to_r_un: dest:f src1:i src2:i len:37
209 long_shr_imm: dest:L src1:L clob:1 len:10
210 long_shr_un_imm: dest:L src1:L clob:1 len:10
211 long_shl_imm: dest:L src1:L clob:1 len:10
222 float_add: dest:f src1:f src2:f len:2
223 float_sub: dest:f src1:f src2:f len:2
224 float_mul: dest:f src1:f src2:f len:2
225 float_div: dest:f src1:f src2:f len:2
226 float_div_un: dest:f src1:f src2:f len:2
227 float_rem: dest:f src1:f src2:f len:17
228 float_rem_un: dest:f src1:f src2:f len:17
229 float_neg: dest:f src1:f len:2
230 float_not: dest:f src1:f len:2
231 float_conv_to_i1: dest:y src1:f len:39
232 float_conv_to_i2: dest:y src1:f len:39
233 float_conv_to_i4: dest:i src1:f len:39
234 float_conv_to_i8: dest:L src1:f len:39
235 float_conv_to_u4: dest:i src1:f len:39
236 float_conv_to_u8: dest:L src1:f len:39
237 float_conv_to_u2: dest:y src1:f len:39
238 float_conv_to_u1: dest:y src1:f len:39
239 float_conv_to_i: dest:i src1:f len:39
240 float_conv_to_ovf_i: dest:a src1:f len:30
241 float_conv_to_ovd_u: dest:a src1:f len:30
243 float_ceq: dest:y src1:f src2:f len:25
244 float_cgt: dest:y src1:f src2:f len:25
245 float_cgt_un: dest:y src1:f src2:f len:37
246 float_clt: dest:y src1:f src2:f len:25
247 float_clt_un: dest:y src1:f src2:f len:32
248 float_conv_to_u: dest:i src1:f len:36
250 aot_const: dest:i len:5
251 load_gotaddr: dest:i len:64
252 got_entry: dest:i src1:b len:7
253 x86_test_null: src1:i len:2
254 x86_compare_membase_reg: src1:b src2:i len:7
255 x86_compare_membase_imm: src1:b len:11
256 x86_compare_membase8_imm: src1:b len:8
257 x86_compare_mem_imm: len:11
258 x86_compare_reg_membase: src1:i src2:b len:7
259 x86_inc_reg: dest:i src1:i clob:1 len:1
260 x86_inc_membase: src1:b len:7
261 x86_dec_reg: dest:i src1:i clob:1 len:1
262 x86_dec_membase: src1:b len:7
263 x86_add_membase_imm: src1:b len:11
264 x86_sub_membase_imm: src1:b len:11
265 x86_and_membase_imm: src1:b len:11
266 x86_or_membase_imm: src1:b len:11
267 x86_xor_membase_imm: src1:b len:11
268 x86_push: src1:i len:1
270 x86_push_membase: src1:b len:7
271 x86_push_obj: src1:b len:30
272 x86_push_got_entry: src1:b len:7
273 x86_lea: dest:i src1:i src2:i len:7
274 x86_lea_membase: dest:i src1:i len:10
275 x86_xchg: src1:i src2:i clob:x len:1
276 x86_fpop: src1:f len:2
277 x86_fp_load_i8: dest:f src1:b len:7
278 x86_fp_load_i4: dest:f src1:b len:7
279 x86_seteq_membase: src1:b len:7
280 x86_setne_membase: src1:b len:7
281 x86_add_membase: dest:i src1:i src2:b clob:1 len:11
282 x86_sub_membase: dest:i src1:i src2:b clob:1 len:11
283 x86_mul_membase: dest:i src1:i src2:b clob:1 len:13
284 adc: dest:i src1:i src2:i len:2 clob:1
285 addcc: dest:i src1:i src2:i len:2 clob:1
286 subcc: dest:i src1:i src2:i len:2 clob:1
287 adc_imm: dest:i src1:i len:6 clob:1
288 sbb: dest:i src1:i src2:i len:2 clob:1
289 sbb_imm: dest:i src1:i len:6 clob:1
291 sin: dest:f src1:f len:6
292 cos: dest:f src1:f len:6
293 abs: dest:f src1:f len:2
294 tan: dest:f src1:f len:49
295 atan: dest:f src1:f len:8
296 sqrt: dest:f src1:f len:2
297 bigmul: len:2 dest:l src1:a src2:i
298 bigmul_un: len:2 dest:l src1:a src2:i
299 sext_i1: dest:i src1:y len:3
300 sext_i2: dest:i src1:y len:3
301 tls_get: dest:i len:20
302 atomic_add_i4: src1:b src2:i dest:i len:16
303 atomic_add_new_i4: src1:b src2:i dest:i len:16
304 atomic_exchange_i4: src1:b src2:i dest:i len:24
305 memory_barrier: len:16