1 # sparc32 cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the register allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
18 # L register pair (same as 'i' on v9)
19 # l %o0:%o1 register pair (same as 'i' on v9)
22 # len:number describe the maximun length in bytes of the instruction
23 # number is a positive integer
25 # cost:number describe how many cycles are needed to complete the instruction (unused)
27 # clob:spec describe if the instruction clobbers registers or has special needs
29 # spec can be one of the following characters:
30 # c clobbers caller-save registers
31 # r 'reserves' the destination register until a later instruction unreserves it
32 # used mostly to set output registers in function calls
34 # flags:spec describe if the instruction uses or sets the flags (unused)
36 # spec can be one of the following chars:
39 # m uses and modifies the flags
41 # res:spec describe what units are used in the processor (unused)
43 # delay: describe delay slots (unused)
45 # the required specifiers are: len, clob (if registers are clobbered), the registers
46 # specifiers if the registers are actually used, flags (when scheduling is implemented).
48 # See the code in mini-sparc32.c for more details on how the specifiers are used.
64 sparc_brz: src1:i len: 8
65 sparc_brlez: src1:i len: 8
66 sparc_brlz: src1:i len: 8
67 sparc_brnz: src1:i len: 8
68 sparc_brgz: src1:i len: 8
69 sparc_brgez: src1:i len: 8
70 sparc_cond_exc_eqz: src1:i len:64
71 sparc_cond_exc_nez: src1:i len:64
72 sparc_cond_exc_ltz: src1:i len:64
73 sparc_cond_exc_gtz: src1:i len:64
74 sparc_cond_exc_gez: src1:i len:64
75 sparc_cond_exc_lez: src1:i len:64
76 add: dest:i src1:i src2:i len:64
77 sub: dest:i src1:i src2:i len:4
78 mul: dest:i src1:i src2:i len:4
79 div: dest:i src1:i src2:i len:64
80 div.un: dest:i src1:i src2:i len:8
81 rem: dest:d src1:i src2:i len:64
82 rem.un: dest:d src1:i src2:i len:64
83 and: dest:i src1:i src2:i len:4
84 or: dest:i src1:i src2:i len:4
85 xor: dest:i src1:i src2:i len:4
86 shl: dest:i src1:i src2:i len:4
87 shr: dest:i src1:i src2:i len:4
88 shr.un: dest:i src1:i src2:i len:4
89 neg: dest:i src1:i len:4
90 not: dest:i src1:i len:4
91 conv.i1: dest:i src1:i len:8
92 conv.i2: dest:i src1:i len:8
93 conv.i4: dest:i src1:i len:4
94 conv.i8: dest:i src1:i len:4
95 conv.r4: dest:f src1:i len:64
96 conv.r8: dest:f src1:i len:64
97 conv.u4: dest:i src1:i len:4
98 conv.u8: dest:i src1:i len:4
100 rethrow: src1:i len:64
101 conv.ovf.u4: dest:i src1:i len:64
102 ckfinite: dest:f src1:f len:40
103 conv.u2: dest:i src1:i len:8
104 conv.u1: dest:i src1:i len:4
105 conv.i: dest:i src1:i len:4
106 mul.ovf: dest:i src1:i src2:i len:64
107 mul.ovf.un: dest:i src1:i src2:i len:64
108 start_handler: len:64
110 endfilter: src1:i len:64
111 conv.u: dest:i src1:i len:4
115 cgt.un: dest:i len:64
117 clt.un: dest:i len:64
118 localloc: dest:i src1:i len:64
119 sparc_localloc_imm: dest:i len:64
120 compare: src1:i src2:i len:4
121 icompare: src1:i src2:i len:4
122 compare_imm: src1:i len:64
123 icompare_imm: src1:i len:64
124 fcompare: src1:f src2:f len:64
125 lcompare: src1:i src2:i len:4
126 setfret: dest:f src1:f len:8
129 setret: dest:a src1:i len:4
130 sparc_setfreg_float: dest:f src1:f len:4 clob:r
131 checkthis: src1:b len:4
132 oparglist: src1:i len:64
133 call: dest:o clob:c len:40
134 call_reg: dest:o src1:i len:64 clob:c
135 call_membase: dest:o src1:b len:64 clob:c
136 voidcall: len:64 clob:c
137 voidcall_reg: src1:i len:64 clob:c
138 voidcall_membase: src1:b len:64 clob:c
139 fcall: dest:f len:64 clob:c
140 fcall_reg: dest:f src1:i len:64 clob:c
141 fcall_membase: dest:f src1:b len:64 clob:c
142 lcall: dest:l len:42 clob:c
143 lcall_reg: dest:l src1:i len:64 clob:c
144 lcall_membase: dest:l src1:b len:64 clob:c
146 vcall_reg: src1:i len:64 clob:c
147 vcall_membase: src1:b len:64 clob:c
148 iconst: dest:i len:64
149 i8const: dest:i len:64
150 r4const: dest:f len:64
151 r8const: dest:f len:64
152 store_membase_imm: dest:b len:64
153 store_membase_reg: dest:b src1:i len:64
154 storei1_membase_imm: dest:b len:64
155 storei1_membase_reg: dest:b src1:i len:64
156 storei2_membase_imm: dest:b len:64
157 storei2_membase_reg: dest:b src1:i len:64
158 storei4_membase_imm: dest:b len:64
159 storei4_membase_reg: dest:b src1:i len:64
160 storei8_membase_imm: dest:b len:64 len:64
161 storei8_membase_reg: dest:b src1:i len:64
162 storer4_membase_reg: dest:b src1:f len:64
163 storer8_membase_reg: dest:b src1:f len:64
164 load_membase: dest:i src1:b len:64
165 loadi1_membase: dest:i src1:b len:64
166 loadu1_membase: dest:i src1:b len:64
167 loadi2_membase: dest:i src1:b len:64
168 loadu2_membase: dest:i src1:b len:64
169 loadi4_membase: dest:i src1:b len:64
170 loadu4_membase: dest:i src1:b len:64
171 loadi8_membase: dest:i src1:b len:64
172 loadr4_membase: dest:f src1:b len:64
173 loadr8_membase: dest:f src1:b len:64
174 loadu4_mem: dest:i len:8
175 move: dest:i src1:i len:4
176 add_imm: dest:i src1:i len:64
177 addcc_imm: dest:i src1:i len:64
178 sub_imm: dest:i src1:i len:64
179 subcc_imm: dest:i src1:i len:64
180 mul_imm: dest:i src1:i len:64
181 div_imm: dest:a src1:i src2:i len:64
182 div_un_imm: dest:a src1:i src2:i len:64
183 rem_imm: dest:d src1:i src2:i len:64
184 rem_un_imm: dest:d src1:i src2:i len:64
185 and_imm: dest:i src1:i len:64
186 or_imm: dest:i src1:i len:64
187 xor_imm: dest:i src1:i len:64
188 shl_imm: dest:i src1:i len:64
189 shr_imm: dest:i src1:i len:64
190 shr_un_imm: dest:i src1:i len:64
192 cond_exc_ne_un: len:64
194 cond_exc_lt_un: len:64
196 cond_exc_gt_un: len:64
198 cond_exc_ge_un: len:64
200 cond_exc_le_un: len:64
205 long_shl: dest:i src1:i src2:i len:64
206 long_shr: dest:i src1:i src2:i len:64
207 long_shr_un: dest:i src1:i src2:i len:64
208 long_conv_to_ovf_i: dest:i src1:i src2:i len:48
210 long_conv_to_r_un: dest:f src1:i src2:i len:64
211 long_shr_imm: dest:i src1:i len:64
212 long_shr_un_imm: dest:i src1:i len:64
213 long_shl_imm: dest:i src1:i len:64
224 float_add: dest:f src1:f src2:f len:4
225 float_sub: dest:f src1:f src2:f len:4
226 float_mul: dest:f src1:f src2:f len:4
227 float_div: dest:f src1:f src2:f len:4
228 float_div_un: dest:f src1:f src2:f len:4
229 float_rem: dest:f src1:f src2:f len:64
230 float_rem_un: dest:f src1:f src2:f len:64
231 float_neg: dest:f src1:f len:4
232 float_not: dest:f src1:f len:4
233 float_conv_to_i1: dest:i src1:f len:40
234 float_conv_to_i2: dest:i src1:f len:40
235 float_conv_to_i4: dest:i src1:f len:40
236 float_conv_to_i8: dest:L src1:f len:40
237 float_conv_to_r4: dest:f src1:f len:8
238 float_conv_to_u4: dest:i src1:f len:40
239 float_conv_to_u8: dest:L src1:f len:40
240 float_conv_to_u2: dest:i src1:f len:40
241 float_conv_to_u1: dest:i src1:f len:40
242 float_conv_to_i: dest:i src1:f len:40
243 float_ceq: dest:i src1:f src2:f len:64
244 float_cgt: dest:i src1:f src2:f len:64
245 float_cgt_un: dest:i src1:f src2:f len:64
246 float_clt: dest:i src1:f src2:f len:64
247 float_clt_un: dest:i src1:f src2:f len:64
248 float_conv_to_u: dest:i src1:f len:64
250 aot_const: dest:i len:64
251 adc: dest:i src1:i src2:i len:4
252 addcc: dest:i src1:i src2:i len:4
253 subcc: dest:i src1:i src2:i len:4
254 adc_imm: dest:i src1:i len:64
255 sbb: dest:i src1:i src2:i len:4
256 sbb_imm: dest:i src1:i len:64
258 bigmul: len:2 dest:L src1:a src2:i
259 bigmul_un: len:2 dest:L src1:a src2:i
260 fmove: dest:f src1:f len:8
263 int_add: dest:i src1:i src2:i len:64
264 int_sub: dest:i src1:i src2:i len:64
265 int_mul: dest:i src1:i src2:i len:64
266 int_div: dest:i src1:i src2:i len:64
267 int_div_un: dest:i src1:i src2:i len:64
268 int_rem: dest:i src1:i src2:i len:64
269 int_rem_un: dest:i src1:i src2:i len:64
270 int_and: dest:i src1:i src2:i len:64
271 int_or: dest:i src1:i src2:i len:64
272 int_xor: dest:i src1:i src2:i len:64
273 int_shl: dest:i src1:i src2:i len:64
274 int_shr: dest:i src1:i src2:i len:64
275 int_shr_un: dest:i src1:i src2:i len:64
276 int_adc: dest:i src1:i src2:i len:64
277 int_adc_imm: dest:i src1:i len:64
278 int_sbb: dest:i src1:i src2:i len:64
279 int_sbb_imm: dest:i src1:i len:64
280 int_addcc: dest:i src1:i src2:i len:64
281 int_subcc: dest:i src1:i src2:i len:64
282 int_add_imm: dest:i src1:i len:64
283 int_sub_imm: dest:i src1:i len:64
284 int_mul_imm: dest:i src1:i len:64
285 int_div_imm: dest:i src1:i len:64
286 int_div_un_imm: dest:i src1:i len:64
287 int_rem_imm: dest:i src1:i len:64
288 int_rem_un_imm: dest:i src1:i len:64
289 int_and_imm: dest:i src1:i len:64
290 int_or_imm: dest:i src1:i len:64
291 int_xor_imm: dest:i src1:i len:64
292 int_shl_imm: dest:i src1:i len:64
293 int_shr_imm: dest:i src1:i len:64
294 int_shr_un_imm: dest:i src1:i len:64
295 int_neg: dest:i src1:i len:64
296 int_not: dest:i src1:i len:64
297 int_ceq: dest:i len:64
298 int_cgt: dest:i len:64
299 int_cgt_un: dest:i len:64
300 int_clt: dest:i len:64
301 int_clt_un: dest:i len:64
313 memory_barrier: len:4