1 # sparc32 cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the register allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
18 # L register pair (same as 'i' on v9)
19 # l %o0:%o1 register pair (same as 'i' on v9)
22 # len:number describe the maximun length in bytes of the instruction
23 # number is a positive integer
25 # cost:number describe how many cycles are needed to complete the instruction (unused)
27 # clob:spec describe if the instruction clobbers registers or has special needs
29 # spec can be one of the following characters:
30 # c clobbers caller-save registers
31 # r 'reserves' the destination register until a later instruction unreserves it
32 # used mostly to set output registers in function calls
34 # flags:spec describe if the instruction uses or sets the flags (unused)
36 # spec can be one of the following chars:
39 # m uses and modifies the flags
41 # res:spec describe what units are used in the processor (unused)
43 # delay: describe delay slots (unused)
45 # the required specifiers are: len, clob (if registers are clobbered), the registers
46 # specifiers if the registers are actually used, flags (when scheduling is implemented).
48 # See the code in mini-sparc32.c for more details on how the specifiers are used.
64 sparc_brz: src1:i len: 8
65 sparc_brlez: src1:i len: 8
66 sparc_brlz: src1:i len: 8
67 sparc_brnz: src1:i len: 8
68 sparc_brgz: src1:i len: 8
69 sparc_brgez: src1:i len: 8
70 sparc_cond_exc_eqz: src1:i len:64
71 sparc_cond_exc_nez: src1:i len:64
72 sparc_cond_exc_ltz: src1:i len:64
73 sparc_cond_exc_gtz: src1:i len:64
74 sparc_cond_exc_gez: src1:i len:64
75 sparc_cond_exc_lez: src1:i len:64
76 ldind.i1: dest:i len:4
77 ldind.u1: dest:i len:4
78 ldind.i2: dest:i len:4
79 ldind.u2: dest:i len:4
80 ldind.i4: dest:i len:4
81 ldind.u4: dest:i len:4
83 ldind.ref: dest:i len:4
84 stind.ref: src1:b src2:i
85 stind.i1: src1:b src2:i
86 stind.i2: src1:b src2:i
87 stind.i4: src1:b src2:i
88 stind.r4: src1:b src2:f
89 stind.r8: src1:b src2:f
90 add: dest:i src1:i src2:i len:64
91 sub: dest:i src1:i src2:i len:4
92 mul: dest:i src1:i src2:i len:4
93 div: dest:i src1:i src2:i len:64
94 div.un: dest:i src1:i src2:i len:8
95 rem: dest:d src1:i src2:i len:64
96 rem.un: dest:d src1:i src2:i len:64
97 and: dest:i src1:i src2:i len:4
98 or: dest:i src1:i src2:i len:4
99 xor: dest:i src1:i src2:i len:4
100 shl: dest:i src1:i src2:i len:4
101 shr: dest:i src1:i src2:i len:4
102 shr.un: dest:i src1:i src2:i len:4
103 neg: dest:i src1:i len:4
104 not: dest:i src1:i len:4
105 conv.i1: dest:i src1:i len:8
106 conv.i2: dest:i src1:i len:8
107 conv.i4: dest:i src1:i len:4
108 conv.i8: dest:i src1:i len:4
109 conv.r4: dest:f src1:i len:64
110 conv.r8: dest:f src1:i len:64
111 conv.u4: dest:i src1:i len:4
112 conv.u8: dest:i src1:i len:4
114 op_rethrow: src1:i len:64
115 conv.ovf.u4: dest:i src1:i len:64
116 ckfinite: dest:f src1:f len:40
117 conv.u2: dest:i src1:i len:8
118 conv.u1: dest:i src1:i len:4
119 conv.i: dest:i src1:i len:4
120 mul.ovf: dest:i src1:i src2:i len:64
121 mul.ovf.un: dest:i src1:i src2:i len:64
122 start_handler: len:64
125 conv.u: dest:i src1:i len:4
129 cgt.un: dest:i len:64
131 clt.un: dest:i len:64
132 localloc: dest:i src1:i len:64
133 sparc_localloc_imm: dest:i len:64
134 compare: src1:i src2:i len:4
135 icompare: src1:i src2:i len:4
136 compare_imm: src1:i len:64
137 icompare_imm: src1:i len:64
138 fcompare: src1:f src2:f len:64
139 lcompare: src1:i src2:i len:4
140 setfret: dest:f src1:f len:8
143 setret: dest:a src1:i len:4
144 setreg: dest:i src1:i len:4 clob:r
145 setregimm: dest:i len:64 clob:r
146 setfreg: dest:f src1:f len:4 clob:r
147 sparc_setfreg_float: dest:f src1:f len:4 clob:r
148 checkthis: src1:b len:4
149 oparglist: src1:i len:64
150 call: dest:o clob:c len:40
151 call_reg: dest:o src1:i len:64 clob:c
152 call_membase: dest:o src1:b len:64 clob:c
153 voidcall: len:64 clob:c
154 voidcall_reg: src1:i len:64 clob:c
155 voidcall_membase: src1:b len:64 clob:c
156 fcall: dest:f len:64 clob:c
157 fcall_reg: dest:f src1:i len:64 clob:c
158 fcall_membase: dest:f src1:b len:64 clob:c
159 lcall: dest:l len:42 clob:c
160 lcall_reg: dest:l src1:i len:64 clob:c
161 lcall_membase: dest:l src1:b len:64 clob:c
163 vcall_reg: src1:i len:64 clob:c
164 vcall_membase: src1:b len:64 clob:c
165 iconst: dest:i len:64
166 i8const: dest:i len:64
167 r4const: dest:f len:64
168 r8const: dest:f len:64
169 store_membase_imm: dest:b len:64
170 store_membase_reg: dest:b src1:i len:64
171 storei1_membase_imm: dest:b len:64
172 storei1_membase_reg: dest:b src1:i len:64
173 storei2_membase_imm: dest:b len:64
174 storei2_membase_reg: dest:b src1:i len:64
175 storei4_membase_imm: dest:b len:64
176 storei4_membase_reg: dest:b src1:i len:64
177 storei8_membase_imm: dest:b len:64 len:64
178 storei8_membase_reg: dest:b src1:i len:64
179 storer4_membase_reg: dest:b src1:f len:64
180 storer8_membase_reg: dest:b src1:f len:64
181 load_membase: dest:i src1:b len:64
182 loadi1_membase: dest:i src1:b len:64
183 loadu1_membase: dest:i src1:b len:64
184 loadi2_membase: dest:i src1:b len:64
185 loadu2_membase: dest:i src1:b len:64
186 loadi4_membase: dest:i src1:b len:64
187 loadu4_membase: dest:i src1:b len:64
188 loadi8_membase: dest:i src1:b len:64
189 loadr4_membase: dest:f src1:b len:64
190 loadr8_membase: dest:f src1:b len:64
191 loadu4_mem: dest:i len:8
192 move: dest:i src1:i len:4
193 add_imm: dest:i src1:i len:64
194 addcc_imm: dest:i src1:i len:64
195 sub_imm: dest:i src1:i len:64
196 subcc_imm: dest:i src1:i len:64
197 mul_imm: dest:i src1:i len:64
198 div_imm: dest:a src1:i src2:i len:64
199 div_un_imm: dest:a src1:i src2:i len:64
200 rem_imm: dest:d src1:i src2:i len:64
201 rem_un_imm: dest:d src1:i src2:i len:64
202 and_imm: dest:i src1:i len:64
203 or_imm: dest:i src1:i len:64
204 xor_imm: dest:i src1:i len:64
205 shl_imm: dest:i src1:i len:64
206 shr_imm: dest:i src1:i len:64
207 shr_un_imm: dest:i src1:i len:64
209 cond_exc_ne_un: len:64
211 cond_exc_lt_un: len:64
213 cond_exc_gt_un: len:64
215 cond_exc_ge_un: len:64
217 cond_exc_le_un: len:64
222 long_shl: dest:i src1:i src2:i len:64
223 long_shr: dest:i src1:i src2:i len:64
224 long_shr_un: dest:i src1:i src2:i len:64
225 long_conv_to_ovf_i: dest:i src1:i src2:i len:48
227 long_conv_to_r_un: dest:f src1:i src2:i len:64
228 long_shr_imm: dest:i src1:i len:64
229 long_shr_un_imm: dest:i src1:i len:64
230 long_shl_imm: dest:i src1:i len:64
241 float_add: dest:f src1:f src2:f len:4
242 float_sub: dest:f src1:f src2:f len:4
243 float_mul: dest:f src1:f src2:f len:4
244 float_div: dest:f src1:f src2:f len:4
245 float_div_un: dest:f src1:f src2:f len:4
246 float_rem: dest:f src1:f src2:f len:64
247 float_rem_un: dest:f src1:f src2:f len:64
248 float_neg: dest:f src1:f len:4
249 float_not: dest:f src1:f len:4
250 float_conv_to_i1: dest:i src1:f len:40
251 float_conv_to_i2: dest:i src1:f len:40
252 float_conv_to_i4: dest:i src1:f len:40
253 float_conv_to_i8: dest:L src1:f len:40
254 float_conv_to_r4: dest:f src1:f len:8
255 float_conv_to_u4: dest:i src1:f len:40
256 float_conv_to_u8: dest:L src1:f len:40
257 float_conv_to_u2: dest:i src1:f len:40
258 float_conv_to_u1: dest:i src1:f len:40
259 float_conv_to_i: dest:i src1:f len:40
260 float_ceq: dest:i src1:f src2:f len:64
261 float_cgt: dest:i src1:f src2:f len:64
262 float_cgt_un: dest:i src1:f src2:f len:64
263 float_clt: dest:i src1:f src2:f len:64
264 float_clt_un: dest:i src1:f src2:f len:64
265 float_conv_to_u: dest:i src1:f len:64
267 op_endfilter: src1:i len:64
268 aot_const: dest:i len:64
269 adc: dest:i src1:i src2:i len:4
270 addcc: dest:i src1:i src2:i len:4
271 subcc: dest:i src1:i src2:i len:4
272 adc_imm: dest:i src1:i len:64
273 sbb: dest:i src1:i src2:i len:4
274 sbb_imm: dest:i src1:i len:64
276 op_bigmul: len:2 dest:L src1:a src2:i
277 op_bigmul_un: len:2 dest:L src1:a src2:i
278 fmove: dest:f src1:f len:8
281 int_add: dest:i src1:i src2:i len:64
282 int_sub: dest:i src1:i src2:i len:64
283 int_mul: dest:i src1:i src2:i len:64
284 int_div: dest:i src1:i src2:i len:64
285 int_div_un: dest:i src1:i src2:i len:64
286 int_rem: dest:i src1:i src2:i len:64
287 int_rem_un: dest:i src1:i src2:i len:64
288 int_and: dest:i src1:i src2:i len:64
289 int_or: dest:i src1:i src2:i len:64
290 int_xor: dest:i src1:i src2:i len:64
291 int_shl: dest:i src1:i src2:i len:64
292 int_shr: dest:i src1:i src2:i len:64
293 int_shr_un: dest:i src1:i src2:i len:64
294 int_adc: dest:i src1:i src2:i len:64
295 int_adc_imm: dest:i src1:i len:64
296 int_sbb: dest:i src1:i src2:i len:64
297 int_sbb_imm: dest:i src1:i len:64
298 int_addcc: dest:i src1:i src2:i len:64
299 int_subcc: dest:i src1:i src2:i len:64
300 int_add_imm: dest:i src1:i len:64
301 int_sub_imm: dest:i src1:i len:64
302 int_mul_imm: dest:i src1:i len:64
303 int_div_imm: dest:i src1:i len:64
304 int_div_un_imm: dest:i src1:i len:64
305 int_rem_imm: dest:i src1:i len:64
306 int_rem_un_imm: dest:i src1:i len:64
307 int_and_imm: dest:i src1:i len:64
308 int_or_imm: dest:i src1:i len:64
309 int_xor_imm: dest:i src1:i len:64
310 int_shl_imm: dest:i src1:i len:64
311 int_shr_imm: dest:i src1:i len:64
312 int_shr_un_imm: dest:i src1:i len:64
313 int_neg: dest:i src1:i len:64
314 int_not: dest:i src1:i len:64
315 int_ceq: dest:i len:64
316 int_cgt: dest:i len:64
317 int_cgt_un: dest:i len:64
318 int_clt: dest:i len:64
319 int_clt_un: dest:i len:64
331 memory_barrier: len:4