1 # S/390 cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
20 # len:number describe the maximun length in bytes of the instruction
21 # number is a positive integer
23 # cost:number describe how many cycles are needed to complete the instruction (unused)
25 # clob:spec describe if the instruction clobbers registers or has special needs
27 # spec can be one of the following characters:
28 # c clobbers caller-save registers
29 # r 'reserves' the destination register until a later instruction unreserves it
30 # used mostly to set output registers in function calls
32 # flags:spec describe if the instruction uses or sets the flags (unused)
34 # spec can be one of the following chars:
37 # m uses and modifies the flags
39 # res:spec describe what units are used in the processor (unused)
41 # delay: describe delay slots (unused)
43 # the required specifiers are: len, clob (if registers are clobbered), the registers
44 # specifiers if the registers are actually used, flags (when scheduling is implemented).
46 # See the code in mini-x86.c for more details on how the specifiers are used.
87 call: dest:a clob:c len:6
117 ldind.i1: dest:i len:8
118 ldind.u1: dest:i len:8
119 ldind.i2: dest:i len:8
120 ldind.u2: dest:i len:8
121 ldind.i4: dest:i len:8
122 ldind.u4: dest:i len:8
124 ldind.i: dest:i len:8
127 ldind.ref: dest:i len:8
128 stind.ref: src1:b src2:i
129 stind.i1: src1:b src2:i
130 stind.i2: src1:b src2:i
131 stind.i4: src1:b src2:i
133 stind.r4: src1:b src2:f
134 stind.r8: src1:b src2:f
136 add: dest:i src1:i src2:i len:4 clob:1
137 sub: dest:i src1:i src2:i len:4 clob:1
138 mul: dest:i src1:i src2:i len:4 clob:1
139 div: dest:a src1:i src2:i len:10 clob:d
140 div.un: dest:a src1:i src2:i len:12 clob:d
141 rem: dest:d src1:i src2:i len:10 clob:d
142 rem.un: dest:d src1:i src2:i len:12 clob:d
143 and: dest:i src1:i src2:i len:6 clob:1
144 or: dest:i src1:i src2:i len:4 clob:1
145 xor: dest:i src1:i src2:i len:4 clob:1
146 shl: dest:i src1:i src2:i clob:s len:6
147 shr: dest:i src1:i src2:i clob:s len:6
148 shr.un: dest:i src1:i src2:i clob:s len:6
149 neg: dest:i src1:i len:4 clob:1
150 not: dest:i src1:i len:8 clob:1
151 conv.i1: dest:i src1:i len:22
152 conv.i2: dest:i src1:i len:22
153 conv.i4: dest:i src1:i len:2
155 conv.r4: dest:f src1:i len:4
156 conv.r8: dest:f src1:i len:4
157 conv.u4: dest:i src1:i
166 conv.r.un: dest:f src1:i len:30
218 ckfinite: dest:f src1:f len:22
221 conv.u2: dest:i src1:i len:14
222 conv.u1: dest:i src1:i len:8
223 conv.i: dest:i src1:i len:2
228 mul.ovf: dest:i src1:i src2:i len:18 clob:1
229 # this opcode is handled specially in the code generator
230 mul.ovf.un: dest:i src1:i src2:i len:20 clob:1
238 conv.u: dest:i src1:i len:4
250 cgt.un: dest:i len:12
252 clt.un: dest:i len:12
261 localloc: dest:i src1:i len:40
288 compare: src1:i src2:i len:4
289 compare_imm: src1:i len:14
290 fcompare: src1:f src2:f len:14
297 setret: dest:a src1:i len:4
298 setlret: src1:i src2:i len:12
299 setreg: dest:i src1:i len:4 clob:r
300 setregimm: dest:i len:16 clob:r
301 setfreg: dest:f src1:f len:4 clob:r
302 checkthis: src1:b len:4
303 voidcall: len:8 clob:c
304 voidcall_reg: src1:i len:8 clob:c
305 voidcall_membase: src1:b len:12 clob:c
306 fcall: dest:f len:8 clob:c
307 fcall_reg: dest:f src1:i len:8 clob:c
308 fcall_membase: dest:f src1:b len:12 clob:c
309 lcall: dest:l len:8 clob:c
310 lcall_reg: dest:l src1:i len:8 clob:c
311 lcall_membase: dest:l src1:b len:12 clob:c
313 vcall_reg: src1:i len:8 clob:c
314 vcall_membase: src1:b len:12 clob:c
315 call_reg: dest:a src1:i len:8 clob:c
316 call_membase: dest:a src1:b len:12 clob:c
318 iconst: dest:i len:16
320 r4const: dest:f len:22
321 r8const: dest:f len:18
326 store_membase_imm: dest:b len:32
327 store_membase_reg: dest:b src1:i len:18
328 storei1_membase_imm: dest:b len:32
329 storei1_membase_reg: dest:b src1:i len:18
330 storei2_membase_imm: dest:b len:32
331 storei2_membase_reg: dest:b src1:i len:18
332 storei4_membase_imm: dest:b len:32
333 storei4_membase_reg: dest:b src1:i len:18
334 storei8_membase_imm: dest:b
335 storei8_membase_reg: dest:b src1:i
336 storer4_membase_reg: dest:b src1:f len:20
337 storer8_membase_reg: dest:b src1:f len:20
338 load_membase: dest:i src1:b len:18
339 loadi1_membase: dest:i src1:b len:40
340 loadu1_membase: dest:i src1:b len:26
341 loadi2_membase: dest:i src1:b len:22
342 loadu2_membase: dest:i src1:b len:26
343 loadi4_membase: dest:i src1:b len:18
344 loadu4_membase: dest:i src1:b len:18
345 loadi8_membase: dest:i src1:b
346 loadr4_membase: dest:f src1:b len:18
347 loadr8_membase: dest:f src1:b len:18
348 loadu4_mem: dest:i len:8
349 move: dest:i src1:i len:4
350 fmove: dest:f src1:f len:4
351 add_imm: dest:i src1:i len:18
352 addcc_imm: dest:i src1:i len:18
353 sub_imm: dest:i src1:i len:18
354 subcc_imm: dest:i src1:i len:18
355 mul_imm: dest:i src1:i len:18
356 # there is no actual support for division or reminder by immediate
357 # we simulate them, though (but we need to change the burg rules
358 # to allocate a symbolic reg for src2)
359 div_imm: dest:i src1:i src2:i len:24
360 div_un_imm: dest:i src1:i src2:i len:24
361 rem_imm: dest:i src1:i src2:i len:24
362 rem_un_imm: dest:i src1:i src2:i len:24
363 and_imm: dest:i src1:i len:16
364 or_imm: dest:i src1:i len:16
365 xor_imm: dest:i src1:i len:16
366 shl_imm: dest:i src1:i len:8
367 shr_imm: dest:i src1:i len:8
368 shr_un_imm: dest:i src1:i len:8
370 cond_exc_ne_un: len:8
372 cond_exc_lt_un: len:8
374 cond_exc_gt_un: len:8
376 cond_exc_ge_un: len:8
378 cond_exc_le_un: len:8
409 long_conv_to_ovf_i: dest:i src1:i src2:i len:44
413 long_mul_ovf: len: 18
414 long_mul_ovf_un: len: 18
417 long_conv_to_ovf_i1_un:
418 long_conv_to_ovf_i2_un:
419 long_conv_to_ovf_i4_un:
420 long_conv_to_ovf_i8_un:
421 long_conv_to_ovf_u1_un:
422 long_conv_to_ovf_u2_un:
423 long_conv_to_ovf_u4_un:
424 long_conv_to_ovf_u8_un:
425 long_conv_to_ovf_i_un:
426 long_conv_to_ovf_u_un:
440 long_conv_to_r_un: dest:f src1:i src2:i len:37
467 float_add: dest:f src1:f src2:f len:6
468 float_sub: dest:f src1:f src2:f len:6
469 float_mul: dest:f src1:f src2:f len:6
470 float_div: dest:f src1:f src2:f len:6
471 float_div_un: dest:f src1:f src2:f len:6
472 float_rem: dest:f src1:f src2:f len:16
473 float_rem_un: dest:f src1:f src2:f len:16
474 float_neg: dest:f src1:f len:6
475 float_not: dest:f src1:f len:6
476 float_conv_to_i1: dest:i src1:f len:50
477 float_conv_to_i2: dest:i src1:f len:50
478 float_conv_to_i4: dest:i src1:f len:50
479 float_conv_to_i8: dest:l src1:f len:50
480 float_conv_to_r4: dest:f src1:f len:4
482 float_conv_to_u4: dest:i src1:f len:52
483 float_conv_to_u8: dest:l src1:f len:52
484 float_conv_to_u2: dest:i src1:f len:52
485 float_conv_to_u1: dest:i src1:f len:52
486 float_conv_to_i: dest:i src1:f len:52
495 float_conv_to_ovf_i1_un:
496 float_conv_to_ovf_i2_un:
497 float_conv_to_ovf_i4_un:
498 float_conv_to_ovf_i8_un:
499 float_conv_to_ovf_u1_un:
500 float_conv_to_ovf_u2_un:
501 float_conv_to_ovf_u4_un:
502 float_conv_to_ovf_u8_un:
503 float_conv_to_ovf_i_un:
504 float_conv_to_ovf_u_un:
505 float_conv_to_ovf_i1:
506 float_conv_to_ovf_u1:
507 float_conv_to_ovf_i2:
508 float_conv_to_ovf_u2:
509 float_conv_to_ovf_i4:
510 float_conv_to_ovf_u4:
511 float_conv_to_ovf_i8:
512 float_conv_to_ovf_u8:
513 float_ceq: dest:i src1:f src2:f len:16
514 float_cgt: dest:i src1:f src2:f len:16
515 float_cgt_un: dest:i src1:f src2:f len:16
516 float_clt: dest:i src1:f src2:f len:16
517 float_clt_un: dest:i src1:f src2:f len:16
518 float_conv_to_u: dest:i src1:f len:36
520 op_endfilter: src1:i len:12
521 aot_const: dest:i len:8
522 #x86_test_null: src1:i len:4
523 #x86_compare_membase_reg: src1:b src2:i len:8
524 #x86_compare_membase_imm: src1:b len:8
525 #x86_compare_reg_membase: src1:i src2:b len:8
526 #x86_inc_reg: dest:i src1:i clob:1 len:1
527 #x86_inc_membase: src1:b len:6
528 #x86_dec_reg: dest:i src1:i clob:1 len:1
529 #x86_dec_membase: src1:b len:6
530 #x86_add_membase_imm: src1:b len:8
531 #x86_sub_membase_imm: src1:b len:8
532 #x86_push: src1:i len:1
534 #x86_push_membase: src1:b len:6
535 #x86_push_obj: src1:b len:30
536 #x86_lea: dest:i src1:i src2:i len:7
537 #x86_xchg: src1:i src2:i clob:x len:1
538 #x86_fpop: src1:f len:2
539 #x86_fp_load_i8: dest:f src1:b len:7
540 #x86_fp_load_i4: dest:f src1:b len:7
541 sqrt: dest:f src1:f len:4
542 adc: dest:i src1:i src2:i len:6
543 addcc: dest:i src1:i src2:i len:6
544 subcc: dest:i src1:i src2:i len:6
545 adc_imm: dest:i src1:i len:14
546 sbb: dest:i src1:i src2:i len:6
547 sbb_imm: dest:i src1:i len:14
549 #ppc_subfic: dest:i src1:i len:4
550 #ppc_subfze: dest:i src1:i len:4
551 op_bigmul: len:2 dest:l src1:a src2:i
552 op_bigmul_un: len:2 dest:l src1:a src2:i