1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
20 # len:number describe the maximun length in bytes of the instruction
21 # number is a positive integer
23 # cost:number describe how many cycles are needed to complete the instruction (unused)
25 # clob:spec describe if the instruction clobbers registers or has special needs
27 # spec can be one of the following characters:
28 # c clobbers caller-save registers
29 # r 'reserves' the destination register until a later instruction unreserves it
30 # used mostly to set output registers in function calls
32 # flags:spec describe if the instruction uses or sets the flags (unused)
34 # spec can be one of the following chars:
37 # m uses and modifies the flags
39 # res:spec describe what units are used in the processor (unused)
41 # delay: describe delay slots (unused)
43 # the required specifiers are: len, clob (if registers are clobbered), the registers
44 # specifiers if the registers are actually used, flags (when scheduling is implemented).
46 # See the code in mini-x86.c for more details on how the specifiers are used.
52 call: dest:a clob:c len:16
64 add: dest:i src1:i src2:i len:4
65 sub: dest:i src1:i src2:i len:4
66 mul: dest:i src1:i src2:i len:4
67 div: dest:i src1:i src2:i len:40
68 div.un: dest:i src1:i src2:i len:16
69 rem: dest:i src1:i src2:i len:48
70 rem.un: dest:i src1:i src2:i len:24
71 and: dest:i src1:i src2:i len:4
72 or: dest:i src1:i src2:i len:4
73 xor: dest:i src1:i src2:i len:4
74 shl: dest:i src1:i src2:i len:4
75 shr: dest:i src1:i src2:i len:4
76 shr.un: dest:i src1:i src2:i len:4
77 neg: dest:i src1:i len:4
78 not: dest:i src1:i len:4
79 conv.i1: dest:i src1:i len:4
80 conv.i2: dest:i src1:i len:4
81 conv.i4: dest:i src1:i len:4
82 conv.r4: dest:f src1:i len:36
83 conv.r8: dest:f src1:i len:36
84 conv.u4: dest:i src1:i
85 conv.r.un: dest:f src1:i len:32
87 rethrow: src1:i len:20
89 ppc_check_finite: src1:i len:16
90 conv.u2: dest:i src1:i len:4
91 conv.u1: dest:i src1:i len:4
92 conv.i: dest:i src1:i len:4
93 add.ovf: dest:i src1:i src2:i len:16
94 add.ovf.un: dest:i src1:i src2:i len:16
95 mul.ovf: dest:i src1:i src2:i len:16
96 # this opcode is handled specially in the code generator
97 mul.ovf.un: dest:i src1:i src2:i len:16
98 sub.ovf: dest:i src1:i src2:i len:16
99 sub.ovf.un: dest:i src1:i src2:i len:16
100 add_ovf_carry: dest:i src1:i src2:i len:16
101 sub_ovf_carry: dest:i src1:i src2:i len:16
102 add_ovf_un_carry: dest:i src1:i src2:i len:16
103 sub_ovf_un_carry: dest:i src1:i src2:i len:16
104 start_handler: len:16
106 conv.u: dest:i src1:i len:4
109 cgt.un: dest:i len:12
111 clt.un: dest:i len:12
112 localloc: dest:i src1:i len:60
113 compare: src1:i src2:i len:4
114 compare_imm: src1:i len:12
115 fcompare: src1:f src2:f len:12
116 oparglist: src1:i len:12
119 setret: dest:a src1:i len:4
120 setlret: src1:i src2:i len:12
121 checkthis: src1:b len:4
122 voidcall: len:16 clob:c
123 voidcall_reg: src1:i len:8 clob:c
124 voidcall_membase: src1:b len:12 clob:c
125 fcall: dest:g len:16 clob:c
126 fcall_reg: dest:g src1:i len:8 clob:c
127 fcall_membase: dest:g src1:b len:12 clob:c
128 lcall: dest:l len:16 clob:c
129 lcall_reg: dest:l src1:i len:8 clob:c
130 lcall_membase: dest:l src1:b len:12 clob:c
132 vcall_reg: src1:i len:8 clob:c
133 vcall_membase: src1:b len:12 clob:c
134 call_reg: dest:a src1:i len:8 clob:c
135 call_membase: dest:a src1:b len:12 clob:c
136 iconst: dest:i len:12
137 r4const: dest:f len:12
138 r8const: dest:f len:12
140 store_membase_reg: dest:b src1:i len:4
141 storei1_membase_reg: dest:b src1:i len:4
142 storei2_membase_reg: dest:b src1:i len:4
143 storei4_membase_reg: dest:b src1:i len:4
144 storer4_membase_reg: dest:b src1:f len:8
145 storer8_membase_reg: dest:b src1:f len:4
146 load_membase: dest:i src1:b len:4
147 loadi1_membase: dest:i src1:b len:8
148 loadu1_membase: dest:i src1:b len:4
149 loadi2_membase: dest:i src1:b len:4
150 loadu2_membase: dest:i src1:b len:4
151 loadi4_membase: dest:i src1:b len:4
152 loadu4_membase: dest:i src1:b len:4
153 loadr4_membase: dest:f src1:b len:4
154 loadr8_membase: dest:f src1:b len:4
155 load_memindex: dest:i src1:b src2:i len:4
156 loadi1_memindex: dest:i src1:b src2:i len:8
157 loadu1_memindex: dest:i src1:b src2:i len:4
158 loadi2_memindex: dest:i src1:b src2:i len:4
159 loadu2_memindex: dest:i src1:b src2:i len:4
160 loadi4_memindex: dest:i src1:b src2:i len:4
161 loadu4_memindex: dest:i src1:b src2:i len:4
162 loadr4_memindex: dest:f src1:b src2:i len:4
163 loadr8_memindex: dest:f src1:b src2:i len:4
164 store_memindex: dest:b src1:i src2:i len:4
165 storei1_memindex: dest:b src1:i src2:i len:4
166 storei2_memindex: dest:b src1:i src2:i len:4
167 storei4_memindex: dest:b src1:i src2:i len:4
168 storer4_memindex: dest:b src1:i src2:i len:4
169 storer8_memindex: dest:b src1:i src2:i len:4
170 loadu4_mem: dest:i len:8
171 move: dest:i src1:i len:4
172 fmove: dest:f src1:f len:4
173 add_imm: dest:i src1:i len:4
174 sub_imm: dest:i src1:i len:4
175 mul_imm: dest:i src1:i len:4
176 # there is no actual support for division or reminder by immediate
177 # we simulate them, though (but we need to change the burg rules
178 # to allocate a symbolic reg for src2)
179 div_imm: dest:i src1:i src2:i len:20
180 div_un_imm: dest:i src1:i src2:i len:12
181 rem_imm: dest:i src1:i src2:i len:28
182 rem_un_imm: dest:i src1:i src2:i len:16
183 and_imm: dest:i src1:i len:4
184 or_imm: dest:i src1:i len:4
185 xor_imm: dest:i src1:i len:4
186 shl_imm: dest:i src1:i len:4
187 shr_imm: dest:i src1:i len:4
188 shr_un_imm: dest:i src1:i len:4
190 cond_exc_ne_un: len:8
192 cond_exc_lt_un: len:8
194 cond_exc_gt_un: len:8
196 cond_exc_ge_un: len:8
198 cond_exc_le_un: len:8
203 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
205 long_conv_to_r_un: dest:f src1:i src2:i len:37
216 float_add: dest:f src1:f src2:f len:4
217 float_sub: dest:f src1:f src2:f len:4
218 float_mul: dest:f src1:f src2:f len:4
219 float_div: dest:f src1:f src2:f len:4
220 float_div_un: dest:f src1:f src2:f len:4
221 float_rem: dest:f src1:f src2:f len:16
222 float_rem_un: dest:f src1:f src2:f len:16
223 float_neg: dest:f src1:f len:4
224 float_not: dest:f src1:f len:4
225 float_conv_to_i1: dest:i src1:f len:40
226 float_conv_to_i2: dest:i src1:f len:40
227 float_conv_to_i4: dest:i src1:f len:40
228 float_conv_to_i8: dest:l src1:f len:40
229 float_conv_to_r4: dest:f src1:f len:4
230 float_conv_to_u4: dest:i src1:f len:40
231 float_conv_to_u8: dest:l src1:f len:40
232 float_conv_to_u2: dest:i src1:f len:40
233 float_conv_to_u1: dest:i src1:f len:40
234 float_conv_to_i: dest:i src1:f len:40
235 float_ceq: dest:i src1:f src2:f len:16
236 float_cgt: dest:i src1:f src2:f len:16
237 float_cgt_un: dest:i src1:f src2:f len:20
238 float_clt: dest:i src1:f src2:f len:16
239 float_clt_un: dest:i src1:f src2:f len:20
240 float_conv_to_u: dest:i src1:f len:36
242 endfilter: src1:i len:16
243 aot_const: dest:i len:8
244 sqrt: dest:f src1:f len:4
245 adc: dest:i src1:i src2:i len:4
246 addcc: dest:i src1:i src2:i len:4
247 subcc: dest:i src1:i src2:i len:4
248 addcc_imm: dest:i src1:i len:4
249 sbb: dest:i src1:i src2:i len:4
251 ppc_subfic: dest:i src1:i len:4
252 ppc_subfze: dest:i src1:i len:4
253 bigmul: len:12 dest:l src1:i src2:i
254 bigmul_un: len:12 dest:l src1:i src2:i
255 tls_get: len:8 dest:i