1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
21 # len:number describe the maximun length in bytes of the instruction
22 # number is a positive integer
24 # cost:number describe how many cycles are needed to complete the instruction (unused)
26 # clob:spec describe if the instruction clobbers registers or has special needs
28 # spec can be one of the following characters:
29 # c clobbers caller-save registers
30 # 1 clobbers the first source register
32 # d EAX and EDX are clobbered
33 # s the src1 operand needs to be in ECX (shift opcodes)
34 # x both the source operands are clobbered (xchg)
36 # flags:spec describe if the instruction uses or sets the flags (unused)
38 # spec can be one of the following chars:
41 # m uses and modifies the flags
43 # res:spec describe what units are used in the processor (unused)
45 # delay: describe delay slots (unused)
47 # the required specifiers are: len, clob (if registers are clobbered), the registers
48 # specifiers if the registers are actually used, flags (when scheduling is implemented).
50 # See the code in mini-x86.c for more details on how the specifiers are used.
92 call: dest:a clob:c len:11
122 ldind.i1: dest:i len:6
123 ldind.u1: dest:i len:6
124 ldind.i2: dest:i len:6
125 ldind.u2: dest:i len:6
126 ldind.i4: dest:i len:6
127 ldind.u4: dest:i len:6
129 ldind.i: dest:i len:6
132 ldind.ref: dest:i len:6
133 stind.ref: src1:b src2:i
134 stind.i1: src1:b src2:i
135 stind.i2: src1:b src2:i
136 stind.i4: src1:b src2:i
138 stind.r4: src1:b src2:f
139 stind.r8: src1:b src2:f
140 add: dest:i src1:i src2:i len:2 clob:1
141 sub: dest:i src1:i src2:i len:2 clob:1
142 mul: dest:i src1:i src2:i len:3 clob:1
143 div: dest:a src1:i src2:i len:15 clob:d
144 div.un: dest:a src1:i src2:i len:15 clob:d
145 rem: dest:d src1:i src2:i len:15 clob:d
146 rem.un: dest:d src1:i src2:i len:15 clob:d
147 and: dest:i src1:i src2:i len:2 clob:1
148 or: dest:i src1:i src2:i len:2 clob:1
149 xor: dest:i src1:i src2:i len:2 clob:1
150 shl: dest:i src1:i src2:i clob:s len:2
151 shr: dest:i src1:i src2:i clob:s len:2
152 shr.un: dest:i src1:i src2:i clob:s len:2
153 neg: dest:i src1:i len:2 clob:1
154 not: dest:i src1:i len:2 clob:1
155 conv.i1: dest:i src1:i len:3
156 conv.i2: dest:i src1:i len:3
157 conv.i4: dest:i src1:i len:2
159 conv.r4: dest:f src1:i len:7
160 conv.r8: dest:f src1:i len:7
161 conv.u4: dest:i src1:i
247 ckfinite: dest:f src1:f len:22
261 conv.u2: dest:i src1:i len:3
262 conv.u1: dest:i src1:i len:3
263 conv.i: dest:i src1:i len:3
268 mul.ovf: dest:i src1:i src2:i clob:1 len:9
269 # this opcode is handled specially in the code generator
270 mul.ovf.un: dest:i src1:i src2:i len:12
277 conv.u: dest:i src1:i len:3
324 localloc: dest:i src1:i len:30
360 compare: src1:i src2:i len:2
361 compare_imm: src1:i len:6
362 fcompare: src1:f src2:f clob:a len:9
369 setret: dest:a src1:i len:2
370 setlret: dest:l src1:i src2:i len:4
371 checkthis: src1:b len:3
372 voidcall: len:11 clob:c
373 voidcall_reg: src1:i len:5 clob:c
374 voidcall_membase: src1:b len:10 clob:c
375 fcall: dest:f len:8 clob:c
376 fcall_reg: dest:f src1:i len:5 clob:c
377 fcall_membase: dest:f src1:b len:10 clob:c
378 lcall: dest:l len:8 clob:c
379 lcall_reg: dest:l src1:i len:5 clob:c
380 lcall_membase: dest:l src1:b len:10 clob:c
382 vcall_reg: src1:i len:5 clob:c
383 vcall_membase: src1:b len:10 clob:c
384 call_reg: dest:i src1:i len:5 clob:c
385 call_membase: dest:i src1:b len:10 clob:c
389 r4const: dest:f len:6
390 r8const: dest:f len:6
395 store_membase_imm: dest:b len:10
396 store_membase_reg: dest:b src1:i len:7
397 storei1_membase_imm: dest:b len:10
398 storei1_membase_reg: dest:b src1:i len:7
399 storei2_membase_imm: dest:b len:11
400 storei2_membase_reg: dest:b src1:i len:7
401 storei4_membase_imm: dest:b len:10
402 storei4_membase_reg: dest:b src1:i len:7
403 storei8_membase_imm: dest:b
404 storei8_membase_reg: dest:b src1:i
405 storer4_membase_reg: dest:b src1:f len:7
406 storer8_membase_reg: dest:b src1:f len:6
407 load_membase: dest:i src1:b len:6
408 loadi1_membase: dest:i src1:b len:7
409 loadu1_membase: dest:i src1:b len:7
410 loadi2_membase: dest:i src1:b len:7
411 loadu2_membase: dest:i src1:b len:7
412 loadi4_membase: dest:i src1:b len:6
413 loadu4_membase: dest:i src1:b len:6
414 loadi8_membase: dest:i src1:b
415 loadr4_membase: dest:f src1:b len:6
416 loadr8_membase: dest:f src1:b len:6
417 loadu4_mem: dest:i len:9
418 move: dest:i src1:i len:2
419 add_imm: dest:i src1:i len:6 clob:1
420 sub_imm: dest:i src1:i len:6 clob:1
421 mul_imm: dest:i src1:i len:6
422 # there is no actual support for division or reminder by immediate
423 # we simulate them, though (but we need to change the burg rules
424 # to allocate a symbolic reg for src2)
425 div_imm: dest:a src1:i src2:i len:15 clob:d
426 div_un_imm: dest:a src1:i src2:i len:15 clob:d
427 rem_imm: dest:d src1:i src2:i len:15 clob:d
428 rem_un_imm: dest:d src1:i src2:i len:15 clob:d
429 and_imm: dest:i src1:i len:6 clob:1
430 or_imm: dest:i src1:i len:6 clob:1
431 xor_imm: dest:i src1:i len:6 clob:1
432 shl_imm: dest:i src1:i len:6 clob:1
433 shr_imm: dest:i src1:i len:6 clob:1
434 shr_un_imm: dest:i src1:i len:6 clob:1
436 cond_exc_ne_un: len:6
438 cond_exc_lt_un: len:6
440 cond_exc_gt_un: len:6
442 cond_exc_ge_un: len:6
444 cond_exc_le_un: len:6
475 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
483 long_conv_to_ovf_i1_un:
484 long_conv_to_ovf_i2_un:
485 long_conv_to_ovf_i4_un:
486 long_conv_to_ovf_i8_un:
487 long_conv_to_ovf_u1_un:
488 long_conv_to_ovf_u2_un:
489 long_conv_to_ovf_u4_un:
490 long_conv_to_ovf_u8_un:
491 long_conv_to_ovf_i_un:
492 long_conv_to_ovf_u_un:
506 long_conv_to_r_un: dest:f src1:i src2:i len:37
540 float_neg: dest:f src1:f len:2
541 float_not: dest:f src1:f len:2
542 float_conv_to_i1: dest:i src1:f len:39
543 float_conv_to_i2: dest:i src1:f len:39
544 float_conv_to_i4: dest:i src1:f len:39
545 float_conv_to_i8: dest:l src1:f len:39
548 float_conv_to_u4: dest:i src1:f len:39
549 float_conv_to_u8: dest:l src1:f len:39
550 float_conv_to_u2: dest:i src1:f len:39
551 float_conv_to_u1: dest:i src1:f len:39
552 float_conv_to_i: dest:i src1:f len:39
553 float_conv_to_ovf_i: dest:a src1:f len:30
554 float_conv_to_ovd_u: dest:a src1:f len:30
561 float_conv_to_ovf_i1_un:
562 float_conv_to_ovf_i2_un:
563 float_conv_to_ovf_i4_un:
564 float_conv_to_ovf_i8_un:
565 float_conv_to_ovf_u1_un:
566 float_conv_to_ovf_u2_un:
567 float_conv_to_ovf_u4_un:
568 float_conv_to_ovf_u8_un:
569 float_conv_to_ovf_i_un:
570 float_conv_to_ovf_u_un:
571 float_conv_to_ovf_i1:
572 float_conv_to_ovf_u1:
573 float_conv_to_ovf_i2:
574 float_conv_to_ovf_u2:
575 float_conv_to_ovf_i4:
576 float_conv_to_ovf_u4:
577 float_conv_to_ovf_i8:
578 float_conv_to_ovf_u8:
579 float_ceq: dest:i src1:f src2:f len:25
580 float_cgt: dest:i src1:f src2:f len:25
581 float_cgt_un: dest:i src1:f src2:f len:37
582 float_clt: dest:i src1:f src2:f len:25
583 float_clt_un: dest:i src1:f src2:f len:32
584 float_conv_to_u: dest:i src1:f len:36
586 aot_const: dest:i len:5
587 x86_test_null: src1:i len:2
588 x86_compare_membase_reg: src1:b src2:i len:6
589 x86_compare_membase_imm: src1:b len:10
590 x86_compare_reg_membase: src1:i src2:b len:6
591 x86_inc_reg: dest:i src1:i clob:1 len:1
592 x86_inc_membase: src1:b len:6
593 x86_dec_reg: dest:i src1:i clob:1 len:1
594 x86_dec_membase: src1:b len:6
595 x86_add_membase_imm: src1:b len:8
596 x86_sub_membase_imm: src1:b len:8
597 x86_push: src1:i len:1
599 x86_push_membase: src1:b len:6
600 x86_push_obj: src1:b len:30
601 x86_lea: dest:i src1:i src2:i len:7
602 x86_xchg: src1:i src2:i clob:x len:1
603 x86_fpop: src1:f len:2
604 x86_fp_load_i8: dest:f src1:b len:7
605 x86_fp_load_i4: dest:f src1:b len:7
606 x86_seteq_membase: src1:b len:7
607 adc: dest:i src1:i src2:i len:2 clob:1
608 addcc: dest:i src1:i src2:i len:2 clob:1
609 subcc: dest:i src1:i src2:i len:2 clob:1
610 adc_imm: dest:i src1:i len:6 clob:1
611 sbb: dest:i src1:i src2:i len:2 clob:1
612 sbb_imm: dest:i src1:i len:6 clob:1
614 sin: dest:f src1:f len:2
615 cos: dest:f src1:f len:2
616 abs: dest:f src1:f len:2
617 tan: dest:f src1:f len:2
618 atan: dest:f src1:f len:2
619 sqrt: dest:f src1:f len:2
620 sext_i1: dest:i src1:i len:3
621 sext_i2: dest:i src1:i len:3