1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
21 # len:number describe the maximun length in bytes of the instruction
22 # number is a positive integer
24 # cost:number describe how many cycles are needed to complete the instruction (unused)
26 # clob:spec describe if the instruction clobbers registers or has special needs
28 # spec can be one of the following characters:
29 # c clobbers caller-save registers
30 # 1 clobbers the first source register
32 # d EAX and EDX are clobbered
33 # s the src1 operand needs to be in ECX (shift opcodes)
34 # x both the source operands are clobbered (xchg)
36 # flags:spec describe if the instruction uses or sets the flags (unused)
38 # spec can be one of the following chars:
41 # m uses and modifies the flags
43 # res:spec describe what units are used in the processor (unused)
45 # delay: describe delay slots (unused)
47 # the required specifiers are: len, clob (if registers are clobbered), the registers
48 # specifiers if the registers are actually used, flags (when scheduling is implemented).
50 # See the code in mini-x86.c for more details on how the specifiers are used.
91 call: dest:a clob:c len:11
121 ldind.i1: dest:i len:6
122 ldind.u1: dest:i len:6
123 ldind.i2: dest:i len:6
124 ldind.u2: dest:i len:6
125 ldind.i4: dest:i len:6
126 ldind.u4: dest:i len:6
128 ldind.i: dest:i len:6
131 ldind.ref: dest:i len:6
132 stind.ref: src1:b src2:i
133 stind.i1: src1:b src2:i
134 stind.i2: src1:b src2:i
135 stind.i4: src1:b src2:i
137 stind.r4: src1:b src2:f
138 stind.r8: src1:b src2:f
139 add: dest:i src1:i src2:i len:2 clob:1
140 sub: dest:i src1:i src2:i len:2 clob:1
141 mul: dest:i src1:i src2:i len:3 clob:1
142 div: dest:a src1:i src2:i len:15 clob:d
143 div.un: dest:a src1:i src2:i len:15 clob:d
144 rem: dest:d src1:i src2:i len:15 clob:d
145 rem.un: dest:d src1:i src2:i len:15 clob:d
146 and: dest:i src1:i src2:i len:2 clob:1
147 or: dest:i src1:i src2:i len:2 clob:1
148 xor: dest:i src1:i src2:i len:2 clob:1
149 shl: dest:i src1:i src2:i clob:s len:2
150 shr: dest:i src1:i src2:i clob:s len:2
151 shr.un: dest:i src1:i src2:i clob:s len:2
152 neg: dest:i src1:i len:2 clob:1
153 not: dest:i src1:i len:2 clob:1
154 conv.i1: dest:i src1:i len:3
155 conv.i2: dest:i src1:i len:3
156 conv.i4: dest:i src1:i len:2
158 conv.r4: dest:f src1:i len:7
159 conv.r8: dest:f src1:i len:7
160 conv.u4: dest:i src1:i
221 ckfinite: dest:f src1:f len:22
224 conv.u2: dest:i src1:i len:3
225 conv.u1: dest:i src1:i len:3
226 conv.i: dest:i src1:i len:3
231 mul.ovf: dest:i src1:i src2:i clob:1 len:9
232 # this opcode is handled specially in the code generator
233 mul.ovf.un: dest:i src1:i src2:i len:12
240 conv.u: dest:i src1:i len:3
263 localloc: dest:i src1:i len:32
290 compare: src1:i src2:i len:2
291 compare_imm: src1:i len:6
292 fcompare: src1:f src2:f clob:a len:9
296 oparglist: src1:b len:10
300 setret: dest:a src1:i len:2
301 setlret: dest:l src1:i src2:i len:4
302 checkthis: src1:b len:3
303 voidcall: len:11 clob:c
304 voidcall_reg: src1:i len:5 clob:c
305 voidcall_membase: src1:b len:10 clob:c
306 fcall: dest:f len:8 clob:c
307 fcall_reg: dest:f src1:i len:5 clob:c
308 fcall_membase: dest:f src1:b len:10 clob:c
309 lcall: dest:l len:8 clob:c
310 lcall_reg: dest:l src1:i len:5 clob:c
311 lcall_membase: dest:l src1:b len:10 clob:c
313 vcall_reg: src1:i len:5 clob:c
314 vcall_membase: src1:b len:10 clob:c
315 call_reg: dest:a src1:i len:5 clob:c
316 call_membase: dest:a src1:b len:10 clob:c
320 r4const: dest:f len:6
321 r8const: dest:f len:6
326 store_membase_imm: dest:b len:10
327 store_membase_reg: dest:b src1:i len:7
328 storei1_membase_imm: dest:b len:10
329 storei1_membase_reg: dest:b src1:i len:7
330 storei2_membase_imm: dest:b len:11
331 storei2_membase_reg: dest:b src1:i len:7
332 storei4_membase_imm: dest:b len:10
333 storei4_membase_reg: dest:b src1:i len:7
334 storei8_membase_imm: dest:b
335 storei8_membase_reg: dest:b src1:i
336 storer4_membase_reg: dest:b src1:f len:7
337 storer8_membase_reg: dest:b src1:f len:6
338 load_membase: dest:i src1:b len:6
339 loadi1_membase: dest:i src1:b len:7
340 loadu1_membase: dest:i src1:b len:7
341 loadi2_membase: dest:i src1:b len:7
342 loadu2_membase: dest:i src1:b len:7
343 loadi4_membase: dest:i src1:b len:6
344 loadu4_membase: dest:i src1:b len:6
345 loadi8_membase: dest:i src1:b
346 loadr4_membase: dest:f src1:b len:6
347 loadr8_membase: dest:f src1:b len:6
348 loadu4_mem: dest:i len:9
349 move: dest:i src1:i len:2
350 add_imm: dest:i src1:i len:6 clob:1
351 sub_imm: dest:i src1:i len:6 clob:1
352 mul_imm: dest:i src1:i len:6
353 # there is no actual support for division or reminder by immediate
354 # we simulate them, though (but we need to change the burg rules
355 # to allocate a symbolic reg for src2)
356 div_imm: dest:a src1:i src2:i len:15 clob:d
357 div_un_imm: dest:a src1:i src2:i len:15 clob:d
358 rem_imm: dest:d src1:i src2:i len:15 clob:d
359 rem_un_imm: dest:d src1:i src2:i len:15 clob:d
360 and_imm: dest:i src1:i len:6 clob:1
361 or_imm: dest:i src1:i len:6 clob:1
362 xor_imm: dest:i src1:i len:6 clob:1
363 shl_imm: dest:i src1:i len:6 clob:1
364 shr_imm: dest:i src1:i len:6 clob:1
365 shr_un_imm: dest:i src1:i len:6 clob:1
367 cond_exc_ne_un: len:6
369 cond_exc_lt_un: len:6
371 cond_exc_gt_un: len:6
373 cond_exc_ge_un: len:6
375 cond_exc_le_un: len:6
406 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
414 long_conv_to_ovf_i1_un:
415 long_conv_to_ovf_i2_un:
416 long_conv_to_ovf_i4_un:
417 long_conv_to_ovf_i8_un:
418 long_conv_to_ovf_u1_un:
419 long_conv_to_ovf_u2_un:
420 long_conv_to_ovf_u4_un:
421 long_conv_to_ovf_u8_un:
422 long_conv_to_ovf_i_un:
423 long_conv_to_ovf_u_un:
437 long_conv_to_r_un: dest:f src1:i src2:i len:37
471 float_neg: dest:f src1:f len:2
472 float_not: dest:f src1:f len:2
473 float_conv_to_i1: dest:i src1:f len:39
474 float_conv_to_i2: dest:i src1:f len:39
475 float_conv_to_i4: dest:i src1:f len:39
476 float_conv_to_i8: dest:l src1:f len:39
479 float_conv_to_u4: dest:i src1:f len:39
480 float_conv_to_u8: dest:l src1:f len:39
481 float_conv_to_u2: dest:i src1:f len:39
482 float_conv_to_u1: dest:i src1:f len:39
483 float_conv_to_i: dest:i src1:f len:39
484 float_conv_to_ovf_i: dest:a src1:f len:30
485 float_conv_to_ovd_u: dest:a src1:f len:30
492 float_conv_to_ovf_i1_un:
493 float_conv_to_ovf_i2_un:
494 float_conv_to_ovf_i4_un:
495 float_conv_to_ovf_i8_un:
496 float_conv_to_ovf_u1_un:
497 float_conv_to_ovf_u2_un:
498 float_conv_to_ovf_u4_un:
499 float_conv_to_ovf_u8_un:
500 float_conv_to_ovf_i_un:
501 float_conv_to_ovf_u_un:
502 float_conv_to_ovf_i1:
503 float_conv_to_ovf_u1:
504 float_conv_to_ovf_i2:
505 float_conv_to_ovf_u2:
506 float_conv_to_ovf_i4:
507 float_conv_to_ovf_u4:
508 float_conv_to_ovf_i8:
509 float_conv_to_ovf_u8:
510 float_ceq: dest:i src1:f src2:f len:25
511 float_cgt: dest:i src1:f src2:f len:25
512 float_cgt_un: dest:i src1:f src2:f len:37
513 float_clt: dest:i src1:f src2:f len:25
514 float_clt_un: dest:i src1:f src2:f len:32
515 float_conv_to_u: dest:i src1:f len:36
517 aot_const: dest:i len:5
518 x86_test_null: src1:i len:2
519 x86_compare_membase_reg: src1:b src2:i len:6
520 x86_compare_membase_imm: src1:b len:10
521 x86_compare_reg_membase: src1:i src2:b len:6
522 x86_inc_reg: dest:i src1:i clob:1 len:1
523 x86_inc_membase: src1:b len:6
524 x86_dec_reg: dest:i src1:i clob:1 len:1
525 x86_dec_membase: src1:b len:6
526 x86_add_membase_imm: src1:b len:8
527 x86_sub_membase_imm: src1:b len:8
528 x86_push: src1:i len:1
530 x86_push_membase: src1:b len:6
531 x86_push_obj: src1:b len:30
532 x86_lea: dest:i src1:i src2:i len:7
533 x86_lea_membase: dest:i src1:i len:10
534 x86_xchg: src1:i src2:i clob:x len:1
535 x86_fpop: src1:f len:2
536 x86_fp_load_i8: dest:f src1:b len:7
537 x86_fp_load_i4: dest:f src1:b len:7
538 x86_seteq_membase: src1:b len:7
539 adc: dest:i src1:i src2:i len:2 clob:1
540 addcc: dest:i src1:i src2:i len:2 clob:1
541 subcc: dest:i src1:i src2:i len:2 clob:1
542 adc_imm: dest:i src1:i len:6 clob:1
543 sbb: dest:i src1:i src2:i len:2 clob:1
544 sbb_imm: dest:i src1:i len:6 clob:1
546 sin: dest:f src1:f len:2
547 cos: dest:f src1:f len:2
548 abs: dest:f src1:f len:2
549 tan: dest:f src1:f len:45
550 atan: dest:f src1:f len:4
551 sqrt: dest:f src1:f len:2
552 op_bigmul: len:2 dest:l src1:a src2:i
553 op_bigmul_un: len:2 dest:l src1:a src2:i
554 sext_i1: dest:i src1:i len:3
555 sext_i2: dest:i src1:i len:3