1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
21 # len:number describe the maximun length in bytes of the instruction
22 # number is a positive integer. If the length is not specified
23 # it defaults to zero. But lengths are only checked if the given opcode
24 # is encountered during compilation. Some opcodes, like CONV_U4 are
25 # transformed into other opcodes in the brg files, so they do not show up
26 # during code generation.
28 # cost:number describe how many cycles are needed to complete the instruction (unused)
30 # clob:spec describe if the instruction clobbers registers or has special needs
32 # spec can be one of the following characters:
33 # c clobbers caller-save registers
34 # 1 clobbers the first source register
36 # d EAX and EDX are clobbered
37 # s the src1 operand needs to be in ECX (shift opcodes)
38 # x both the source operands are clobbered (xchg)
40 # flags:spec describe if the instruction uses or sets the flags (unused)
42 # spec can be one of the following chars:
45 # m uses and modifies the flags
47 # res:spec describe what units are used in the processor (unused)
49 # delay: describe delay slots (unused)
51 # the required specifiers are: len, clob (if registers are clobbered), the registers
52 # specifiers if the registers are actually used, flags (when scheduling is implemented).
54 # See the code in mini-x86.c for more details on how the specifiers are used.
95 call: dest:a clob:c len:11
125 ldind.i1: dest:i len:6
126 ldind.u1: dest:i len:6
127 ldind.i2: dest:i len:6
128 ldind.u2: dest:i len:6
129 ldind.i4: dest:i len:6
130 ldind.u4: dest:i len:6
132 ldind.i: dest:i len:6
135 ldind.ref: dest:i len:6
136 stind.ref: src1:b src2:i
137 stind.i1: src1:b src2:i
138 stind.i2: src1:b src2:i
139 stind.i4: src1:b src2:i
141 stind.r4: dest:f src1:b
142 stind.r8: dest:f src1:b
143 add: dest:i src1:i src2:i len:2 clob:1
144 sub: dest:i src1:i src2:i len:2 clob:1
145 mul: dest:i src1:i src2:i len:3 clob:1
146 div: dest:a src1:i src2:i len:15 clob:d
147 div.un: dest:a src1:i src2:i len:15 clob:d
148 rem: dest:d src1:i src2:i len:15 clob:d
149 rem.un: dest:d src1:i src2:i len:15 clob:d
150 and: dest:i src1:i src2:i len:2 clob:1
151 or: dest:i src1:i src2:i len:2 clob:1
152 xor: dest:i src1:i src2:i len:2 clob:1
153 shl: dest:i src1:i src2:i clob:s len:2
154 shr: dest:i src1:i src2:i clob:s len:2
155 shr.un: dest:i src1:i src2:i clob:s len:2
156 neg: dest:i src1:i len:2 clob:1
157 not: dest:i src1:i len:2 clob:1
158 conv.i1: dest:i src1:i len:3
159 conv.i2: dest:i src1:i len:3
160 conv.i4: dest:i src1:i len:2
162 conv.r4: dest:f src1:i len:7
163 conv.r8: dest:f src1:i len:7
164 conv.u4: dest:i src1:i
225 ckfinite: dest:f src1:f len:22
228 conv.u2: dest:i src1:i len:3
229 conv.u1: dest:i src1:i len:3
230 conv.i: dest:i src1:i len:3
235 mul.ovf: dest:i src1:i src2:i clob:1 len:9
236 # this opcode is handled specially in the code generator
237 mul.ovf.un: dest:i src1:i src2:i len:16
244 conv.u: dest:i src1:i len:3
267 localloc: dest:i src1:i len:64
294 compare: src1:i src2:i len:2
295 compare_imm: src1:i len:6
296 fcompare: src1:f src2:f clob:a len:9
300 oparglist: src1:b len:10
304 setret: dest:a src1:i len:2
305 setlret: dest:l src1:i src2:i len:4
306 checkthis: src1:b len:3
307 voidcall: len:11 clob:c
308 voidcall_reg: src1:i len:11 clob:c
309 voidcall_membase: src1:b len:16 clob:c
310 fcall: dest:f len:11 clob:c
311 fcall_reg: dest:f src1:i len:11 clob:c
312 fcall_membase: dest:f src1:b len:16 clob:c
313 lcall: dest:l len:11 clob:c
314 lcall_reg: dest:l src1:i len:11 clob:c
315 lcall_membase: dest:l src1:b len:16 clob:c
317 vcall_reg: src1:i len:11 clob:c
318 vcall_membase: src1:b len:16 clob:c
319 call_reg: dest:a src1:i len:11 clob:c
320 call_membase: dest:a src1:b len:16 clob:c
324 r4const: dest:f len:6
325 r8const: dest:f len:6
330 store_membase_imm: dest:b len:10
331 store_membase_reg: dest:b src1:i len:7
332 storei1_membase_imm: dest:b len:10
333 storei1_membase_reg: dest:b src1:i len:7
334 storei2_membase_imm: dest:b len:11
335 storei2_membase_reg: dest:b src1:i len:7
336 storei4_membase_imm: dest:b len:10
337 storei4_membase_reg: dest:b src1:i len:7
338 storei8_membase_imm: dest:b
339 storei8_membase_reg: dest:b src1:i
340 storer4_membase_reg: dest:b src1:f len:7
341 storer8_membase_reg: dest:b src1:f len:6
342 load_membase: dest:i src1:b len:6
343 loadi1_membase: dest:i src1:b len:7
344 loadu1_membase: dest:i src1:b len:7
345 loadi2_membase: dest:i src1:b len:7
346 loadu2_membase: dest:i src1:b len:7
347 loadi4_membase: dest:i src1:b len:6
348 loadu4_membase: dest:i src1:b len:6
349 loadi8_membase: dest:i src1:b
350 loadr4_membase: dest:f src1:b len:6
351 loadr8_membase: dest:f src1:b len:6
352 loadr8_spill_membase: src1:b len:8
353 loadu4_mem: dest:i len:9
354 move: dest:i src1:i len:2
355 add_imm: dest:i src1:i len:6 clob:1
356 sub_imm: dest:i src1:i len:6 clob:1
357 mul_imm: dest:i src1:i len:6
358 # there is no actual support for division or reminder by immediate
359 # we simulate them, though (but we need to change the burg rules
360 # to allocate a symbolic reg for src2)
361 div_imm: dest:a src1:i src2:i len:15 clob:d
362 div_un_imm: dest:a src1:i src2:i len:15 clob:d
363 rem_imm: dest:d src1:i src2:i len:15 clob:d
364 rem_un_imm: dest:d src1:i src2:i len:15 clob:d
365 and_imm: dest:i src1:i len:6 clob:1
366 or_imm: dest:i src1:i len:6 clob:1
367 xor_imm: dest:i src1:i len:6 clob:1
368 shl_imm: dest:i src1:i len:6 clob:1
369 shr_imm: dest:i src1:i len:6 clob:1
370 shr_un_imm: dest:i src1:i len:6 clob:1
372 cond_exc_ne_un: len:6
374 cond_exc_lt_un: len:6
376 cond_exc_gt_un: len:6
378 cond_exc_ge_un: len:6
380 cond_exc_le_un: len:6
411 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
419 long_conv_to_ovf_i1_un:
420 long_conv_to_ovf_i2_un:
421 long_conv_to_ovf_i4_un:
422 long_conv_to_ovf_i8_un:
423 long_conv_to_ovf_u1_un:
424 long_conv_to_ovf_u2_un:
425 long_conv_to_ovf_u4_un:
426 long_conv_to_ovf_u8_un:
427 long_conv_to_ovf_i_un:
428 long_conv_to_ovf_u_un:
442 long_conv_to_r_un: dest:f src1:i src2:i len:37
469 float_add: src1:f src2:f len:2
470 float_sub: src1:f src2:f len:2
471 float_mul: src1:f src2:f len:2
472 float_div: src1:f src2:f len:2
473 float_div_un: src1:f src2:f len:2
474 float_rem: src1:f src2:f len:17
475 float_rem_un: src1:f src2:f len:17
476 float_neg: dest:f src1:f len:2
477 float_not: dest:f src1:f len:2
478 float_conv_to_i1: dest:i src1:f len:39
479 float_conv_to_i2: dest:i src1:f len:39
480 float_conv_to_i4: dest:i src1:f len:39
481 float_conv_to_i8: dest:l src1:f len:39
484 float_conv_to_u4: dest:i src1:f len:39
485 float_conv_to_u8: dest:l src1:f len:39
486 float_conv_to_u2: dest:i src1:f len:39
487 float_conv_to_u1: dest:i src1:f len:39
488 float_conv_to_i: dest:i src1:f len:39
489 float_conv_to_ovf_i: dest:a src1:f len:30
490 float_conv_to_ovd_u: dest:a src1:f len:30
497 float_conv_to_ovf_i1_un:
498 float_conv_to_ovf_i2_un:
499 float_conv_to_ovf_i4_un:
500 float_conv_to_ovf_i8_un:
501 float_conv_to_ovf_u1_un:
502 float_conv_to_ovf_u2_un:
503 float_conv_to_ovf_u4_un:
504 float_conv_to_ovf_u8_un:
505 float_conv_to_ovf_i_un:
506 float_conv_to_ovf_u_un:
507 float_conv_to_ovf_i1:
508 float_conv_to_ovf_u1:
509 float_conv_to_ovf_i2:
510 float_conv_to_ovf_u2:
511 float_conv_to_ovf_i4:
512 float_conv_to_ovf_u4:
513 float_conv_to_ovf_i8:
514 float_conv_to_ovf_u8:
515 float_ceq: dest:i src1:f src2:f len:25
516 float_cgt: dest:i src1:f src2:f len:25
517 float_cgt_un: dest:i src1:f src2:f len:37
518 float_clt: dest:i src1:f src2:f len:25
519 float_clt_un: dest:i src1:f src2:f len:32
520 float_conv_to_u: dest:i src1:f len:36
522 aot_const: dest:i len:5
523 x86_test_null: src1:i len:2
524 x86_compare_membase_reg: src1:b src2:i len:6
525 x86_compare_membase_imm: src1:b len:11
526 x86_compare_reg_membase: src1:i src2:b len:6
527 x86_inc_reg: dest:i src1:i clob:1 len:1
528 x86_inc_membase: src1:b len:6
529 x86_dec_reg: dest:i src1:i clob:1 len:1
530 x86_dec_membase: src1:b len:6
531 x86_add_membase_imm: src1:b len:11
532 x86_sub_membase_imm: src1:b len:11
533 x86_push: src1:i len:1
535 x86_push_membase: src1:b len:6
536 x86_push_obj: src1:b len:30
537 x86_lea: dest:i src1:i src2:i len:7
538 x86_lea_membase: dest:i src1:i len:10
539 x86_xchg: src1:i src2:i clob:x len:1
540 x86_fpop: src1:f len:2
541 x86_fp_load_i8: dest:f src1:b len:7
542 x86_fp_load_i4: dest:f src1:b len:7
543 x86_seteq_membase: src1:b len:7
544 x86_add_membase: dest:i src1:i src2:b clob:1 len:11
545 x86_sub_membase: dest:i src1:i src2:b clob:1 len:11
546 x86_mul_membase: dest:i src1:i src2:b clob:1 len:13
547 adc: dest:i src1:i src2:i len:2 clob:1
548 addcc: dest:i src1:i src2:i len:2 clob:1
549 subcc: dest:i src1:i src2:i len:2 clob:1
550 adc_imm: dest:i src1:i len:6 clob:1
551 sbb: dest:i src1:i src2:i len:2 clob:1
552 sbb_imm: dest:i src1:i len:6 clob:1
554 sin: dest:f src1:f len:2
555 cos: dest:f src1:f len:2
556 abs: dest:f src1:f len:2
557 tan: dest:f src1:f len:45
558 atan: dest:f src1:f len:4
559 sqrt: dest:f src1:f len:2
560 op_bigmul: len:2 dest:l src1:a src2:i
561 op_bigmul_un: len:2 dest:l src1:a src2:i
562 sext_i1: dest:i src1:i len:3
563 sext_i2: dest:i src1:i len:3