1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
20 # l long reg (forced eax:edx)
21 # L long reg (dynamic)
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer. If the length is not specified
25 # it defaults to zero. But lengths are only checked if the given opcode
26 # is encountered during compilation. Some opcodes, like CONV_U4 are
27 # transformed into other opcodes in the brg files, so they do not show up
28 # during code generation.
30 # cost:number describe how many cycles are needed to complete the instruction (unused)
32 # clob:spec describe if the instruction clobbers registers or has special needs
34 # spec can be one of the following characters:
35 # c clobbers caller-save registers
36 # 1 clobbers the first source register
38 # d EAX and EDX are clobbered
39 # s the src2 operand needs to be in ECX (shift opcodes)
40 # x both the source operands are clobbered (xchg)
42 # flags:spec describe if the instruction uses or sets the flags (unused)
44 # spec can be one of the following chars:
47 # m uses and modifies the flags
49 # res:spec describe what units are used in the processor (unused)
51 # delay: describe delay slots (unused)
53 # the required specifiers are: len, clob (if registers are clobbered), the registers
54 # specifiers if the registers are actually used, flags (when scheduling is implemented).
56 # See the code in mini-x86.c for more details on how the specifiers are used.
97 call: dest:a clob:c len:11
127 ldind.i1: dest:i len:6
128 ldind.u1: dest:i len:6
129 ldind.i2: dest:i len:6
130 ldind.u2: dest:i len:6
131 ldind.i4: dest:i len:6
132 ldind.u4: dest:i len:6
134 ldind.i: dest:i len:6
137 ldind.ref: dest:i len:6
138 stind.ref: src1:b src2:i
139 stind.i1: src1:b src2:i
140 stind.i2: src1:b src2:i
141 stind.i4: src1:b src2:i
143 stind.r4: dest:f src1:b
144 stind.r8: dest:f src1:b
145 add: dest:i src1:i src2:i len:2 clob:1
146 sub: dest:i src1:i src2:i len:2 clob:1
147 mul: dest:i src1:i src2:i len:3 clob:1
148 div: dest:a src1:i src2:i len:15 clob:d
149 div.un: dest:a src1:i src2:i len:15 clob:d
150 rem: dest:d src1:i src2:i len:15 clob:d
151 rem.un: dest:d src1:i src2:i len:15 clob:d
152 and: dest:i src1:i src2:i len:2 clob:1
153 or: dest:i src1:i src2:i len:2 clob:1
154 xor: dest:i src1:i src2:i len:2 clob:1
155 shl: dest:i src1:i src2:i clob:s len:2
156 shr: dest:i src1:i src2:i clob:s len:2
157 shr.un: dest:i src1:i src2:i clob:s len:2
158 neg: dest:i src1:i len:2 clob:1
159 not: dest:i src1:i len:2 clob:1
160 conv.i1: dest:i src1:i len:3
161 conv.i2: dest:i src1:i len:3
162 conv.i4: dest:i src1:i len:2
164 conv.r4: dest:f src1:i len:7
165 conv.r8: dest:f src1:i len:7
166 conv.u4: dest:i src1:i
178 op_rethrow: src1:i len:6
228 ckfinite: dest:f src1:f len:22
231 conv.u2: dest:i src1:i len:3
232 conv.u1: dest:i src1:i len:3
233 conv.i: dest:i src1:i len:3
238 mul.ovf: dest:i src1:i src2:i clob:1 len:9
239 # this opcode is handled specially in the code generator
240 mul.ovf.un: dest:i src1:i src2:i len:16
247 conv.u: dest:i src1:i len:3
271 localloc: dest:i src1:i len:80
293 compare: src1:i src2:i len:2
294 compare_imm: src1:i len:6
295 fcompare: src1:f src2:f clob:a len:9
299 oparglist: src1:b len:10
303 setret: dest:a src1:i len:2
304 setlret: dest:l src1:i src2:i len:4
305 checkthis: src1:b len:2
306 voidcall: len:11 clob:c
307 voidcall_reg: src1:i len:11 clob:c
308 voidcall_membase: src1:b len:16 clob:c
309 fcall: dest:f len:11 clob:c
310 fcall_reg: dest:f src1:i len:11 clob:c
311 fcall_membase: dest:f src1:b len:16 clob:c
312 lcall: dest:l len:11 clob:c
313 lcall_reg: dest:l src1:i len:11 clob:c
314 lcall_membase: dest:l src1:b len:16 clob:c
316 vcall_reg: src1:i len:11 clob:c
317 vcall_membase: src1:b len:16 clob:c
318 call_reg: dest:a src1:i len:11 clob:c
319 call_membase: dest:a src1:b len:16 clob:c
323 r4const: dest:f len:6
324 r8const: dest:f len:6
329 store_membase_imm: dest:b len:10
330 store_membase_reg: dest:b src1:i len:7
331 storei1_membase_imm: dest:b len:10
332 storei1_membase_reg: dest:b src1:i len:7
333 storei2_membase_imm: dest:b len:11
334 storei2_membase_reg: dest:b src1:i len:7
335 storei4_membase_imm: dest:b len:10
336 storei4_membase_reg: dest:b src1:i len:7
337 storei8_membase_imm: dest:b
338 storei8_membase_reg: dest:b src1:i
339 storer4_membase_reg: dest:b src1:f len:7
340 storer8_membase_reg: dest:b src1:f len:6
341 load_membase: dest:i src1:b len:6
342 loadi1_membase: dest:i src1:b len:7
343 loadu1_membase: dest:i src1:b len:7
344 loadi2_membase: dest:i src1:b len:7
345 loadu2_membase: dest:i src1:b len:7
346 loadi4_membase: dest:i src1:b len:6
347 loadu4_membase: dest:i src1:b len:6
348 loadi8_membase: dest:i src1:b
349 loadr4_membase: dest:f src1:b len:6
350 loadr8_membase: dest:f src1:b len:6
351 loadr8_spill_membase: src1:b len:8
352 loadu4_mem: dest:i len:9
353 move: dest:i src1:i len:2
354 addcc_imm: dest:i src1:i len:6 clob:1
355 add_imm: dest:i src1:i len:6 clob:1
356 subcc_imm: dest:i src1:i len:6 clob:1
357 sub_imm: dest:i src1:i len:6 clob:1
358 mul_imm: dest:i src1:i len:6
359 # there is no actual support for division or reminder by immediate
360 # we simulate them, though (but we need to change the burg rules
361 # to allocate a symbolic reg for src2)
362 div_imm: dest:a src1:i src2:i len:15 clob:d
363 div_un_imm: dest:a src1:i src2:i len:15 clob:d
364 rem_imm: dest:d src1:i src2:i len:15 clob:d
365 rem_un_imm: dest:d src1:i src2:i len:15 clob:d
366 and_imm: dest:i src1:i len:6 clob:1
367 or_imm: dest:i src1:i len:6 clob:1
368 xor_imm: dest:i src1:i len:6 clob:1
369 shl_imm: dest:i src1:i len:6 clob:1
370 shr_imm: dest:i src1:i len:6 clob:1
371 shr_un_imm: dest:i src1:i len:6 clob:1
373 cond_exc_ne_un: len:6
375 cond_exc_lt_un: len:6
377 cond_exc_gt_un: len:6
379 cond_exc_ge_un: len:6
381 cond_exc_le_un: len:6
396 long_shl: dest:L src1:L src2:i clob:s len:21
397 long_shr: dest:L src1:L src2:i clob:s len:22
398 long_shr_un: dest:L src1:L src2:i clob:s len:22
412 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
420 long_conv_to_ovf_i1_un:
421 long_conv_to_ovf_i2_un:
422 long_conv_to_ovf_i4_un:
423 long_conv_to_ovf_i8_un:
424 long_conv_to_ovf_u1_un:
425 long_conv_to_ovf_u2_un:
426 long_conv_to_ovf_u4_un:
427 long_conv_to_ovf_u8_un:
428 long_conv_to_ovf_i_un:
429 long_conv_to_ovf_u_un:
443 long_conv_to_r_un: dest:f src1:i src2:i len:37
445 long_shr_imm: dest:L src1:L len:10
446 long_shr_un_imm: dest:L src1:L len:10
447 long_shl_imm: dest:L src1:L len:10
470 float_add: dest:f src1:f src2:f len:2
471 float_sub: dest:f src1:f src2:f len:2
472 float_mul: dest:f src1:f src2:f len:2
473 float_div: dest:f src1:f src2:f len:2
474 float_div_un: dest:f src1:f src2:f len:2
475 float_rem: dest:f src1:f src2:f len:17
476 float_rem_un: dest:f src1:f src2:f len:17
477 float_neg: dest:f src1:f len:2
478 float_not: dest:f src1:f len:2
479 float_conv_to_i1: dest:i src1:f len:39
480 float_conv_to_i2: dest:i src1:f len:39
481 float_conv_to_i4: dest:i src1:f len:39
482 float_conv_to_i8: dest:L src1:f len:39
485 float_conv_to_u4: dest:i src1:f len:39
486 float_conv_to_u8: dest:L src1:f len:39
487 float_conv_to_u2: dest:i src1:f len:39
488 float_conv_to_u1: dest:i src1:f len:39
489 float_conv_to_i: dest:i src1:f len:39
490 float_conv_to_ovf_i: dest:a src1:f len:30
491 float_conv_to_ovd_u: dest:a src1:f len:30
498 float_conv_to_ovf_i1_un:
499 float_conv_to_ovf_i2_un:
500 float_conv_to_ovf_i4_un:
501 float_conv_to_ovf_i8_un:
502 float_conv_to_ovf_u1_un:
503 float_conv_to_ovf_u2_un:
504 float_conv_to_ovf_u4_un:
505 float_conv_to_ovf_u8_un:
506 float_conv_to_ovf_i_un:
507 float_conv_to_ovf_u_un:
508 float_conv_to_ovf_i1:
509 float_conv_to_ovf_u1:
510 float_conv_to_ovf_i2:
511 float_conv_to_ovf_u2:
512 float_conv_to_ovf_i4:
513 float_conv_to_ovf_u4:
514 float_conv_to_ovf_i8:
515 float_conv_to_ovf_u8:
516 float_ceq: dest:i src1:f src2:f len:25
517 float_cgt: dest:i src1:f src2:f len:25
518 float_cgt_un: dest:i src1:f src2:f len:37
519 float_clt: dest:i src1:f src2:f len:25
520 float_clt_un: dest:i src1:f src2:f len:32
521 float_conv_to_u: dest:i src1:f len:36
523 aot_const: dest:i len:5
524 load_gotaddr: dest:i len:64
525 got_entry: dest:i src1:b len:7
526 x86_test_null: src1:i len:2
527 x86_compare_membase_reg: src1:b src2:i len:6
528 x86_compare_membase_imm: src1:b len:11
529 x86_compare_membase8_imm: src1:b len:8
530 x86_compare_reg_membase: src1:i src2:b len:6
531 x86_inc_reg: dest:i src1:i clob:1 len:1
532 x86_inc_membase: src1:b len:6
533 x86_dec_reg: dest:i src1:i clob:1 len:1
534 x86_dec_membase: src1:b len:6
535 x86_add_membase_imm: src1:b len:11
536 x86_sub_membase_imm: src1:b len:11
537 x86_push: src1:i len:1
539 x86_push_membase: src1:b len:6
540 x86_push_obj: src1:b len:30
541 x86_push_got_entry: src1:b len:7
542 x86_lea: dest:i src1:i src2:i len:7
543 x86_lea_membase: dest:i src1:i len:10
544 x86_xchg: src1:i src2:i clob:x len:1
545 x86_fpop: src1:f len:2
546 x86_fp_load_i8: dest:f src1:b len:7
547 x86_fp_load_i4: dest:f src1:b len:7
548 x86_seteq_membase: src1:b len:7
549 x86_setne_membase: src1:b len:7
550 x86_add_membase: dest:i src1:i src2:b clob:1 len:11
551 x86_sub_membase: dest:i src1:i src2:b clob:1 len:11
552 x86_mul_membase: dest:i src1:i src2:b clob:1 len:13
553 adc: dest:i src1:i src2:i len:2 clob:1
554 addcc: dest:i src1:i src2:i len:2 clob:1
555 subcc: dest:i src1:i src2:i len:2 clob:1
556 adc_imm: dest:i src1:i len:6 clob:1
557 sbb: dest:i src1:i src2:i len:2 clob:1
558 sbb_imm: dest:i src1:i len:6 clob:1
560 sin: dest:f src1:f len:6
561 cos: dest:f src1:f len:6
562 abs: dest:f src1:f len:2
563 tan: dest:f src1:f len:49
564 atan: dest:f src1:f len:8
565 sqrt: dest:f src1:f len:2
566 op_bigmul: len:2 dest:l src1:a src2:i
567 op_bigmul_un: len:2 dest:l src1:a src2:i
568 sext_i1: dest:i src1:i len:3
569 sext_i2: dest:i src1:i len:3
570 x86_tls_get: dest:i len:20
571 atomic_add_i4: src1:b src2:i dest:i len:16
572 atomic_exchange_i4: src1:b src2:i dest:i len:14
573 atomic_add_imm_i4: src1:b dest:i len:15
574 atomic_add_imm_prev_i4: src1:b dest:i len:10