1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
20 # l long reg (forced eax:edx)
21 # L long reg (dynamic)
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer. If the length is not specified
25 # it defaults to zero. But lengths are only checked if the given opcode
26 # is encountered during compilation. Some opcodes, like CONV_U4 are
27 # transformed into other opcodes in the brg files, so they do not show up
28 # during code generation.
30 # cost:number describe how many cycles are needed to complete the instruction (unused)
32 # clob:spec describe if the instruction clobbers registers or has special needs
34 # spec can be one of the following characters:
35 # c clobbers caller-save registers
36 # 1 clobbers the first source register
38 # d EAX and EDX are clobbered
39 # s the src2 operand needs to be in ECX (shift opcodes)
40 # x both the source operands are clobbered (xchg)
42 # flags:spec describe if the instruction uses or sets the flags (unused)
44 # spec can be one of the following chars:
47 # m uses and modifies the flags
49 # res:spec describe what units are used in the processor (unused)
51 # delay: describe delay slots (unused)
53 # the required specifiers are: len, clob (if registers are clobbered), the registers
54 # specifiers if the registers are actually used, flags (when scheduling is implemented).
56 # See the code in mini-x86.c for more details on how the specifiers are used.
97 call: dest:a clob:c len:11
127 ldind.i1: dest:i len:6
128 ldind.u1: dest:i len:6
129 ldind.i2: dest:i len:6
130 ldind.u2: dest:i len:6
131 ldind.i4: dest:i len:6
132 ldind.u4: dest:i len:6
134 ldind.i: dest:i len:6
137 ldind.ref: dest:i len:6
138 stind.ref: src1:b src2:i
139 stind.i1: src1:b src2:i
140 stind.i2: src1:b src2:i
141 stind.i4: src1:b src2:i
143 stind.r4: dest:f src1:b
144 stind.r8: dest:f src1:b
145 add: dest:i src1:i src2:i len:2 clob:1
146 sub: dest:i src1:i src2:i len:2 clob:1
147 mul: dest:i src1:i src2:i len:3 clob:1
148 div: dest:a src1:i src2:i len:15 clob:d
149 div.un: dest:a src1:i src2:i len:15 clob:d
150 rem: dest:d src1:i src2:i len:15 clob:d
151 rem.un: dest:d src1:i src2:i len:15 clob:d
152 and: dest:i src1:i src2:i len:2 clob:1
153 or: dest:i src1:i src2:i len:2 clob:1
154 xor: dest:i src1:i src2:i len:2 clob:1
155 shl: dest:i src1:i src2:i clob:s len:2
156 shr: dest:i src1:i src2:i clob:s len:2
157 shr.un: dest:i src1:i src2:i clob:s len:2
158 neg: dest:i src1:i len:2 clob:1
159 not: dest:i src1:i len:2 clob:1
160 conv.i1: dest:i src1:i len:3
161 conv.i2: dest:i src1:i len:3
162 conv.i4: dest:i src1:i len:2
164 conv.r4: dest:f src1:i len:7
165 conv.r8: dest:f src1:i len:7
166 conv.u4: dest:i src1:i
227 ckfinite: dest:f src1:f len:22
230 conv.u2: dest:i src1:i len:3
231 conv.u1: dest:i src1:i len:3
232 conv.i: dest:i src1:i len:3
237 mul.ovf: dest:i src1:i src2:i clob:1 len:9
238 # this opcode is handled specially in the code generator
239 mul.ovf.un: dest:i src1:i src2:i len:16
246 conv.u: dest:i src1:i len:3
269 localloc: dest:i src1:i len:64
296 compare: src1:i src2:i len:2
297 compare_imm: src1:i len:6
298 fcompare: src1:f src2:f clob:a len:9
302 oparglist: src1:b len:10
306 setret: dest:a src1:i len:2
307 setlret: dest:l src1:i src2:i len:4
308 checkthis: src1:b len:3
309 voidcall: len:11 clob:c
310 voidcall_reg: src1:i len:11 clob:c
311 voidcall_membase: src1:b len:16 clob:c
312 fcall: dest:f len:11 clob:c
313 fcall_reg: dest:f src1:i len:11 clob:c
314 fcall_membase: dest:f src1:b len:16 clob:c
315 lcall: dest:l len:11 clob:c
316 lcall_reg: dest:l src1:i len:11 clob:c
317 lcall_membase: dest:l src1:b len:16 clob:c
319 vcall_reg: src1:i len:11 clob:c
320 vcall_membase: src1:b len:16 clob:c
321 call_reg: dest:a src1:i len:11 clob:c
322 call_membase: dest:a src1:b len:16 clob:c
326 r4const: dest:f len:6
327 r8const: dest:f len:6
332 store_membase_imm: dest:b len:10
333 store_membase_reg: dest:b src1:i len:7
334 storei1_membase_imm: dest:b len:10
335 storei1_membase_reg: dest:b src1:i len:7
336 storei2_membase_imm: dest:b len:11
337 storei2_membase_reg: dest:b src1:i len:7
338 storei4_membase_imm: dest:b len:10
339 storei4_membase_reg: dest:b src1:i len:7
340 storei8_membase_imm: dest:b
341 storei8_membase_reg: dest:b src1:i
342 storer4_membase_reg: dest:b src1:f len:7
343 storer8_membase_reg: dest:b src1:f len:6
344 load_membase: dest:i src1:b len:6
345 loadi1_membase: dest:i src1:b len:7
346 loadu1_membase: dest:i src1:b len:7
347 loadi2_membase: dest:i src1:b len:7
348 loadu2_membase: dest:i src1:b len:7
349 loadi4_membase: dest:i src1:b len:6
350 loadu4_membase: dest:i src1:b len:6
351 loadi8_membase: dest:i src1:b
352 loadr4_membase: dest:f src1:b len:6
353 loadr8_membase: dest:f src1:b len:6
354 loadr8_spill_membase: src1:b len:8
355 loadu4_mem: dest:i len:9
356 move: dest:i src1:i len:2
357 add_imm: dest:i src1:i len:6 clob:1
358 sub_imm: dest:i src1:i len:6 clob:1
359 mul_imm: dest:i src1:i len:6
360 # there is no actual support for division or reminder by immediate
361 # we simulate them, though (but we need to change the burg rules
362 # to allocate a symbolic reg for src2)
363 div_imm: dest:a src1:i src2:i len:15 clob:d
364 div_un_imm: dest:a src1:i src2:i len:15 clob:d
365 rem_imm: dest:d src1:i src2:i len:15 clob:d
366 rem_un_imm: dest:d src1:i src2:i len:15 clob:d
367 and_imm: dest:i src1:i len:6 clob:1
368 or_imm: dest:i src1:i len:6 clob:1
369 xor_imm: dest:i src1:i len:6 clob:1
370 shl_imm: dest:i src1:i len:6 clob:1
371 shr_imm: dest:i src1:i len:6 clob:1
372 shr_un_imm: dest:i src1:i len:6 clob:1
374 cond_exc_ne_un: len:6
376 cond_exc_lt_un: len:6
378 cond_exc_gt_un: len:6
380 cond_exc_ge_un: len:6
382 cond_exc_le_un: len:6
397 long_shl: dest:L src1:L src2:i clob:s len:21
398 long_shr: dest:L src1:L src2:i clob:s len:22
399 long_shr_un: dest:L src1:L src2:i clob:s len:22
413 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
421 long_conv_to_ovf_i1_un:
422 long_conv_to_ovf_i2_un:
423 long_conv_to_ovf_i4_un:
424 long_conv_to_ovf_i8_un:
425 long_conv_to_ovf_u1_un:
426 long_conv_to_ovf_u2_un:
427 long_conv_to_ovf_u4_un:
428 long_conv_to_ovf_u8_un:
429 long_conv_to_ovf_i_un:
430 long_conv_to_ovf_u_un:
444 long_conv_to_r_un: dest:f src1:i src2:i len:37
446 long_shr_imm: dest:L src1:L len:10
447 long_shr_un_imm: dest:L src1:L len:10
448 long_shl_imm: dest:L src1:L len:10
471 float_add: dest:f src1:f src2:f len:2
472 float_sub: dest:f src1:f src2:f len:2
473 float_mul: dest:f src1:f src2:f len:2
474 float_div: dest:f src1:f src2:f len:2
475 float_div_un: dest:f src1:f src2:f len:2
476 float_rem: dest:f src1:f src2:f len:17
477 float_rem_un: dest:f src1:f src2:f len:17
478 float_neg: dest:f src1:f len:2
479 float_not: dest:f src1:f len:2
480 float_conv_to_i1: dest:i src1:f len:39
481 float_conv_to_i2: dest:i src1:f len:39
482 float_conv_to_i4: dest:i src1:f len:39
483 float_conv_to_i8: dest:L src1:f len:39
486 float_conv_to_u4: dest:i src1:f len:39
487 float_conv_to_u8: dest:L src1:f len:39
488 float_conv_to_u2: dest:i src1:f len:39
489 float_conv_to_u1: dest:i src1:f len:39
490 float_conv_to_i: dest:i src1:f len:39
491 float_conv_to_ovf_i: dest:a src1:f len:30
492 float_conv_to_ovd_u: dest:a src1:f len:30
499 float_conv_to_ovf_i1_un:
500 float_conv_to_ovf_i2_un:
501 float_conv_to_ovf_i4_un:
502 float_conv_to_ovf_i8_un:
503 float_conv_to_ovf_u1_un:
504 float_conv_to_ovf_u2_un:
505 float_conv_to_ovf_u4_un:
506 float_conv_to_ovf_u8_un:
507 float_conv_to_ovf_i_un:
508 float_conv_to_ovf_u_un:
509 float_conv_to_ovf_i1:
510 float_conv_to_ovf_u1:
511 float_conv_to_ovf_i2:
512 float_conv_to_ovf_u2:
513 float_conv_to_ovf_i4:
514 float_conv_to_ovf_u4:
515 float_conv_to_ovf_i8:
516 float_conv_to_ovf_u8:
517 float_ceq: dest:i src1:f src2:f len:25
518 float_cgt: dest:i src1:f src2:f len:25
519 float_cgt_un: dest:i src1:f src2:f len:37
520 float_clt: dest:i src1:f src2:f len:25
521 float_clt_un: dest:i src1:f src2:f len:32
522 float_conv_to_u: dest:i src1:f len:36
524 aot_const: dest:i len:5
525 x86_test_null: src1:i len:2
526 x86_compare_membase_reg: src1:b src2:i len:6
527 x86_compare_membase_imm: src1:b len:11
528 x86_compare_reg_membase: src1:i src2:b len:6
529 x86_inc_reg: dest:i src1:i clob:1 len:1
530 x86_inc_membase: src1:b len:6
531 x86_dec_reg: dest:i src1:i clob:1 len:1
532 x86_dec_membase: src1:b len:6
533 x86_add_membase_imm: src1:b len:11
534 x86_sub_membase_imm: src1:b len:11
535 x86_push: src1:i len:1
537 x86_push_membase: src1:b len:6
538 x86_push_obj: src1:b len:30
539 x86_lea: dest:i src1:i src2:i len:7
540 x86_lea_membase: dest:i src1:i len:10
541 x86_xchg: src1:i src2:i clob:x len:1
542 x86_fpop: src1:f len:2
543 x86_fp_load_i8: dest:f src1:b len:7
544 x86_fp_load_i4: dest:f src1:b len:7
545 x86_seteq_membase: src1:b len:7
546 x86_add_membase: dest:i src1:i src2:b clob:1 len:11
547 x86_sub_membase: dest:i src1:i src2:b clob:1 len:11
548 x86_mul_membase: dest:i src1:i src2:b clob:1 len:13
549 adc: dest:i src1:i src2:i len:2 clob:1
550 addcc: dest:i src1:i src2:i len:2 clob:1
551 subcc: dest:i src1:i src2:i len:2 clob:1
552 adc_imm: dest:i src1:i len:6 clob:1
553 sbb: dest:i src1:i src2:i len:2 clob:1
554 sbb_imm: dest:i src1:i len:6 clob:1
556 sin: dest:f src1:f len:6
557 cos: dest:f src1:f len:6
558 abs: dest:f src1:f len:2
559 tan: dest:f src1:f len:49
560 atan: dest:f src1:f len:8
561 sqrt: dest:f src1:f len:2
562 op_bigmul: len:2 dest:l src1:a src2:i
563 op_bigmul_un: len:2 dest:l src1:a src2:i
564 sext_i1: dest:i src1:i len:3
565 sext_i2: dest:i src1:i len:3