1 # mips cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant
3 # information about the cpu instructions that may be used by the regsiter
4 # allocator, the scheduler and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value.
8 # Specifiers are separated by white space.
9 # Here is a description of the specifiers valid for this file and their
12 # dest:register describes the destination register of an instruction
13 # src1:register describes the first source register of an instruction
14 # src2:register describes the second source register of an instruction
16 # register may have the following values:
18 # l integer register pair
19 # v v0 register (output from calls)
20 # V v0/v1 register pair (output from calls)
22 # b base register (used in address references)
23 # f floating point register (pair - always)
24 # g floating point register return pair (f0/f1)
26 # len:number describe the maximun length in bytes of the instruction
27 # number is a positive integer
29 # cost:number describe how many cycles are needed to complete the instruction (unused)
31 # clob:spec describe if the instruction clobbers registers or has special needs
33 # spec can be one of the following characters:
34 # c clobbers caller-save registers
35 # r 'reserves' the destination register until a later instruction unreserves it
36 # used mostly to set output registers in function calls
38 # flags:spec describe if the instruction uses or sets the flags (unused)
40 # spec can be one of the following chars:
43 # m uses and modifies the flags
45 # res:spec describe what units are used in the processor (unused)
47 # delay: describe delay slots (unused)
49 # the required specifiers are: len, clob (if registers are clobbered), the registers
50 # specifiers if the registers are actually used, flags (when scheduling is implemented).
52 # See the code in mini-x86.c for more details on how the specifiers are used.
58 call: dest:v clob:c len:20
59 calli: dest:v clob:c len:20
88 ldind.i1: dest:i len:8
89 ldind.u1: dest:i len:8
90 ldind.i2: dest:i len:8
91 ldind.u2: dest:i len:8
92 ldind.i4: dest:i len:8
93 ldind.u4: dest:i len:8
95 ldind.ref: dest:i len:8
96 stind.ref: src1:b src2:i
97 stind.i1: src1:b src2:i
98 stind.i2: src1:b src2:i
99 stind.i4: src1:b src2:i
100 stind.r4: src1:b src2:f
101 stind.r8: src1:b src2:f
102 add: dest:i src1:i src2:i len:4
103 sub: dest:i src1:i src2:i len:4
104 mul: dest:i src1:i src2:i len:20
105 div: dest:i src1:i src2:i len:76
106 div.un: dest:i src1:i src2:i len:76
107 rem: dest:i src1:i src2:i len:76
108 rem.un: dest:i src1:i src2:i len:76
109 and: dest:i src1:i src2:i len:4
110 or: dest:i src1:i src2:i len:4
111 xor: dest:i src1:i src2:i len:4
112 shl: dest:i src1:i src2:i len:4
113 shr: dest:i src1:i src2:i len:4
114 shr.un: dest:i src1:i src2:i len:4
115 neg: dest:i src1:i len:4
116 not: dest:i src1:i len:4
117 conv.i1: dest:i src1:i len:8
118 conv.i2: dest:i src1:i len:8
119 conv.i4: dest:i src1:i len:4
120 conv.r4: dest:f src1:i len:36
121 conv.r8: dest:f src1:i len:36
122 conv.u4: dest:i src1:i
123 callvirt: dest:v clob:c len:20
124 conv.r.un: dest:f src1:i len:32
126 rethrow: src1:i len:24
127 ckfinite: dest:f src1:f len:24
128 conv.u2: dest:i src1:i len:8
129 conv.u1: dest:i src1:i len:4
130 conv.i: dest:i src1:i len:4
131 add.ovf: dest:i src1:i src2:i len:64
132 add.ovf.un: dest:i src1:i src2:i len:64
133 mul.ovf: dest:i src1:i src2:i len:64
134 # this opcode is handled specially in the code generator
135 mul.ovf.un: dest:i src1:i src2:i len:64
136 sub.ovf: dest:i src1:i src2:i len:64
137 sub.ovf.un: dest:i src1:i src2:i len:64
138 add_ovf_carry: dest:i src1:i src2:i len:64
139 sub_ovf_carry: dest:i src1:i src2:i len:64
140 add_ovf_un_carry: dest:i src1:i src2:i len:64
141 sub_ovf_un_carry: dest:i src1:i src2:i len:64
142 start_handler: len:16
144 conv.u: dest:i src1:i len:4
147 cgt.un: dest:i len:16
149 clt.un: dest:i len:16
150 localloc: dest:i src1:i len:60
152 compare: src1:i src2:i len:20
153 compare_imm: src1:i len:20
154 fcompare: src1:f src2:f len:12
155 oparglist: src1:i len:12
158 setret: dest:v src1:i len:4
159 setlret: src1:i src2:i len:12
160 setreg: dest:i src1:i len:8 clob:r
161 setregimm: dest:i len:8 clob:r
162 setfreg: dest:f src1:f len:8 clob:r
163 checkthis: src1:b len:4
164 voidcall: len:20 clob:c
165 voidcall_reg: src1:i len:20 clob:c
166 voidcall_membase: src1:b len:20 clob:c
167 fcall: dest:g len:20 clob:c
168 fcall_reg: dest:g src1:i len:20 clob:c
169 fcall_membase: dest:g src1:b len:20 clob:c
170 lcall: dest:V len:28 clob:c
171 lcall_reg: dest:V src1:i len:28 clob:c
172 lcall_membase: dest:V src1:b len:28 clob:c
174 vcall_reg: src1:i len:20 clob:c
175 vcall_membase: src1:b len:20 clob:c
176 call_reg: dest:v src1:i len:20 clob:c
177 call_membase: dest:v src1:b len:20 clob:c
178 iconst: dest:i len:12
179 r4const: dest:f len:20
180 r8const: dest:f len:28
182 store_membase_imm: dest:b len:20
183 store_membase_reg: dest:b src1:i len:16
184 storei1_membase_imm: dest:b len:20
185 storei1_membase_reg: dest:b src1:i len:16
186 storei2_membase_imm: dest:b len:20
187 storei2_membase_reg: dest:b src1:i len:16
188 storei4_membase_imm: dest:b len:20
189 storei4_membase_reg: dest:b src1:i len:16
190 storei8_membase_imm: dest:b
191 storei8_membase_reg: dest:b src1:i
192 storer4_membase_reg: dest:b src1:f len:16
193 storer8_membase_reg: dest:b src1:f len:16
194 load_membase: dest:i src1:b len:16
195 loadi1_membase: dest:i src1:b len:16
196 loadu1_membase: dest:i src1:b len:16
197 loadi2_membase: dest:i src1:b len:16
198 loadu2_membase: dest:i src1:b len:16
199 loadi4_membase: dest:i src1:b len:16
200 loadu4_membase: dest:i src1:b len:16
201 loadi8_membase: dest:i src1:b
202 loadr4_membase: dest:f src1:b len:16
203 loadr8_membase: dest:f src1:b len:16
204 loadu4_mem: dest:i len:8
205 move: dest:i src1:i len:4
206 fmove: dest:f src1:f len:8
207 add_imm: dest:i src1:i len:12
208 sub_imm: dest:i src1:i len:12
209 mul_imm: dest:i src1:i len:20
210 # there is no actual support for division or reminder by immediate
211 # we simulate them, though (but we need to change the burg rules
212 # to allocate a symbolic reg for src2)
213 div_imm: dest:i src1:i src2:i len:20
214 div_un_imm: dest:i src1:i src2:i len:12
215 rem_imm: dest:i src1:i src2:i len:28
216 rem_un_imm: dest:i src1:i src2:i len:16
217 and_imm: dest:i src1:i len:12
218 or_imm: dest:i src1:i len:12
219 xor_imm: dest:i src1:i len:12
220 shl_imm: dest:i src1:i len:8
221 shr_imm: dest:i src1:i len:8
222 shr_un_imm: dest:i src1:i len:8
224 cond_exc_ne_un: len:32
226 cond_exc_lt_un: len:32
228 cond_exc_gt_un: len:32
230 cond_exc_ge_un: len:32
232 cond_exc_le_un: len:32
237 long_conv_to_i1: dest:i src1:l len:32
238 long_conv_to_i2: dest:i src1:l len:32
239 long_conv_to_i4: dest:i src1:l len:32
240 long_conv_to_r4: dest:f src1:l len:32
241 long_conv_to_r8: dest:f src1:l len:32
242 long_conv_to_u4: dest:i src1:l len:32
243 long_conv_to_u8: dest:l src1:l len:32
244 long_conv_to_u2: dest:i src1:l len:32
245 long_conv_to_u1: dest:i src1:l len:32
246 long_conv_to_i: dest:i src1:l len:32
247 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
249 long_conv_to_r_un: dest:f src1:i src2:i len:37
250 float_beq: src1:f src2:f len:16
251 float_bne_un: src1:f src2:f len:16
252 float_blt: src1:f src2:f len:16
253 float_blt_un: src1:f src2:f len:16
254 float_bgt: src1:f src2:f len:16
255 float_btg_un: src1:f src2:f len:16
256 float_bge: src1:f src2:f len:16
257 float_bge_un: src1:f src2:f len:16
258 float_ble: src1:f src2:f len:16
259 float_ble_un: src1:f src2:f len:16
260 float_add: dest:f src1:f src2:f len:4
261 float_sub: dest:f src1:f src2:f len:4
262 float_mul: dest:f src1:f src2:f len:4
263 float_div: dest:f src1:f src2:f len:4
264 float_div_un: dest:f src1:f src2:f len:4
265 float_rem: dest:f src1:f src2:f len:16
266 float_rem_un: dest:f src1:f src2:f len:16
267 float_neg: dest:f src1:f len:4
268 float_not: dest:f src1:f len:4
269 float_conv_to_i1: dest:i src1:f len:40
270 float_conv_to_i2: dest:i src1:f len:40
271 float_conv_to_i4: dest:i src1:f len:40
272 float_conv_to_i8: dest:l src1:f len:40
273 float_conv_to_r4: dest:f src1:f len:8
274 float_conv_to_u4: dest:i src1:f len:40
275 float_conv_to_u8: dest:l src1:f len:40
276 float_conv_to_u2: dest:i src1:f len:40
277 float_conv_to_u1: dest:i src1:f len:40
278 float_conv_to_i: dest:i src1:f len:40
279 float_ceq: dest:i src1:f src2:f len:20
280 float_cgt: dest:i src1:f src2:f len:20
281 float_cgt_un: dest:i src1:f src2:f len:20
282 float_clt: dest:i src1:f src2:f len:20
283 float_clt_un: dest:i src1:f src2:f len:20
284 float_conv_to_u: dest:i src1:f len:36
286 endfilter: src1:i len:16
287 aot_const: dest:i len:8
288 sqrt: dest:f src1:f len:4
289 adc: dest:i src1:i src2:i len:4
290 addcc: dest:i src1:i src2:i len:4
291 subcc: dest:i src1:i src2:i len:4
292 adc_imm: dest:i src1:i len:12
293 addcc_imm: dest:i src1:i len:12
294 subcc_imm: dest:i src1:i len:12
295 sbb: dest:i src1:i src2:i len:4
296 sbb_imm: dest:i src1:i len:12
298 #ppc_subfic: dest:i src1:i len:4
299 #ppc_subfze: dest:i src1:i len:4
300 bigmul: len:52 dest:l src1:i src2:i
301 bigmul_un: len:52 dest:l src1:i src2:i
302 tls_get: len:8 dest:i
303 mips_beq: src1:i src2:i len:24
304 mips_bgez: src1:i len:24
305 mips_bgtz: src1:i len:24
306 mips_blez: src1:i len:24
307 mips_bltz: src1:i len:24
308 mips_bne: src1:i src2:i len:24
309 mips_cvtsd: dest:f src1:f len:8
310 mips_fbeq: src1:f src2:f len:16
311 mips_fbge: src1:f src2:f len:16
312 mips_fbgt: src1:f src2:f len:16
313 mips_fble: src1:f src2:f len:16
314 mips_fblt: src1:f src2:f len:16
315 mips_fbne: src1:f src2:f len:16
316 mips_lwc1: dest:f src1:b len:16
317 mips_mtc1_s: dest:f src1:i len:8
318 mips_mfc1_s: dest:i src1:f len:8
319 mips_mtc1_d: dest:f src1:i len:8
320 mips_mfc1_d: dest:i src1:f len:8
321 mips_slti: dest:i src1:i len:4
322 mips_slt: dest:i src1:i src2:i len:4
323 mips_sltiu: dest:i src1:i len:4
324 mips_sltu: dest:i src1:i src2:i len:4
325 mips_xori: dest:i src1:i len:4
326 mips_cond_exc_eq: src1:i src2:i len:40
327 mips_cond_exc_ge: src1:i src2:i len:40
328 mips_cond_exc_gt: src1:i src2:i len:40
329 mips_cond_exc_le: src1:i src2:i len:40
330 mips_cond_exc_lt: src1:i src2:i len:40
331 mips_cond_exc_ne_un: src1:i src2:i len:40
332 mips_cond_exc_ge_un: src1:i src2:i len:40
333 mips_cond_exc_gt_un: src1:i src2:i len:40
334 mips_cond_exc_le_un: src1:i src2:i len:40
335 mips_cond_exc_lt_un: src1:i src2:i len:40
336 mips_cond_exc_ov: src1:i src2:i len:40
337 mips_cond_exc_no: src1:i src2:i len:40
338 mips_cond_exc_c: src1:i src2:i len:40
339 mips_cond_exc_nc: src1:i src2:i len:40
340 mips_cond_exc_ieq: src1:i src2:i len:40
341 mips_cond_exc_ige: src1:i src2:i len:40
342 mips_cond_exc_igt: src1:i src2:i len:40
343 mips_cond_exc_ile: src1:i src2:i len:40
344 mips_cond_exc_ilt: src1:i src2:i len:40
345 mips_cond_exc_ine_un: src1:i src2:i len:40
346 mips_cond_exc_ige_un: src1:i src2:i len:40
347 mips_cond_exc_igt_un: src1:i src2:i len:40
348 mips_cond_exc_ile_un: src1:i src2:i len:40
349 mips_cond_exc_ilt_un: src1:i src2:i len:40
350 mips_cond_exc_iov: src1:i src2:i len:40
351 mips_cond_exc_ino: src1:i src2:i len:40
352 mips_cond_exc_ic: src1:i src2:i len:40
353 mips_cond_exc_inc: src1:i src2:i len:40