1 # mips cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant
3 # information about the cpu instructions that may be used by the regsiter
4 # allocator, the scheduler and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value.
8 # Specifiers are separated by white space.
9 # Here is a description of the specifiers valid for this file and their
12 # dest:register describes the destination register of an instruction
13 # src1:register describes the first source register of an instruction
14 # src2:register describes the second source register of an instruction
16 # register may have the following values:
18 # l integer register pair
19 # v v0 register (output from calls)
20 # V v0/v1 register pair (output from calls)
22 # b base register (used in address references)
23 # f floating point register (pair - always)
24 # g floating point register return pair (f0/f1)
26 # len:number describe the maximun length in bytes of the instruction
27 # number is a positive integer
29 # cost:number describe how many cycles are needed to complete the instruction (unused)
31 # clob:spec describe if the instruction clobbers registers or has special needs
33 # spec can be one of the following characters:
34 # c clobbers caller-save registers
35 # r 'reserves' the destination register until a later instruction unreserves it
36 # used mostly to set output registers in function calls
38 # flags:spec describe if the instruction uses or sets the flags (unused)
40 # spec can be one of the following chars:
43 # m uses and modifies the flags
45 # res:spec describe what units are used in the processor (unused)
47 # delay: describe delay slots (unused)
49 # the required specifiers are: len, clob (if registers are clobbered), the registers
50 # specifiers if the registers are actually used, flags (when scheduling is implemented).
52 # See the code in mini-x86.c for more details on how the specifiers are used.
94 call: dest:v clob:c len:20
95 calli: dest:v clob:c len:20
123 switch: src1:i len:40
124 ldind.i1: dest:i len:8
125 ldind.u1: dest:i len:8
126 ldind.i2: dest:i len:8
127 ldind.u2: dest:i len:8
128 ldind.i4: dest:i len:8
129 ldind.u4: dest:i len:8
131 ldind.i: dest:i len:8
134 ldind.ref: dest:i len:8
135 stind.ref: src1:b src2:i
136 stind.i1: src1:b src2:i
137 stind.i2: src1:b src2:i
138 stind.i4: src1:b src2:i
140 stind.r4: src1:b src2:f
141 stind.r8: src1:b src2:f
142 add: dest:i src1:i src2:i len:4
143 sub: dest:i src1:i src2:i len:4
144 mul: dest:i src1:i src2:i len:20
145 div: dest:i src1:i src2:i len:76
146 div.un: dest:i src1:i src2:i len:76
147 rem: dest:i src1:i src2:i len:76
148 rem.un: dest:i src1:i src2:i len:76
149 and: dest:i src1:i src2:i len:4
150 or: dest:i src1:i src2:i len:4
151 xor: dest:i src1:i src2:i len:4
152 shl: dest:i src1:i src2:i len:4
153 shr: dest:i src1:i src2:i len:4
154 shr.un: dest:i src1:i src2:i len:4
155 neg: dest:i src1:i len:4
156 not: dest:i src1:i len:4
157 conv.i1: dest:i src1:i len:8
158 conv.i2: dest:i src1:i len:8
159 conv.i4: dest:i src1:i len:4
161 conv.r4: dest:f src1:i len:36
162 conv.r8: dest:f src1:i len:36
163 conv.u4: dest:i src1:i
165 callvirt: dest:v clob:c len:20
172 conv.r.un: dest:f src1:i len:32
175 op_rethrow: src1:i len:24
225 ckfinite: dest:f src1:f len:24
228 conv.u2: dest:i src1:i len:8
229 conv.u1: dest:i src1:i len:4
230 conv.i: dest:i src1:i len:4
233 add.ovf: dest:i src1:i src2:i len:64
234 add.ovf.un: dest:i src1:i src2:i len:64
235 mul.ovf: dest:i src1:i src2:i len:64
236 # this opcode is handled specially in the code generator
237 mul.ovf.un: dest:i src1:i src2:i len:64
238 sub.ovf: dest:i src1:i src2:i len:64
239 sub.ovf.un: dest:i src1:i src2:i len:64
240 add_ovf_carry: dest:i src1:i src2:i len:64
241 sub_ovf_carry: dest:i src1:i src2:i len:64
242 add_ovf_un_carry: dest:i src1:i src2:i len:64
243 sub_ovf_un_carry: dest:i src1:i src2:i len:64
244 start_handler: len:16
249 conv.u: dest:i src1:i len:4
261 cgt.un: dest:i len:16
263 clt.un: dest:i len:16
272 localloc: dest:i src1:i len:60
295 compare: src1:i src2:i len:20
296 compare_imm: src1:i len:20
297 fcompare: src1:f src2:f len:12
301 oparglist: src1:i len:12
305 setret: dest:v src1:i len:4
306 setlret: src1:i src2:i len:12
307 setreg: dest:i src1:i len:8 clob:r
308 setregimm: dest:i len:8 clob:r
309 setfreg: dest:f src1:f len:8 clob:r
310 checkthis: src1:b len:4
311 voidcall: len:20 clob:c
312 voidcall_reg: src1:i len:20 clob:c
313 voidcall_membase: src1:b len:20 clob:c
314 fcall: dest:g len:20 clob:c
315 fcall_reg: dest:g src1:i len:20 clob:c
316 fcall_membase: dest:g src1:b len:20 clob:c
317 lcall: dest:V len:28 clob:c
318 lcall_reg: dest:V src1:i len:28 clob:c
319 lcall_membase: dest:V src1:b len:28 clob:c
321 vcall_reg: src1:i len:20 clob:c
322 vcall_membase: src1:b len:20 clob:c
323 call_reg: dest:v src1:i len:20 clob:c
324 call_membase: dest:v src1:b len:20 clob:c
326 iconst: dest:i len:12
328 r4const: dest:f len:20
329 r8const: dest:f len:28
334 store_membase_imm: dest:b len:20
335 store_membase_reg: dest:b src1:i len:16
336 storei1_membase_imm: dest:b len:20
337 storei1_membase_reg: dest:b src1:i len:16
338 storei2_membase_imm: dest:b len:20
339 storei2_membase_reg: dest:b src1:i len:16
340 storei4_membase_imm: dest:b len:20
341 storei4_membase_reg: dest:b src1:i len:16
342 storei8_membase_imm: dest:b
343 storei8_membase_reg: dest:b src1:i
344 storer4_membase_reg: dest:b src1:f len:16
345 storer8_membase_reg: dest:b src1:f len:16
346 load_membase: dest:i src1:b len:16
347 loadi1_membase: dest:i src1:b len:16
348 loadu1_membase: dest:i src1:b len:16
349 loadi2_membase: dest:i src1:b len:16
350 loadu2_membase: dest:i src1:b len:16
351 loadi4_membase: dest:i src1:b len:16
352 loadu4_membase: dest:i src1:b len:16
353 loadi8_membase: dest:i src1:b
354 loadr4_membase: dest:f src1:b len:16
355 loadr8_membase: dest:f src1:b len:16
356 loadu4_mem: dest:i len:8
357 move: dest:i src1:i len:4
358 fmove: dest:f src1:f len:8
359 add_imm: dest:i src1:i len:12
360 sub_imm: dest:i src1:i len:12
361 mul_imm: dest:i src1:i len:20
362 # there is no actual support for division or reminder by immediate
363 # we simulate them, though (but we need to change the burg rules
364 # to allocate a symbolic reg for src2)
365 div_imm: dest:i src1:i src2:i len:20
366 div_un_imm: dest:i src1:i src2:i len:12
367 rem_imm: dest:i src1:i src2:i len:28
368 rem_un_imm: dest:i src1:i src2:i len:16
369 and_imm: dest:i src1:i len:12
370 or_imm: dest:i src1:i len:12
371 xor_imm: dest:i src1:i len:12
372 shl_imm: dest:i src1:i len:8
373 shr_imm: dest:i src1:i len:8
374 shr_un_imm: dest:i src1:i len:8
376 cond_exc_ne_un: len:32
378 cond_exc_lt_un: len:32
380 cond_exc_gt_un: len:32
382 cond_exc_ge_un: len:32
384 cond_exc_le_un: len:32
404 long_conv_to_i1: dest:i src1:l len:32
405 long_conv_to_i2: dest:i src1:l len:32
406 long_conv_to_i4: dest:i src1:l len:32
408 long_conv_to_r4: dest:f src1:l len:32
409 long_conv_to_r8: dest:f src1:l len:32
410 long_conv_to_u4: dest:i src1:l len:32
411 long_conv_to_u8: dest:l src1:l len:32
412 long_conv_to_u2: dest:i src1:l len:32
413 long_conv_to_u1: dest:i src1:l len:32
414 long_conv_to_i: dest:i src1:l len:32
415 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
423 long_conv_to_ovf_i1_un:
424 long_conv_to_ovf_i2_un:
425 long_conv_to_ovf_i4_un:
426 long_conv_to_ovf_i8_un:
427 long_conv_to_ovf_u1_un:
428 long_conv_to_ovf_u2_un:
429 long_conv_to_ovf_u4_un:
430 long_conv_to_ovf_u8_un:
431 long_conv_to_ovf_i_un:
432 long_conv_to_ovf_u_un:
446 long_conv_to_r_un: dest:f src1:i src2:i len:37
463 float_beq: src1:f src2:f len:16
464 float_bne_un: src1:f src2:f len:16
465 float_blt: src1:f src2:f len:16
466 float_blt_un: src1:f src2:f len:16
467 float_bgt: src1:f src2:f len:16
468 float_btg_un: src1:f src2:f len:16
469 float_bge: src1:f src2:f len:16
470 float_bge_un: src1:f src2:f len:16
471 float_ble: src1:f src2:f len:16
472 float_ble_un: src1:f src2:f len:16
473 float_add: dest:f src1:f src2:f len:4
474 float_sub: dest:f src1:f src2:f len:4
475 float_mul: dest:f src1:f src2:f len:4
476 float_div: dest:f src1:f src2:f len:4
477 float_div_un: dest:f src1:f src2:f len:4
478 float_rem: dest:f src1:f src2:f len:16
479 float_rem_un: dest:f src1:f src2:f len:16
480 float_neg: dest:f src1:f len:4
481 float_not: dest:f src1:f len:4
482 float_conv_to_i1: dest:i src1:f len:40
483 float_conv_to_i2: dest:i src1:f len:40
484 float_conv_to_i4: dest:i src1:f len:40
485 float_conv_to_i8: dest:l src1:f len:40
486 float_conv_to_r4: dest:f src1:f len:8
488 float_conv_to_u4: dest:i src1:f len:40
489 float_conv_to_u8: dest:l src1:f len:40
490 float_conv_to_u2: dest:i src1:f len:40
491 float_conv_to_u1: dest:i src1:f len:40
492 float_conv_to_i: dest:i src1:f len:40
501 float_conv_to_ovf_i1_un:
502 float_conv_to_ovf_i2_un:
503 float_conv_to_ovf_i4_un:
504 float_conv_to_ovf_i8_un:
505 float_conv_to_ovf_u1_un:
506 float_conv_to_ovf_u2_un:
507 float_conv_to_ovf_u4_un:
508 float_conv_to_ovf_u8_un:
509 float_conv_to_ovf_i_un:
510 float_conv_to_ovf_u_un:
511 float_conv_to_ovf_i1:
512 float_conv_to_ovf_u1:
513 float_conv_to_ovf_i2:
514 float_conv_to_ovf_u2:
515 float_conv_to_ovf_i4:
516 float_conv_to_ovf_u4:
517 float_conv_to_ovf_i8:
518 float_conv_to_ovf_u8:
519 float_ceq: dest:i src1:f src2:f len:20
520 float_cgt: dest:i src1:f src2:f len:20
521 float_cgt_un: dest:i src1:f src2:f len:20
522 float_clt: dest:i src1:f src2:f len:20
523 float_clt_un: dest:i src1:f src2:f len:20
524 float_conv_to_u: dest:i src1:f len:36
526 op_endfilter: src1:i len:16
527 aot_const: dest:i len:8
528 sqrt: dest:f src1:f len:4
529 adc: dest:i src1:i src2:i len:4
530 addcc: dest:i src1:i src2:i len:4
531 subcc: dest:i src1:i src2:i len:4
532 adc_imm: dest:i src1:i len:12
533 addcc_imm: dest:i src1:i len:12
534 subcc_imm: dest:i src1:i len:12
535 sbb: dest:i src1:i src2:i len:4
536 sbb_imm: dest:i src1:i len:12
538 #ppc_subfic: dest:i src1:i len:4
539 #ppc_subfze: dest:i src1:i len:4
540 op_bigmul: len:52 dest:l src1:i src2:i
541 op_bigmul_un: len:52 dest:l src1:i src2:i
542 tls_get: len:8 dest:i
543 mips_beq: src1:i src2:i len:24
544 mips_bgez: src1:i len:24
545 mips_bgtz: src1:i len:24
546 mips_blez: src1:i len:24
547 mips_bltz: src1:i len:24
548 mips_bne: src1:i src2:i len:24
549 mips_cvtsd: dest:f src1:f len:8
550 mips_fbeq: src1:f src2:f len:16
551 mips_fbge: src1:f src2:f len:16
552 mips_fbgt: src1:f src2:f len:16
553 mips_fble: src1:f src2:f len:16
554 mips_fblt: src1:f src2:f len:16
555 mips_fbne: src1:f src2:f len:16
556 mips_lwc1: dest:f src1:b len:16
557 mips_mtc1_s: dest:f src1:i len:8
558 mips_mfc1_s: dest:i src1:f len:8
559 mips_mtc1_d: dest:f src1:i len:8
560 mips_mfc1_d: dest:i src1:f len:8
561 mips_slti: dest:i src1:i len:4
562 mips_slt: dest:i src1:i src2:i len:4
563 mips_sltiu: dest:i src1:i len:4
564 mips_sltu: dest:i src1:i src2:i len:4
565 mips_xori: dest:i src1:i len:4
566 mips_cond_exc_eq: src1:i src2:i len:40
567 mips_cond_exc_ge: src1:i src2:i len:40
568 mips_cond_exc_gt: src1:i src2:i len:40
569 mips_cond_exc_le: src1:i src2:i len:40
570 mips_cond_exc_lt: src1:i src2:i len:40
571 mips_cond_exc_ne_un: src1:i src2:i len:40
572 mips_cond_exc_ge_un: src1:i src2:i len:40
573 mips_cond_exc_gt_un: src1:i src2:i len:40
574 mips_cond_exc_le_un: src1:i src2:i len:40
575 mips_cond_exc_lt_un: src1:i src2:i len:40
576 mips_cond_exc_ov: src1:i src2:i len:40
577 mips_cond_exc_no: src1:i src2:i len:40
578 mips_cond_exc_c: src1:i src2:i len:40
579 mips_cond_exc_nc: src1:i src2:i len:40
580 mips_cond_exc_ieq: src1:i src2:i len:40
581 mips_cond_exc_ige: src1:i src2:i len:40
582 mips_cond_exc_igt: src1:i src2:i len:40
583 mips_cond_exc_ile: src1:i src2:i len:40
584 mips_cond_exc_ilt: src1:i src2:i len:40
585 mips_cond_exc_ine_un: src1:i src2:i len:40
586 mips_cond_exc_ige_un: src1:i src2:i len:40
587 mips_cond_exc_igt_un: src1:i src2:i len:40
588 mips_cond_exc_ile_un: src1:i src2:i len:40
589 mips_cond_exc_ilt_un: src1:i src2:i len:40
590 mips_cond_exc_iov: src1:i src2:i len:40
591 mips_cond_exc_ino: src1:i src2:i len:40
592 mips_cond_exc_ic: src1:i src2:i len:40
593 mips_cond_exc_inc: src1:i src2:i len:40