1 # ia64 cpu description file
3 # The instruction lengths are very conservative, it doesn't matter on ia64
4 # since there are no short branches.
27 add: dest:i src1:i src2:i len:48
28 sub: dest:i src1:i src2:i len:48
29 mul: dest:i src1:i src2:i len:48
30 div: dest:a src1:a src2:i len:48 clob:d
31 div.un: dest:a src1:a src2:i len:48 clob:d
32 rem: dest:d src1:a src2:i len:48 clob:a
33 rem.un: dest:d src1:a src2:i len:48 clob:a
34 and: dest:i src1:i src2:i len:48
35 or: dest:i src1:i src2:i len:48
36 xor: dest:i src1:i src2:i len:48
37 shl: dest:i src1:i src2:s len:48
38 shr: dest:i src1:i src2:s len:48
39 shr.un: dest:i src1:i src2:s len:48
40 neg: dest:i src1:i len:48
41 not: dest:i src1:i len:48
42 conv.i1: dest:i src1:i len:48
43 conv.i2: dest:i src1:i len:48
44 conv.i4: dest:i src1:i len:48
45 conv.i8: dest:i src1:i len:48
46 conv.r4: dest:f src1:i len:112
47 conv.r8: dest:f src1:i len:112
48 conv.u4: dest:i src1:i len:112
49 conv.u8: dest:i src1:i len:112
56 conv.r.un: dest:f src1:i len:48
59 op_rethrow: src1:i len:48
69 conv.ovf.i4.un: dest:i src1:i len:48
105 conv.ovf.u4: dest:i src1:i len:48
109 ckfinite: dest:f src1:f len:48
112 conv.u2: dest:i src1:i len:48
113 conv.u1: dest:i src1:i len:48
114 conv.i: dest:i src1:i len:48
119 mul.ovf: dest:i src1:i src2:i len:48
120 # this opcode is handled specially in the code generator
121 mul.ovf.un: dest:i src1:i src2:i len:48
128 conv.u: dest:i src1:i len:48
140 cgt.un: dest:c len:48
142 clt.un: dest:c len:48
151 localloc: dest:i src1:i len:48
173 compare: src1:i src2:i len:48
174 lcompare: src1:i src2:i len:48
175 icompare: src1:i src2:i len:48
176 compare_imm: src1:i len:48
177 icompare_imm: src1:i len:48
178 fcompare: src1:f src2:f clob:a len:48
181 oparglist: src1:b len:48
182 outarg: src1:i len:48
185 setret: dest:r src1:i len:48
186 setlret: dest:r src1:i src2:i len:48
187 checkthis: src1:b len:48
188 call: dest:r clob:c len:80
189 voidcall: clob:c len:80
190 voidcall_reg: src1:i clob:c len:80
191 voidcall_membase: src1:b clob:c len:80
192 fcall: dest:g len:80 clob:c
193 fcall_reg: dest:g src1:i len:80 clob:c
194 fcall_membase: dest:g src1:b len:80 clob:c
195 lcall: dest:r len:80 clob:c
196 lcall_reg: dest:r src1:i len:80 clob:c
197 lcall_membase: dest:r src1:b len:80 clob:c
199 vcall_reg: src1:i len:80 clob:c
200 vcall_membase: src1:b len:80 clob:c
201 call_reg: dest:r src1:i len:80 clob:c
202 call_membase: dest:r src1:b len:80 clob:c
203 iconst: dest:i len:48
204 i8const: dest:i len:48
205 r4const: dest:f len:48
206 r8const: dest:f len:48
208 store_membase_imm: dest:b len:48
209 store_membase_reg: dest:b src1:i len:48
210 storei8_membase_reg: dest:b src1:i len:48
211 storei1_membase_imm: dest:b len:48
212 storei1_membase_reg: dest:b src1:c len:48
213 storei2_membase_imm: dest:b len:48
214 storei2_membase_reg: dest:b src1:i len:48
215 storei4_membase_imm: dest:b len:48
216 storei4_membase_reg: dest:b src1:i len:48
217 storei8_membase_imm: dest:b len:48
218 storer4_membase_reg: dest:b src1:f len:48
219 storer8_membase_reg: dest:b src1:f len:48
220 load_membase: dest:i src1:b len:48
221 loadi1_membase: dest:c src1:b len:48
222 loadu1_membase: dest:c src1:b len:48
223 loadi2_membase: dest:i src1:b len:48
224 loadu2_membase: dest:i src1:b len:48
225 loadi4_membase: dest:i src1:b len:48
226 loadu4_membase: dest:i src1:b len:48
227 loadi8_membase: dest:i src1:b len:48
228 loadr4_membase: dest:f src1:b len:48
229 loadr8_membase: dest:f src1:b len:48
230 loadr8_spill_membase: src1:b len:48
231 loadu4_mem: dest:i len:48
232 move: dest:i src1:i len:48
233 setreg: dest:i src1:i len:48
234 add_imm: dest:i src1:i len:48
235 sub_imm: dest:i src1:i len:48
236 mul_imm: dest:i src1:i len:48
237 # there is no actual support for division or reminder by immediate
238 # we simulate them, though (but we need to change the burg rules
239 # to allocate a symbolic reg for src2)
240 div_imm: dest:a src1:i src2:i len:48 clob:d
241 div_un_imm: dest:a src1:i src2:i len:48 clob:d
242 rem_imm: dest:d src1:i src2:i len:48 clob:a
243 rem_un_imm: dest:d src1:i src2:i len:48 clob:a
244 and_imm: dest:i src1:i len:48
245 or_imm: dest:i src1:i len:48
246 xor_imm: dest:i src1:i len:48
247 shl_imm: dest:i src1:i len:48
248 shr_imm: dest:i src1:i len:48
249 shr_un_imm: dest:i src1:i len:48
251 cond_exc_ne_un: len:48
253 cond_exc_lt_un: len:48
255 cond_exc_gt_un: len:48
257 cond_exc_ge_un: len:48
259 cond_exc_le_un: len:48
266 long_mul: dest:i src1:i src2:i len:48
267 long_mul_imm: dest:i src1:i src2:i len:48
268 long_div: dest:a src1:a src2:i len:48 clob:d
269 long_div_un: dest:a src1:a src2:i len:48 clob:d
270 long_rem: dest:d src1:a src2:i len:48 clob:a
271 long_rem_un: dest:d src1:a src2:i len:48 clob:a
272 long_shl: dest:i src1:i src2:s len:48
273 long_shr: dest:i src1:i src2:s len:48
274 long_shr_un: dest:i src1:i src2:s len:48
275 long_conv_to_r4: dest:f src1:i len:48
276 long_conv_to_r8: dest:f src1:i len:48
277 long_conv_to_ovf_i: dest:i src1:i src2:i len:48
278 long_mul_ovf: dest:i src1:i src2:i len:48
279 long_mul_ovf_un: dest:i src1:i src2:i len:48
285 long_conv_to_r_un: dest:f src1:i src2:i len:48
287 long_shr_imm: dest:i src1:i len:48
288 long_shr_un_imm: dest:i src1:i len:48
289 long_shl_imm: dest:i src1:i len:48
310 float_add: dest:f src1:f src2:f len:48
311 float_sub: dest:f src1:f src2:f len:48
312 float_mul: dest:f src1:f src2:f len:48
313 float_div: dest:f src1:f src2:f len:48
314 float_div_un: dest:f src1:f src2:f len:48
315 float_rem: dest:f src1:f src2:f len:48
316 float_rem_un: dest:f src1:f src2:f len:48
317 float_neg: dest:f src1:f len:48
318 float_not: dest:f src1:f len:48
319 float_conv_to_i1: dest:i src1:f len:112
320 float_conv_to_i2: dest:i src1:f len:112
321 float_conv_to_i4: dest:i src1:f len:112
322 float_conv_to_i8: dest:i src1:f len:112
323 float_conv_to_r4: dest:f src1:f len:112
324 float_conv_to_r8: dest:f src1:f len:112
325 float_conv_to_u4: dest:i src1:f len:112
326 float_conv_to_u8: dest:i src1:f len:112
327 float_conv_to_u2: dest:i src1:f len:112
328 float_conv_to_u1: dest:i src1:f len:112
329 float_conv_to_i: dest:i src1:f len:112
330 float_conv_to_ovf_i: dest:a src1:f len:112
331 float_conv_to_ovd_u: dest:a src1:f len:112
338 float_conv_to_ovf_i1_un:
339 float_conv_to_ovf_i2_un:
340 float_conv_to_ovf_i4_un:
341 float_conv_to_ovf_i8_un:
342 float_conv_to_ovf_u1_un:
343 float_conv_to_ovf_u2_un:
344 float_conv_to_ovf_u4_un:
345 float_conv_to_ovf_u8_un:
346 float_conv_to_ovf_i_un:
347 float_conv_to_ovf_u_un:
348 float_conv_to_ovf_i1:
349 float_conv_to_ovf_u1:
350 float_conv_to_ovf_i2:
351 float_conv_to_ovf_u2:
352 float_conv_to_ovf_i4:
353 float_conv_to_ovf_u4:
354 float_conv_to_ovf_i8:
355 float_conv_to_ovf_u8:
356 float_ceq: dest:i src1:f src2:f len:48
357 float_cgt: dest:i src1:f src2:f len:48
358 float_cgt_un: dest:i src1:f src2:f len:48
359 float_clt: dest:i src1:f src2:f len:48
360 float_clt_un: dest:i src1:f src2:f len:48
361 float_ceq_membase: dest:i src1:f src2:b len:48
362 float_cgt_membase: dest:i src1:f src2:b len:48
363 float_cgt_un_membase: dest:i src1:f src2:b len:48
364 float_clt_membase: dest:i src1:f src2:b len:48
365 float_clt_un_membase: dest:i src1:f src2:b len:48
366 float_conv_to_u: dest:i src1:f len:48
367 fmove: dest:f src1:f len:48
369 aot_const: dest:i len:48
370 tls_get: dest:i len:48
371 atomic_add_i4: src1:b src2:i dest:i len:48
372 atomic_add_new_i4: src1:b src2:i dest:i len:48
373 atomic_exchange_i4: src1:b src2:i dest:i len:48
374 atomic_add_i8: src1:b src2:i dest:i len:48
375 atomic_add_new_i8: src1:b src2:i dest:i len:48
376 atomic_exchange_i8: src1:b src2:i dest:i len:48
377 adc: dest:i src1:i src2:i len:48
378 addcc: dest:i src1:i src2:i len:48
379 subcc: dest:i src1:i src2:i len:48
380 adc_imm: dest:i src1:i len:48
381 sbb: dest:i src1:i src2:i len:48
382 sbb_imm: dest:i src1:i len:48
383 br_reg: src1:i len:48
384 sin: dest:f src1:f len:48
385 cos: dest:f src1:f len:48
386 abs: dest:f src1:f len:48
387 tan: dest:f src1:f len:48
388 atan: dest:f src1:f len:48
389 sqrt: dest:f src1:f len:48
390 op_bigmul: len:48 dest:i src1:a src2:i
391 op_bigmul_un: len:48 dest:i src1:a src2:i
392 sext_i1: dest:i src1:i len:48
393 sext_i2: dest:i src1:i len:48
396 int_add: dest:i src1:i src2:i len:48
397 int_sub: dest:i src1:i src2:i len:48
398 int_mul: dest:i src1:i src2:i len:48
399 int_mul_ovf: dest:i src1:i src2:i len:48
400 int_mul_ovf_un: dest:i src1:i src2:i len:48
401 int_div: dest:a src1:a src2:i clob:d len:48
402 int_div_un: dest:a src1:a src2:i clob:d len:48
403 int_rem: dest:d src1:a src2:i clob:a len:48
404 int_rem_un: dest:d src1:a src2:i clob:a len:48
405 int_and: dest:i src1:i src2:i len:48
406 int_or: dest:i src1:i src2:i len:48
407 int_xor: dest:i src1:i src2:i len:48
408 int_shl: dest:i src1:i src2:s len:48
409 int_shr: dest:i src1:i src2:s len:48
410 int_shr_un: dest:i src1:i src2:s len:48
411 int_adc: dest:i src1:i src2:i len:48
412 int_adc_imm: dest:i src1:i len:48
413 int_sbb: dest:i src1:i src2:i len:48
414 int_sbb_imm: dest:i src1:i len:48
415 int_addcc: dest:i src1:i src2:i len:96
416 int_subcc: dest:i src1:i src2:i len:48
417 int_add_imm: dest:i src1:i len:48
418 int_sub_imm: dest:i src1:i len:48
419 int_mul_imm: dest:i src1:i len:48
420 int_div_imm: dest:a src1:i clob:d len:48
421 int_div_un_imm: dest:a src1:i clob:d len:48
422 int_rem_imm: dest:d src1:i clob:a len:48
423 int_rem_un_imm: dest:d src1:i clob:a len:48
424 int_and_imm: dest:i src1:i len:48
425 int_or_imm: dest:i src1:i len:48
426 int_xor_imm: dest:i src1:i len:48
427 int_shl_imm: dest:i src1:i len:48
428 int_shr_imm: dest:i src1:i len:48
429 int_shr_un_imm: dest:i src1:i len:48
430 int_neg: dest:i src1:i len:48
431 int_not: dest:i src1:i len:48
432 int_ceq: dest:c len:48
433 int_cgt: dest:c len:48
434 int_cgt_un: dest:c len:48
435 int_clt: dest:c len:48
436 int_clt_un: dest:c len:48
448 ia64_cmp4_eq: src1:i src2:i len:48
449 ia64_cmp4_ne: src1:i src2:i len:48
450 ia64_cmp4_le: src1:i src2:i len:48
451 ia64_cmp4_lt: src1:i src2:i len:48
452 ia64_cmp4_ge: src1:i src2:i len:48
453 ia64_cmp4_gt: src1:i src2:i len:48
454 ia64_cmp4_le_un: src1:i src2:i len:48
455 ia64_cmp4_lt_un: src1:i src2:i len:48
456 ia64_cmp4_ge_un: src1:i src2:i len:48
457 ia64_cmp4_gt_un: src1:i src2:i len:48
458 ia64_cmp_eq: src1:i src2:i len:48
459 ia64_cmp_ne: src1:i src2:i len:48
460 ia64_cmp_le: src1:i src2:i len:48
461 ia64_cmp_lt: src1:i src2:i len:48
462 ia64_cmp_ge: src1:i src2:i len:48
463 ia64_cmp_gt: src1:i src2:i len:48
464 ia64_cmp_lt_un: src1:i src2:i len:48
465 ia64_cmp_gt_un: src1:i src2:i len:48
466 ia64_cmp_le_un: src1:i src2:i len:48
467 ia64_cmp_ge_un: src1:i src2:i len:48
469 ia64_cmp4_eq_imm: src2:i len:48
470 ia64_cmp4_ne_imm: src2:i len:48
471 ia64_cmp4_le_imm: src2:i len:48
472 ia64_cmp4_lt_imm: src2:i len:48
473 ia64_cmp4_ge_imm: src2:i len:48
474 ia64_cmp4_gt_imm: src2:i len:48
475 ia64_cmp4_le_un_imm: src2:i len:48
476 ia64_cmp4_lt_un_imm: src2:i len:48
477 ia64_cmp4_ge_un_imm: src2:i len:48
478 ia64_cmp4_gt_un_imm: src2:i len:48
479 ia64_cmp_eq_imm: src2:i len:48
480 ia64_cmp_ne_imm: src2:i len:48
481 ia64_cmp_le_imm: src2:i len:48
482 ia64_cmp_lt_imm: src2:i len:48
483 ia64_cmp_ge_imm: src2:i len:48
484 ia64_cmp_gt_imm: src2:i len:48
485 ia64_cmp_lt_un_imm: src2:i len:48
486 ia64_cmp_gt_un_imm: src2:i len:48
487 ia64_cmp_le_un_imm: src2:i len:48
488 ia64_cmp_ge_un_imm: src2:i len:48
490 ia64_fcmp_eq: src1:f src2:f len:48
491 ia64_fcmp_ne: src1:f src2:f len:48
492 ia64_fcmp_le: src1:f src2:f len:48
493 ia64_fcmp_lt: src1:f src2:f len:48
494 ia64_fcmp_ge: src1:f src2:f len:48
495 ia64_fcmp_gt: src1:f src2:f len:48
496 ia64_fcmp_lt_un: src1:f src2:f len:96
497 ia64_fcmp_gt_un: src1:f src2:f len:96
498 ia64_fcmp_le_un: src1:f src2:f len:96
499 ia64_fcmp_ge_un: src1:f src2:f len:96
502 ia64_cond_exc: len:48
503 ia64_cset: dest:i len:48