1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
19 # len:number describe the maximun length in bytes of the instruction
20 # number is a positive integer
22 # cost:number describe how many cycles are needed to complete the instruction (unused)
24 # clob:spec describe if the instruction clobbers registers or has special needs
26 # spec can be one of the following characters:
27 # c clobbers caller-save registers
28 # r 'reserves' the destination register until a later instruction unreserves it
29 # used mostly to set output registers in function calls
31 # flags:spec describe if the instruction uses or sets the flags (unused)
33 # spec can be one of the following chars:
36 # m uses and modifies the flags
38 # res:spec describe what units are used in the processor (unused)
40 # delay: describe delay slots (unused)
42 # the required specifiers are: len, clob (if registers are clobbered), the registers
43 # specifiers if the registers are actually used, flags (when scheduling is implemented).
45 # See the code in mini-x86.c for more details on how the specifiers are used.
87 call: dest:a clob:c len:4
117 ldind.i1: dest:i len:8
118 ldind.u1: dest:i len:8
119 ldind.i2: dest:i len:8
120 ldind.u2: dest:i len:8
121 ldind.i4: dest:i len:8
122 ldind.u4: dest:i len:8
124 ldind.i: dest:i len:8
127 ldind.ref: dest:i len:8
128 stind.ref: src1:b src2:i
129 stind.i1: src1:b src2:i
130 stind.i2: src1:b src2:i
131 stind.i4: src1:b src2:i
133 stind.r4: src1:b src2:f
134 stind.r8: src1:b src2:f
135 add: dest:i src1:i src2:i len:4
136 sub: dest:i src1:i src2:i len:4
137 mul: dest:i src1:i src2:i len:4
138 div: dest:a src1:i src2:i len:4
139 div.un: dest:a src1:i src2:i len:4
140 rem: dest:d src1:i src2:i len:12
141 rem.un: dest:d src1:i src2:i len:12
142 and: dest:i src1:i src2:i len:4
143 or: dest:i src1:i src2:i len:4
144 xor: dest:i src1:i src2:i len:4
145 shl: dest:i src1:i src2:i len:4
146 shr: dest:i src1:i src2:i len:4
147 shr.un: dest:i src1:i src2:i len:4
148 neg: dest:i src1:i len:4
149 not: dest:i src1:i len:4
150 conv.i1: dest:i src1:i len:4
151 conv.i2: dest:i src1:i len:4
152 conv.i4: dest:i src1:i len:4
154 conv.r4: dest:f src1:i len:7
155 conv.r8: dest:f src1:i len:7
156 conv.u4: dest:i src1:i
242 ckfinite: dest:f src1:f len:22
256 conv.u2: dest:i src1:i len:4
257 conv.u1: dest:i src1:i len:4
258 conv.i: dest:i src1:i len:4
263 mul.ovf: dest:i src1:i src2:i len:8
264 # this opcode is handled specially in the code generator
265 mul.ovf.un: dest:i src1:i src2:i len:12
272 conv.u: dest:i src1:i len:4
307 cgt.un: dest:i len:12
309 clt.un: dest:i len:12
319 localloc: dest:i src1:i len:30
355 compare: src1:i src2:i len:4
356 compare_imm: src1:i len:12
357 fcompare: src1:f src2:f len:12
364 setret: dest:a src1:i len:4
365 setlret: dest:l src1:i src2:i len:8
366 setreg: dest:i src1:i len:4 clob:r
367 setregimm: dest:i len:8 clob:r
368 setfreg: dest:f src1:f len:4 clob:r
369 checkthis: src1:b len:4
370 voidcall: len:8 clob:c
371 voidcall_reg: src1:i len:8 clob:c
372 voidcall_membase: src1:b len:8 clob:c
373 fcall: dest:f len:8 clob:c
374 fcall_reg: dest:f src1:i len:8 clob:c
375 fcall_membase: dest:f src1:b len:8 clob:c
376 lcall: dest:l len:8 clob:c
377 lcall_reg: dest:l src1:i len:8 clob:c
378 lcall_membase: dest:l src1:b len:8 clob:c
380 vcall_reg: src1:i len:8 clob:c
381 vcall_membase: src1:b len:8 clob:c
382 call_reg: dest:i src1:i len:8 clob:c
383 call_membase: dest:i src1:b len:8 clob:c
387 r4const: dest:f len:8
388 r8const: dest:f len:8
393 store_membase_imm: dest:b len:12
394 store_membase_reg: dest:b src1:i len:8
395 storei1_membase_imm: dest:b len:12
396 storei1_membase_reg: dest:b src1:i len:8
397 storei2_membase_imm: dest:b len:12
398 storei2_membase_reg: dest:b src1:i len:8
399 storei4_membase_imm: dest:b len:12
400 storei4_membase_reg: dest:b src1:i len:8
401 storei8_membase_imm: dest:b
402 storei8_membase_reg: dest:b src1:i
403 storer4_membase_reg: dest:b src1:f len:8
404 storer8_membase_reg: dest:b src1:f len:8
405 load_membase: dest:i src1:b len:12
406 loadi1_membase: dest:i src1:b len:12
407 loadu1_membase: dest:i src1:b len:12
408 loadi2_membase: dest:i src1:b len:12
409 loadu2_membase: dest:i src1:b len:12
410 loadi4_membase: dest:i src1:b len:12
411 loadu4_membase: dest:i src1:b len:12
412 loadi8_membase: dest:i src1:b
413 loadr4_membase: dest:f src1:b len:8
414 loadr8_membase: dest:f src1:b len:12
415 loadu4_mem: dest:i len:8
416 move: dest:i src1:i len:4
417 add_imm: dest:i src1:i len:12
418 sub_imm: dest:i src1:i len:12
419 mul_imm: dest:i src1:i len:12
420 # there is no actual support for division or reminder by immediate
421 # we simulate them, though (but we need to change the burg rules
422 # to allocate a symbolic reg for src2)
423 div_imm: dest:a src1:i src2:i len:12
424 div_un_imm: dest:a src1:i src2:i len:12
425 rem_imm: dest:d src1:i src2:i len:16
426 rem_un_imm: dest:d src1:i src2:i len:16
427 and_imm: dest:i src1:i len:8
428 or_imm: dest:i src1:i len:8
429 xor_imm: dest:i src1:i len:8
430 shl_imm: dest:i src1:i len:8
431 shr_imm: dest:i src1:i len:8
432 shr_un_imm: dest:i src1:i len:8
434 cond_exc_ne_un: len:8
436 cond_exc_lt_un: len:8
438 cond_exc_gt_un: len:8
440 cond_exc_ge_un: len:8
442 cond_exc_le_un: len:8
473 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
481 long_conv_to_ovf_i1_un:
482 long_conv_to_ovf_i2_un:
483 long_conv_to_ovf_i4_un:
484 long_conv_to_ovf_i8_un:
485 long_conv_to_ovf_u1_un:
486 long_conv_to_ovf_u2_un:
487 long_conv_to_ovf_u4_un:
488 long_conv_to_ovf_u8_un:
489 long_conv_to_ovf_i_un:
490 long_conv_to_ovf_u_un:
504 long_conv_to_r_un: dest:f src1:i src2:i len:37
538 float_neg: dest:f src1:f len:4
539 float_not: dest:f src1:f len:4
540 float_conv_to_i1: dest:i src1:f len:40
541 float_conv_to_i2: dest:i src1:f len:40
542 float_conv_to_i4: dest:i src1:f len:40
543 float_conv_to_i8: dest:l src1:f len:40
546 float_conv_to_u4: dest:i src1:f len:40
547 float_conv_to_u8: dest:l src1:f len:40
548 float_conv_to_u2: dest:i src1:f len:40
549 float_conv_to_u1: dest:i src1:f len:40
550 float_conv_to_i: dest:i src1:f len:40
559 float_conv_to_ovf_i1_un:
560 float_conv_to_ovf_i2_un:
561 float_conv_to_ovf_i4_un:
562 float_conv_to_ovf_i8_un:
563 float_conv_to_ovf_u1_un:
564 float_conv_to_ovf_u2_un:
565 float_conv_to_ovf_u4_un:
566 float_conv_to_ovf_u8_un:
567 float_conv_to_ovf_i_un:
568 float_conv_to_ovf_u_un:
569 float_conv_to_ovf_i1:
570 float_conv_to_ovf_u1:
571 float_conv_to_ovf_i2:
572 float_conv_to_ovf_u2:
573 float_conv_to_ovf_i4:
574 float_conv_to_ovf_u4:
575 float_conv_to_ovf_i8:
576 float_conv_to_ovf_u8:
577 float_ceq: dest:i src1:f src2:f len:12
578 float_cgt: dest:i src1:f src2:f len:12
579 float_cgt_un: dest:i src1:f src2:f len:12
580 float_clt: dest:i src1:f src2:f len:12
581 float_clt_un: dest:i src1:f src2:f len:12
582 float_conv_to_u: dest:i src1:f len:36
584 op_endfilter: src1:i len:12
585 aot_const: dest:i len:8
586 x86_test_null: src1:i len:4
587 x86_compare_membase_reg: src1:b src2:i len:8
588 x86_compare_membase_imm: src1:b len:8
589 x86_compare_reg_membase: src1:i src2:b len:8
590 x86_inc_reg: dest:i src1:i clob:1 len:1
591 x86_inc_membase: src1:b len:6
592 x86_dec_reg: dest:i src1:i clob:1 len:1
593 x86_dec_membase: src1:b len:6
594 x86_add_membase_imm: src1:b len:8
595 x86_sub_membase_imm: src1:b len:8
596 x86_push: src1:i len:1
598 x86_push_membase: src1:b len:6
599 x86_push_obj: src1:b len:30
600 x86_lea: dest:i src1:i src2:i len:7
601 x86_xchg: src1:i src2:i clob:x len:1
602 x86_fpop: src1:f len:2
603 x86_fp_load_i8: dest:f src1:b len:7
604 x86_fp_load_i4: dest:f src1:b len:7
605 adc: dest:i src1:i src2:i len:4
606 addcc: dest:i src1:i src2:i len:4
607 subcc: dest:i src1:i src2:i len:4
608 adc_imm: dest:i src1:i len:8
609 sbb: dest:i src1:i src2:i len:4
610 sbb_imm: dest:i src1:i len:8
612 ppc_subfic: dest:i src1:i len:4
613 ppc_subfze: dest:i src1:i len:4