1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
20 # len:number describe the maximun length in bytes of the instruction
21 # number is a positive integer
23 # cost:number describe how many cycles are needed to complete the instruction (unused)
25 # clob:spec describe if the instruction clobbers registers or has special needs
27 # spec can be one of the following characters:
28 # c clobbers caller-save registers
29 # r 'reserves' the destination register until a later instruction unreserves it
30 # used mostly to set output registers in function calls
32 # flags:spec describe if the instruction uses or sets the flags (unused)
34 # spec can be one of the following chars:
37 # m uses and modifies the flags
39 # res:spec describe what units are used in the processor (unused)
41 # delay: describe delay slots (unused)
43 # the required specifiers are: len, clob (if registers are clobbered), the registers
44 # specifiers if the registers are actually used, flags (when scheduling is implemented).
46 # See the code in mini-x86.c for more details on how the specifiers are used.
88 call: dest:a clob:c len:16
118 ldind.i1: dest:i len:8
119 ldind.u1: dest:i len:8
120 ldind.i2: dest:i len:8
121 ldind.u2: dest:i len:8
122 ldind.i4: dest:i len:8
123 ldind.u4: dest:i len:8
125 ldind.i: dest:i len:8
128 ldind.ref: dest:i len:8
129 stind.ref: src1:b src2:i
130 stind.i1: src1:b src2:i
131 stind.i2: src1:b src2:i
132 stind.i4: src1:b src2:i
134 stind.r4: src1:b src2:f
135 stind.r8: src1:b src2:f
136 add: dest:i src1:i src2:i len:4
137 sub: dest:i src1:i src2:i len:4
138 mul: dest:i src1:i src2:i len:4
139 div: dest:i src1:i src2:i len:40
140 div.un: dest:i src1:i src2:i len:16
141 rem: dest:i src1:i src2:i len:48
142 rem.un: dest:i src1:i src2:i len:24
143 and: dest:i src1:i src2:i len:4
144 or: dest:i src1:i src2:i len:4
145 xor: dest:i src1:i src2:i len:4
146 shl: dest:i src1:i src2:i len:4
147 shr: dest:i src1:i src2:i len:4
148 shr.un: dest:i src1:i src2:i len:4
149 neg: dest:i src1:i len:4
150 not: dest:i src1:i len:4
151 conv.i1: dest:i src1:i len:4
152 conv.i2: dest:i src1:i len:4
153 conv.i4: dest:i src1:i len:4
155 conv.r4: dest:f src1:i len:36
156 conv.r8: dest:f src1:i len:36
157 conv.u4: dest:i src1:i
166 conv.r.un: dest:f src1:i len:32
169 op_rethrow: src1:i len:20
220 ppc_check_finite: src1:i len:16
223 conv.u2: dest:i src1:i len:4
224 conv.u1: dest:i src1:i len:4
225 conv.i: dest:i src1:i len:4
228 add.ovf: dest:i src1:i src2:i len:16
229 add.ovf.un: dest:i src1:i src2:i len:16
230 mul.ovf: dest:i src1:i src2:i len:16
231 # this opcode is handled specially in the code generator
232 mul.ovf.un: dest:i src1:i src2:i len:16
233 sub.ovf: dest:i src1:i src2:i len:16
234 sub.ovf.un: dest:i src1:i src2:i len:16
235 add_ovf_carry: dest:i src1:i src2:i len:16
236 sub_ovf_carry: dest:i src1:i src2:i len:16
237 add_ovf_un_carry: dest:i src1:i src2:i len:16
238 sub_ovf_un_carry: dest:i src1:i src2:i len:16
239 start_handler: len:16
244 conv.u: dest:i src1:i len:4
256 cgt.un: dest:i len:12
258 clt.un: dest:i len:12
267 localloc: dest:i src1:i len:60
290 compare: src1:i src2:i len:4
291 compare_imm: src1:i len:12
292 fcompare: src1:f src2:f len:12
296 oparglist: src1:i len:12
300 setret: dest:a src1:i len:4
301 setlret: src1:i src2:i len:12
302 setreg: dest:i src1:i len:4 clob:r
303 setregimm: dest:i len:8 clob:r
304 setfreg: dest:f src1:f len:4 clob:r
305 checkthis: src1:b len:4
306 voidcall: len:16 clob:c
307 voidcall_reg: src1:i len:8 clob:c
308 voidcall_membase: src1:b len:12 clob:c
309 fcall: dest:g len:16 clob:c
310 fcall_reg: dest:g src1:i len:8 clob:c
311 fcall_membase: dest:g src1:b len:12 clob:c
312 lcall: dest:l len:16 clob:c
313 lcall_reg: dest:l src1:i len:8 clob:c
314 lcall_membase: dest:l src1:b len:12 clob:c
316 vcall_reg: src1:i len:8 clob:c
317 vcall_membase: src1:b len:12 clob:c
318 call_reg: dest:a src1:i len:8 clob:c
319 call_membase: dest:a src1:b len:12 clob:c
321 iconst: dest:i len:12
323 r4const: dest:f len:12
324 r8const: dest:f len:12
330 store_membase_reg: dest:b src1:i len:4
332 storei1_membase_reg: dest:b src1:i len:4
334 storei2_membase_reg: dest:b src1:i len:4
336 storei4_membase_reg: dest:b src1:i len:4
339 storer4_membase_reg: dest:b src1:f len:8
340 storer8_membase_reg: dest:b src1:f len:4
341 load_membase: dest:i src1:b len:4
342 loadi1_membase: dest:i src1:b len:8
343 loadu1_membase: dest:i src1:b len:4
344 loadi2_membase: dest:i src1:b len:4
345 loadu2_membase: dest:i src1:b len:4
346 loadi4_membase: dest:i src1:b len:4
347 loadu4_membase: dest:i src1:b len:4
349 loadr4_membase: dest:f src1:b len:4
350 loadr8_membase: dest:f src1:b len:4
351 load_memindex: dest:i src1:b src2:i len:4
352 loadi1_memindex: dest:i src1:b src2:i len:8
353 loadu1_memindex: dest:i src1:b src2:i len:4
354 loadi2_memindex: dest:i src1:b src2:i len:4
355 loadu2_memindex: dest:i src1:b src2:i len:4
356 loadi4_memindex: dest:i src1:b src2:i len:4
357 loadu4_memindex: dest:i src1:b src2:i len:4
358 loadr4_memindex: dest:f src1:b src2:i len:4
359 loadr8_memindex: dest:f src1:b src2:i len:4
360 store_memindex: dest:b src1:i src2:i len:4
361 storei1_memindex: dest:b src1:i src2:i len:4
362 storei2_memindex: dest:b src1:i src2:i len:4
363 storei4_memindex: dest:b src1:i src2:i len:4
364 storer4_memindex: dest:b src1:i src2:i len:4
365 storer8_memindex: dest:b src1:i src2:i len:4
366 loadu4_mem: dest:i len:8
367 move: dest:i src1:i len:4
368 fmove: dest:f src1:f len:4
369 add_imm: dest:i src1:i len:4
370 sub_imm: dest:i src1:i len:4
371 mul_imm: dest:i src1:i len:4
372 # there is no actual support for division or reminder by immediate
373 # we simulate them, though (but we need to change the burg rules
374 # to allocate a symbolic reg for src2)
375 div_imm: dest:i src1:i src2:i len:20
376 div_un_imm: dest:i src1:i src2:i len:12
377 rem_imm: dest:i src1:i src2:i len:28
378 rem_un_imm: dest:i src1:i src2:i len:16
379 and_imm: dest:i src1:i len:4
380 or_imm: dest:i src1:i len:4
381 xor_imm: dest:i src1:i len:4
382 shl_imm: dest:i src1:i len:4
383 shr_imm: dest:i src1:i len:4
384 shr_un_imm: dest:i src1:i len:4
386 cond_exc_ne_un: len:8
388 cond_exc_lt_un: len:8
390 cond_exc_gt_un: len:8
392 cond_exc_ge_un: len:8
394 cond_exc_le_un: len:8
425 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
433 long_conv_to_ovf_i1_un:
434 long_conv_to_ovf_i2_un:
435 long_conv_to_ovf_i4_un:
436 long_conv_to_ovf_i8_un:
437 long_conv_to_ovf_u1_un:
438 long_conv_to_ovf_u2_un:
439 long_conv_to_ovf_u4_un:
440 long_conv_to_ovf_u8_un:
441 long_conv_to_ovf_i_un:
442 long_conv_to_ovf_u_un:
456 long_conv_to_r_un: dest:f src1:i src2:i len:37
483 float_add: dest:f src1:f src2:f len:4
484 float_sub: dest:f src1:f src2:f len:4
485 float_mul: dest:f src1:f src2:f len:4
486 float_div: dest:f src1:f src2:f len:4
487 float_div_un: dest:f src1:f src2:f len:4
488 float_rem: dest:f src1:f src2:f len:16
489 float_rem_un: dest:f src1:f src2:f len:16
490 float_neg: dest:f src1:f len:4
491 float_not: dest:f src1:f len:4
492 float_conv_to_i1: dest:i src1:f len:40
493 float_conv_to_i2: dest:i src1:f len:40
494 float_conv_to_i4: dest:i src1:f len:40
495 float_conv_to_i8: dest:l src1:f len:40
496 float_conv_to_r4: dest:f src1:f len:4
498 float_conv_to_u4: dest:i src1:f len:40
499 float_conv_to_u8: dest:l src1:f len:40
500 float_conv_to_u2: dest:i src1:f len:40
501 float_conv_to_u1: dest:i src1:f len:40
502 float_conv_to_i: dest:i src1:f len:40
511 float_conv_to_ovf_i1_un:
512 float_conv_to_ovf_i2_un:
513 float_conv_to_ovf_i4_un:
514 float_conv_to_ovf_i8_un:
515 float_conv_to_ovf_u1_un:
516 float_conv_to_ovf_u2_un:
517 float_conv_to_ovf_u4_un:
518 float_conv_to_ovf_u8_un:
519 float_conv_to_ovf_i_un:
520 float_conv_to_ovf_u_un:
521 float_conv_to_ovf_i1:
522 float_conv_to_ovf_u1:
523 float_conv_to_ovf_i2:
524 float_conv_to_ovf_u2:
525 float_conv_to_ovf_i4:
526 float_conv_to_ovf_u4:
527 float_conv_to_ovf_i8:
528 float_conv_to_ovf_u8:
529 float_ceq: dest:i src1:f src2:f len:16
530 float_cgt: dest:i src1:f src2:f len:16
531 float_cgt_un: dest:i src1:f src2:f len:20
532 float_clt: dest:i src1:f src2:f len:16
533 float_clt_un: dest:i src1:f src2:f len:20
534 float_conv_to_u: dest:i src1:f len:36
536 op_endfilter: src1:i len:16
537 aot_const: dest:i len:8
538 sqrt: dest:f src1:f len:4
539 adc: dest:i src1:i src2:i len:4
540 addcc: dest:i src1:i src2:i len:4
541 subcc: dest:i src1:i src2:i len:4
543 addcc_imm: dest:i src1:i len:4
545 sbb: dest:i src1:i src2:i len:4
548 ppc_subfic: dest:i src1:i len:4
549 ppc_subfze: dest:i src1:i len:4
550 op_bigmul: len:12 dest:l src1:i src2:i
551 op_bigmul_un: len:12 dest:l src1:i src2:i
552 tls_get: len:8 dest:i