1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
20 # len:number describe the maximun length in bytes of the instruction
21 # number is a positive integer
23 # cost:number describe how many cycles are needed to complete the instruction (unused)
25 # clob:spec describe if the instruction clobbers registers or has special needs
27 # spec can be one of the following characters:
28 # c clobbers caller-save registers
29 # r 'reserves' the destination register until a later instruction unreserves it
30 # used mostly to set output registers in function calls
32 # flags:spec describe if the instruction uses or sets the flags (unused)
34 # spec can be one of the following chars:
37 # m uses and modifies the flags
39 # res:spec describe what units are used in the processor (unused)
41 # delay: describe delay slots (unused)
43 # the required specifiers are: len, clob (if registers are clobbered), the registers
44 # specifiers if the registers are actually used, flags (when scheduling is implemented).
46 # See the code in mini-x86.c for more details on how the specifiers are used.
88 call: dest:a clob:c len:16
118 ldind.i1: dest:i len:8
119 ldind.u1: dest:i len:8
120 ldind.i2: dest:i len:8
121 ldind.u2: dest:i len:8
122 ldind.i4: dest:i len:8
123 ldind.u4: dest:i len:8
125 ldind.i: dest:i len:8
128 ldind.ref: dest:i len:8
129 stind.ref: src1:b src2:i
130 stind.i1: src1:b src2:i
131 stind.i2: src1:b src2:i
132 stind.i4: src1:b src2:i
134 stind.r4: src1:b src2:f
135 stind.r8: src1:b src2:f
136 add: dest:i src1:i src2:i len:4
137 sub: dest:i src1:i src2:i len:4
138 mul: dest:i src1:i src2:i len:4
139 div: dest:i src1:i src2:i len:40
140 div.un: dest:i src1:i src2:i len:16
141 rem: dest:i src1:i src2:i len:48
142 rem.un: dest:i src1:i src2:i len:24
143 and: dest:i src1:i src2:i len:4
144 or: dest:i src1:i src2:i len:4
145 xor: dest:i src1:i src2:i len:4
146 shl: dest:i src1:i src2:i len:4
147 shr: dest:i src1:i src2:i len:4
148 shr.un: dest:i src1:i src2:i len:4
149 neg: dest:i src1:i len:4
150 not: dest:i src1:i len:4
151 conv.i1: dest:i src1:i len:4
152 conv.i2: dest:i src1:i len:4
153 conv.i4: dest:i src1:i len:4
155 conv.r4: dest:f src1:i len:36
156 conv.r8: dest:f src1:i len:36
157 conv.u4: dest:i src1:i
166 conv.r.un: dest:f src1:i len:32
169 op_rethrow: src1:i len:20
219 ckfinite: dest:f src1:f len:24
222 conv.u2: dest:i src1:i len:4
223 conv.u1: dest:i src1:i len:4
224 conv.i: dest:i src1:i len:4
227 add.ovf: dest:i src1:i src2:i len:16
228 add.ovf.un: dest:i src1:i src2:i len:16
229 mul.ovf: dest:i src1:i src2:i len:16
230 # this opcode is handled specially in the code generator
231 mul.ovf.un: dest:i src1:i src2:i len:16
232 sub.ovf: dest:i src1:i src2:i len:16
233 sub.ovf.un: dest:i src1:i src2:i len:16
234 add_ovf_carry: dest:i src1:i src2:i len:16
235 sub_ovf_carry: dest:i src1:i src2:i len:16
236 add_ovf_un_carry: dest:i src1:i src2:i len:16
237 sub_ovf_un_carry: dest:i src1:i src2:i len:16
243 conv.u: dest:i src1:i len:4
255 cgt.un: dest:i len:12
257 clt.un: dest:i len:12
266 localloc: dest:i src1:i len:60
289 compare: src1:i src2:i len:4
290 compare_imm: src1:i len:12
291 fcompare: src1:f src2:f len:12
295 oparglist: src1:i len:12
299 setret: dest:a src1:i len:4
300 setlret: src1:i src2:i len:12
301 setreg: dest:i src1:i len:4 clob:r
302 setregimm: dest:i len:8 clob:r
303 setfreg: dest:f src1:f len:4 clob:r
304 checkthis: src1:b len:4
305 voidcall: len:16 clob:c
306 voidcall_reg: src1:i len:8 clob:c
307 voidcall_membase: src1:b len:12 clob:c
308 fcall: dest:f len:16 clob:c
309 fcall_reg: dest:f src1:i len:8 clob:c
310 fcall_membase: dest:f src1:b len:12 clob:c
311 lcall: dest:l len:16 clob:c
312 lcall_reg: dest:l src1:i len:8 clob:c
313 lcall_membase: dest:l src1:b len:12 clob:c
315 vcall_reg: src1:i len:8 clob:c
316 vcall_membase: src1:b len:12 clob:c
317 call_reg: dest:a src1:i len:8 clob:c
318 call_membase: dest:a src1:b len:12 clob:c
320 iconst: dest:i len:12
322 r4const: dest:f len:12
323 r8const: dest:f len:12
328 store_membase_imm: dest:b len:20
329 store_membase_reg: dest:b src1:i len:12
330 storei1_membase_imm: dest:b len:20
331 storei1_membase_reg: dest:b src1:i len:12
332 storei2_membase_imm: dest:b len:20
333 storei2_membase_reg: dest:b src1:i len:12
334 storei4_membase_imm: dest:b len:20
335 storei4_membase_reg: dest:b src1:i len:12
336 storei8_membase_imm: dest:b
337 storei8_membase_reg: dest:b src1:i
338 storer4_membase_reg: dest:b src1:f len:12
339 storer8_membase_reg: dest:b src1:f len:12
340 load_membase: dest:i src1:b len:12
341 loadi1_membase: dest:i src1:b len:12
342 loadu1_membase: dest:i src1:b len:12
343 loadi2_membase: dest:i src1:b len:12
344 loadu2_membase: dest:i src1:b len:12
345 loadi4_membase: dest:i src1:b len:12
346 loadu4_membase: dest:i src1:b len:12
347 loadi8_membase: dest:i src1:b
348 loadr4_membase: dest:f src1:b len:12
349 loadr8_membase: dest:f src1:b len:12
350 loadu4_mem: dest:i len:8
351 move: dest:i src1:i len:4
352 fmove: dest:f src1:f len:4
353 add_imm: dest:i src1:i len:12
354 sub_imm: dest:i src1:i len:12
355 mul_imm: dest:i src1:i len:12
356 # there is no actual support for division or reminder by immediate
357 # we simulate them, though (but we need to change the burg rules
358 # to allocate a symbolic reg for src2)
359 div_imm: dest:i src1:i src2:i len:20
360 div_un_imm: dest:i src1:i src2:i len:12
361 rem_imm: dest:i src1:i src2:i len:28
362 rem_un_imm: dest:i src1:i src2:i len:16
363 and_imm: dest:i src1:i len:12
364 or_imm: dest:i src1:i len:12
365 xor_imm: dest:i src1:i len:12
366 shl_imm: dest:i src1:i len:8
367 shr_imm: dest:i src1:i len:8
368 shr_un_imm: dest:i src1:i len:8
370 cond_exc_ne_un: len:8
372 cond_exc_lt_un: len:8
374 cond_exc_gt_un: len:8
376 cond_exc_ge_un: len:8
378 cond_exc_le_un: len:8
409 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
417 long_conv_to_ovf_i1_un:
418 long_conv_to_ovf_i2_un:
419 long_conv_to_ovf_i4_un:
420 long_conv_to_ovf_i8_un:
421 long_conv_to_ovf_u1_un:
422 long_conv_to_ovf_u2_un:
423 long_conv_to_ovf_u4_un:
424 long_conv_to_ovf_u8_un:
425 long_conv_to_ovf_i_un:
426 long_conv_to_ovf_u_un:
440 long_conv_to_r_un: dest:f src1:i src2:i len:37
467 float_add: dest:f src1:f src2:f len:4
468 float_sub: dest:f src1:f src2:f len:4
469 float_mul: dest:f src1:f src2:f len:4
470 float_div: dest:f src1:f src2:f len:4
471 float_div_un: dest:f src1:f src2:f len:4
472 float_rem: dest:f src1:f src2:f len:16
473 float_rem_un: dest:f src1:f src2:f len:16
474 float_neg: dest:f src1:f len:4
475 float_not: dest:f src1:f len:4
476 float_conv_to_i1: dest:i src1:f len:40
477 float_conv_to_i2: dest:i src1:f len:40
478 float_conv_to_i4: dest:i src1:f len:40
479 float_conv_to_i8: dest:l src1:f len:40
480 float_conv_to_r4: dest:f src1:f len:4
482 float_conv_to_u4: dest:i src1:f len:40
483 float_conv_to_u8: dest:l src1:f len:40
484 float_conv_to_u2: dest:i src1:f len:40
485 float_conv_to_u1: dest:i src1:f len:40
486 float_conv_to_i: dest:i src1:f len:40
495 float_conv_to_ovf_i1_un:
496 float_conv_to_ovf_i2_un:
497 float_conv_to_ovf_i4_un:
498 float_conv_to_ovf_i8_un:
499 float_conv_to_ovf_u1_un:
500 float_conv_to_ovf_u2_un:
501 float_conv_to_ovf_u4_un:
502 float_conv_to_ovf_u8_un:
503 float_conv_to_ovf_i_un:
504 float_conv_to_ovf_u_un:
505 float_conv_to_ovf_i1:
506 float_conv_to_ovf_u1:
507 float_conv_to_ovf_i2:
508 float_conv_to_ovf_u2:
509 float_conv_to_ovf_i4:
510 float_conv_to_ovf_u4:
511 float_conv_to_ovf_i8:
512 float_conv_to_ovf_u8:
513 float_ceq: dest:i src1:f src2:f len:16
514 float_cgt: dest:i src1:f src2:f len:16
515 float_cgt_un: dest:i src1:f src2:f len:20
516 float_clt: dest:i src1:f src2:f len:16
517 float_clt_un: dest:i src1:f src2:f len:20
518 float_conv_to_u: dest:i src1:f len:36
520 op_endfilter: src1:i len:16
521 aot_const: dest:i len:8
522 x86_test_null: src1:i len:4
523 x86_compare_membase_reg: src1:b src2:i len:8
524 x86_compare_membase_imm: src1:b len:8
525 x86_compare_reg_membase: src1:i src2:b len:8
526 x86_inc_reg: dest:i src1:i clob:1 len:1
527 x86_inc_membase: src1:b len:6
528 x86_dec_reg: dest:i src1:i clob:1 len:1
529 x86_dec_membase: src1:b len:6
530 x86_add_membase_imm: src1:b len:8
531 x86_sub_membase_imm: src1:b len:8
532 x86_push: src1:i len:1
534 x86_push_membase: src1:b len:6
535 x86_push_obj: src1:b len:30
536 x86_lea: dest:i src1:i src2:i len:7
537 x86_xchg: src1:i src2:i clob:x len:1
538 x86_fpop: src1:f len:2
539 x86_fp_load_i8: dest:f src1:b len:7
540 x86_fp_load_i4: dest:f src1:b len:7
541 sqrt: dest:f src1:f len:4
542 adc: dest:i src1:i src2:i len:4
543 addcc: dest:i src1:i src2:i len:4
544 subcc: dest:i src1:i src2:i len:4
545 adc_imm: dest:i src1:i len:12
546 addcc_imm: dest:i src1:i len:12
547 subcc_imm: dest:i src1:i len:12
548 sbb: dest:i src1:i src2:i len:4
549 sbb_imm: dest:i src1:i len:12
551 ppc_subfic: dest:i src1:i len:4
552 ppc_subfze: dest:i src1:i len:4
553 op_bigmul: len:8 dest:l src1:i src2:i
554 op_bigmul_un: len:8 dest:l src1:i src2:i
555 tls_get: len:8 dest:i