1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
19 # len:number describe the maximun length in bytes of the instruction
20 # number is a positive integer
22 # cost:number describe how many cycles are needed to complete the instruction (unused)
24 # clob:spec describe if the instruction clobbers registers or has special needs
26 # spec can be one of the following characters:
27 # c clobbers caller-save registers
28 # r 'reserves' the destination register until a later instruction unreserves it
29 # used mostly to set output registers in function calls
31 # flags:spec describe if the instruction uses or sets the flags (unused)
33 # spec can be one of the following chars:
36 # m uses and modifies the flags
38 # res:spec describe what units are used in the processor (unused)
40 # delay: describe delay slots (unused)
42 # the required specifiers are: len, clob (if registers are clobbered), the registers
43 # specifiers if the registers are actually used, flags (when scheduling is implemented).
45 # See the code in mini-x86.c for more details on how the specifiers are used.
86 call: dest:a clob:c len:4
116 ldind.i1: dest:i len:8
117 ldind.u1: dest:i len:8
118 ldind.i2: dest:i len:8
119 ldind.u2: dest:i len:8
120 ldind.i4: dest:i len:8
121 ldind.u4: dest:i len:8
123 ldind.i: dest:i len:8
126 ldind.ref: dest:i len:8
127 stind.ref: src1:b src2:i
128 stind.i1: src1:b src2:i
129 stind.i2: src1:b src2:i
130 stind.i4: src1:b src2:i
132 stind.r4: src1:b src2:f
133 stind.r8: src1:b src2:f
134 add: dest:i src1:i src2:i len:4
135 sub: dest:i src1:i src2:i len:4
136 mul: dest:i src1:i src2:i len:4
137 div: dest:a src1:i src2:i len:4
138 div.un: dest:a src1:i src2:i len:4
139 rem: dest:d src1:i src2:i len:12
140 rem.un: dest:d src1:i src2:i len:12
141 and: dest:i src1:i src2:i len:4
142 or: dest:i src1:i src2:i len:4
143 xor: dest:i src1:i src2:i len:4
144 shl: dest:i src1:i src2:i len:4
145 shr: dest:i src1:i src2:i len:4
146 shr.un: dest:i src1:i src2:i len:4
147 neg: dest:i src1:i len:4
148 not: dest:i src1:i len:4
149 conv.i1: dest:i src1:i len:4
150 conv.i2: dest:i src1:i len:4
151 conv.i4: dest:i src1:i len:4
153 conv.r4: dest:f src1:i len:7
154 conv.r8: dest:f src1:i len:7
155 conv.u4: dest:i src1:i
216 ckfinite: dest:f src1:f len:22
219 conv.u2: dest:i src1:i len:4
220 conv.u1: dest:i src1:i len:4
221 conv.i: dest:i src1:i len:4
226 mul.ovf: dest:i src1:i src2:i len:8
227 # this opcode is handled specially in the code generator
228 mul.ovf.un: dest:i src1:i src2:i len:12
235 conv.u: dest:i src1:i len:4
247 cgt.un: dest:i len:12
249 clt.un: dest:i len:12
258 localloc: dest:i src1:i len:30
285 compare: src1:i src2:i len:4
286 compare_imm: src1:i len:12
287 fcompare: src1:f src2:f len:12
294 setret: dest:a src1:i len:4
295 setlret: dest:l src1:i src2:i len:8
296 setreg: dest:i src1:i len:4 clob:r
297 setregimm: dest:i len:8 clob:r
298 setfreg: dest:f src1:f len:4 clob:r
299 checkthis: src1:b len:4
300 voidcall: len:8 clob:c
301 voidcall_reg: src1:i len:8 clob:c
302 voidcall_membase: src1:b len:8 clob:c
303 fcall: dest:f len:8 clob:c
304 fcall_reg: dest:f src1:i len:8 clob:c
305 fcall_membase: dest:f src1:b len:8 clob:c
306 lcall: dest:l len:8 clob:c
307 lcall_reg: dest:l src1:i len:8 clob:c
308 lcall_membase: dest:l src1:b len:8 clob:c
310 vcall_reg: src1:i len:8 clob:c
311 vcall_membase: src1:b len:8 clob:c
312 call_reg: dest:i src1:i len:8 clob:c
313 call_membase: dest:i src1:b len:8 clob:c
317 r4const: dest:f len:8
318 r8const: dest:f len:8
323 store_membase_imm: dest:b len:12
324 store_membase_reg: dest:b src1:i len:8
325 storei1_membase_imm: dest:b len:12
326 storei1_membase_reg: dest:b src1:i len:8
327 storei2_membase_imm: dest:b len:12
328 storei2_membase_reg: dest:b src1:i len:8
329 storei4_membase_imm: dest:b len:12
330 storei4_membase_reg: dest:b src1:i len:8
331 storei8_membase_imm: dest:b
332 storei8_membase_reg: dest:b src1:i
333 storer4_membase_reg: dest:b src1:f len:8
334 storer8_membase_reg: dest:b src1:f len:8
335 load_membase: dest:i src1:b len:12
336 loadi1_membase: dest:i src1:b len:12
337 loadu1_membase: dest:i src1:b len:12
338 loadi2_membase: dest:i src1:b len:12
339 loadu2_membase: dest:i src1:b len:12
340 loadi4_membase: dest:i src1:b len:12
341 loadu4_membase: dest:i src1:b len:12
342 loadi8_membase: dest:i src1:b
343 loadr4_membase: dest:f src1:b len:8
344 loadr8_membase: dest:f src1:b len:12
345 loadu4_mem: dest:i len:8
346 move: dest:i src1:i len:4
347 add_imm: dest:i src1:i len:12
348 sub_imm: dest:i src1:i len:12
349 mul_imm: dest:i src1:i len:12
350 # there is no actual support for division or reminder by immediate
351 # we simulate them, though (but we need to change the burg rules
352 # to allocate a symbolic reg for src2)
353 div_imm: dest:a src1:i src2:i len:12
354 div_un_imm: dest:a src1:i src2:i len:12
355 rem_imm: dest:d src1:i src2:i len:16
356 rem_un_imm: dest:d src1:i src2:i len:16
357 and_imm: dest:i src1:i len:8
358 or_imm: dest:i src1:i len:8
359 xor_imm: dest:i src1:i len:8
360 shl_imm: dest:i src1:i len:8
361 shr_imm: dest:i src1:i len:8
362 shr_un_imm: dest:i src1:i len:8
364 cond_exc_ne_un: len:8
366 cond_exc_lt_un: len:8
368 cond_exc_gt_un: len:8
370 cond_exc_ge_un: len:8
372 cond_exc_le_un: len:8
403 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
411 long_conv_to_ovf_i1_un:
412 long_conv_to_ovf_i2_un:
413 long_conv_to_ovf_i4_un:
414 long_conv_to_ovf_i8_un:
415 long_conv_to_ovf_u1_un:
416 long_conv_to_ovf_u2_un:
417 long_conv_to_ovf_u4_un:
418 long_conv_to_ovf_u8_un:
419 long_conv_to_ovf_i_un:
420 long_conv_to_ovf_u_un:
434 long_conv_to_r_un: dest:f src1:i src2:i len:37
468 float_neg: dest:f src1:f len:4
469 float_not: dest:f src1:f len:4
470 float_conv_to_i1: dest:i src1:f len:40
471 float_conv_to_i2: dest:i src1:f len:40
472 float_conv_to_i4: dest:i src1:f len:40
473 float_conv_to_i8: dest:l src1:f len:40
476 float_conv_to_u4: dest:i src1:f len:40
477 float_conv_to_u8: dest:l src1:f len:40
478 float_conv_to_u2: dest:i src1:f len:40
479 float_conv_to_u1: dest:i src1:f len:40
480 float_conv_to_i: dest:i src1:f len:40
489 float_conv_to_ovf_i1_un:
490 float_conv_to_ovf_i2_un:
491 float_conv_to_ovf_i4_un:
492 float_conv_to_ovf_i8_un:
493 float_conv_to_ovf_u1_un:
494 float_conv_to_ovf_u2_un:
495 float_conv_to_ovf_u4_un:
496 float_conv_to_ovf_u8_un:
497 float_conv_to_ovf_i_un:
498 float_conv_to_ovf_u_un:
499 float_conv_to_ovf_i1:
500 float_conv_to_ovf_u1:
501 float_conv_to_ovf_i2:
502 float_conv_to_ovf_u2:
503 float_conv_to_ovf_i4:
504 float_conv_to_ovf_u4:
505 float_conv_to_ovf_i8:
506 float_conv_to_ovf_u8:
507 float_ceq: dest:i src1:f src2:f len:12
508 float_cgt: dest:i src1:f src2:f len:12
509 float_cgt_un: dest:i src1:f src2:f len:12
510 float_clt: dest:i src1:f src2:f len:12
511 float_clt_un: dest:i src1:f src2:f len:12
512 float_conv_to_u: dest:i src1:f len:36
514 op_endfilter: src1:i len:12
515 aot_const: dest:i len:8
516 x86_test_null: src1:i len:4
517 x86_compare_membase_reg: src1:b src2:i len:8
518 x86_compare_membase_imm: src1:b len:8
519 x86_compare_reg_membase: src1:i src2:b len:8
520 x86_inc_reg: dest:i src1:i clob:1 len:1
521 x86_inc_membase: src1:b len:6
522 x86_dec_reg: dest:i src1:i clob:1 len:1
523 x86_dec_membase: src1:b len:6
524 x86_add_membase_imm: src1:b len:8
525 x86_sub_membase_imm: src1:b len:8
526 x86_push: src1:i len:1
528 x86_push_membase: src1:b len:6
529 x86_push_obj: src1:b len:30
530 x86_lea: dest:i src1:i src2:i len:7
531 x86_xchg: src1:i src2:i clob:x len:1
532 x86_fpop: src1:f len:2
533 x86_fp_load_i8: dest:f src1:b len:7
534 x86_fp_load_i4: dest:f src1:b len:7
535 adc: dest:i src1:i src2:i len:4
536 addcc: dest:i src1:i src2:i len:4
537 subcc: dest:i src1:i src2:i len:4
538 adc_imm: dest:i src1:i len:8
539 sbb: dest:i src1:i src2:i len:4
540 sbb_imm: dest:i src1:i len:8
542 ppc_subfic: dest:i src1:i len:4
543 ppc_subfze: dest:i src1:i len:4
544 op_bigmul: len:2 dest:l src1:a src2:i
545 op_bigmul_un: len:2 dest:l src1:a src2:i