1 # Copyright 2003-2011 Novell, Inc (http://www.novell.com)
2 # Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
3 # arm cpu description file
4 # this file is read by genmdesc to pruduce a table with all the relevant information
5 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
6 # and other parts of the arch-dependent part of mini.
8 # An opcode name is followed by a colon and optional specifiers.
9 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
10 # Here is a description of the specifiers valid for this file and their possible values.
12 # dest:register describes the destination register of an instruction
13 # src1:register describes the first source register of an instruction
14 # src2:register describes the second source register of an instruction
16 # register may have the following values:
18 # a r3 register (output from calls)
19 # b base register (used in address references)
20 # f floating point register
21 # g floating point register returned in r0:r1 for soft-float mode
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer
26 # cost:number describe how many cycles are needed to complete the instruction (unused)
28 # clob:spec describe if the instruction clobbers registers or has special needs
30 # spec can be one of the following characters:
31 # c clobbers caller-save registers
32 # r 'reserves' the destination register until a later instruction unreserves it
33 # used mostly to set output registers in function calls
35 # flags:spec describe if the instruction uses or sets the flags (unused)
37 # spec can be one of the following chars:
40 # m uses and modifies the flags
42 # res:spec describe what units are used in the processor (unused)
44 # delay: describe delay slots (unused)
46 # the required specifiers are: len, clob (if registers are clobbered), the registers
47 # specifiers if the registers are actually used, flags (when scheduling is implemented).
49 # See the code in mini-x86.c for more details on how the specifiers are used.
51 memory_barrier: len:8 clob:a
58 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
59 # since the corresponding sigctx structures are not well defined.
60 seq_point: len:38 clob:c
64 rethrow: src1:i len:20
67 call_handler: len:16 clob:c
68 endfilter: src1:i len:16
70 ckfinite: dest:f src1:f len:112
76 localloc: dest:i src1:i len:60
77 compare: src1:i src2:i len:4
78 compare_imm: src1:i len:12
79 fcompare: src1:f src2:f len:12
80 oparglist: src1:i len:12
81 setlret: src1:i src2:i len:12
82 checkthis: src1:b len:4
83 call: dest:a clob:c len:20
84 call_reg: dest:a src1:i len:8 clob:c
85 call_membase: dest:a src1:b len:24 clob:c
86 voidcall: len:20 clob:c
87 voidcall_reg: src1:i len:8 clob:c
88 voidcall_membase: src1:b len:16 clob:c
89 fcall: dest:g len:28 clob:c
90 fcall_reg: dest:g src1:i len:16 clob:c
91 fcall_membase: dest:g src1:b len:24 clob:c
92 lcall: dest:l len:20 clob:c
93 lcall_reg: dest:l src1:i len:8 clob:c
94 lcall_membase: dest:l src1:b len:16 clob:c
96 vcall_reg: src1:i len:8 clob:c
97 vcall_membase: src1:b len:16 clob:c
98 tailcall: len:160 clob:c
100 r4const: dest:f len:24
101 r8const: dest:f len:20
103 store_membase_imm: dest:b len:20
104 store_membase_reg: dest:b src1:i len:20
105 storei1_membase_imm: dest:b len:20
106 storei1_membase_reg: dest:b src1:i len:12
107 storei2_membase_imm: dest:b len:20
108 storei2_membase_reg: dest:b src1:i len:12
109 storei4_membase_imm: dest:b len:20
110 storei4_membase_reg: dest:b src1:i len:20
111 storei8_membase_imm: dest:b
112 storei8_membase_reg: dest:b src1:i
113 storer4_membase_reg: dest:b src1:f len:60
114 storer8_membase_reg: dest:b src1:f len:24
115 store_memindex: dest:b src1:i src2:i len:4
116 storei1_memindex: dest:b src1:i src2:i len:4
117 storei2_memindex: dest:b src1:i src2:i len:4
118 storei4_memindex: dest:b src1:i src2:i len:4
119 load_membase: dest:i src1:b len:20
120 loadi1_membase: dest:i src1:b len:4
121 loadu1_membase: dest:i src1:b len:4
122 loadi2_membase: dest:i src1:b len:4
123 loadu2_membase: dest:i src1:b len:4
124 loadi4_membase: dest:i src1:b len:4
125 loadu4_membase: dest:i src1:b len:4
126 loadi8_membase: dest:i src1:b
127 loadr4_membase: dest:f src1:b len:56
128 loadr8_membase: dest:f src1:b len:24
129 load_memindex: dest:i src1:b src2:i len:4
130 loadi1_memindex: dest:i src1:b src2:i len:4
131 loadu1_memindex: dest:i src1:b src2:i len:4
132 loadi2_memindex: dest:i src1:b src2:i len:4
133 loadu2_memindex: dest:i src1:b src2:i len:4
134 loadi4_memindex: dest:i src1:b src2:i len:4
135 loadu4_memindex: dest:i src1:b src2:i len:4
136 loadu4_mem: dest:i len:8
137 move: dest:i src1:i len:4
138 fmove: dest:f src1:f len:4
139 add_imm: dest:i src1:i len:12
140 sub_imm: dest:i src1:i len:12
141 mul_imm: dest:i src1:i len:12
142 and_imm: dest:i src1:i len:12
143 or_imm: dest:i src1:i len:12
144 xor_imm: dest:i src1:i len:12
145 shl_imm: dest:i src1:i len:8
146 shr_imm: dest:i src1:i len:8
147 shr_un_imm: dest:i src1:i len:8
149 cond_exc_ne_un: len:8
151 cond_exc_lt_un: len:8
153 cond_exc_gt_un: len:8
155 cond_exc_ge_un: len:8
157 cond_exc_le_un: len:8
162 #float_beq: src1:f src2:f len:20
163 #float_bne_un: src1:f src2:f len:20
164 #float_blt: src1:f src2:f len:20
165 #float_blt_un: src1:f src2:f len:20
166 #float_bgt: src1:f src2:f len:20
167 #float_bgt_un: src1:f src2:f len:20
168 #float_bge: src1:f src2:f len:20
169 #float_bge_un: src1:f src2:f len:20
170 #float_ble: src1:f src2:f len:20
171 #float_ble_un: src1:f src2:f len:20
172 float_add: dest:f src1:f src2:f len:4
173 float_sub: dest:f src1:f src2:f len:4
174 float_mul: dest:f src1:f src2:f len:4
175 float_div: dest:f src1:f src2:f len:4
176 float_div_un: dest:f src1:f src2:f len:4
177 float_rem: dest:f src1:f src2:f len:16
178 float_rem_un: dest:f src1:f src2:f len:16
179 float_neg: dest:f src1:f len:4
180 float_not: dest:f src1:f len:4
181 float_conv_to_i1: dest:i src1:f len:88
182 float_conv_to_i2: dest:i src1:f len:88
183 float_conv_to_i4: dest:i src1:f len:88
184 float_conv_to_i8: dest:l src1:f len:88
185 float_conv_to_r4: dest:f src1:f len:8
186 float_conv_to_u4: dest:i src1:f len:88
187 float_conv_to_u8: dest:l src1:f len:88
188 float_conv_to_u2: dest:i src1:f len:88
189 float_conv_to_u1: dest:i src1:f len:88
190 float_conv_to_i: dest:i src1:f len:40
191 float_ceq: dest:i src1:f src2:f len:16
192 float_cgt: dest:i src1:f src2:f len:16
193 float_cgt_un: dest:i src1:f src2:f len:20
194 float_clt: dest:i src1:f src2:f len:16
195 float_clt_un: dest:i src1:f src2:f len:20
196 float_cneq: dest:y src1:f src2:f len:20
197 float_cge: dest:y src1:f src2:f len:20
198 float_cle: dest:y src1:f src2:f len:20
199 float_conv_to_u: dest:i src1:f len:36
200 setfret: src1:f len:12
201 aot_const: dest:i len:16
202 objc_get_selector: dest:i len:32
203 sqrt: dest:f src1:f len:4
204 adc: dest:i src1:i src2:i len:4
205 addcc: dest:i src1:i src2:i len:4
206 subcc: dest:i src1:i src2:i len:4
207 adc_imm: dest:i src1:i len:12
208 addcc_imm: dest:i src1:i len:12
209 subcc_imm: dest:i src1:i len:12
210 sbb: dest:i src1:i src2:i len:4
211 sbb_imm: dest:i src1:i len:12
213 bigmul: len:8 dest:l src1:i src2:i
214 bigmul_un: len:8 dest:l src1:i src2:i
215 tls_get: len:24 dest:i clob:c
218 int_add: dest:i src1:i src2:i len:4
219 int_sub: dest:i src1:i src2:i len:4
220 int_mul: dest:i src1:i src2:i len:4
221 int_div: dest:i src1:i src2:i len:4
222 int_div_un: dest:i src1:i src2:i len:4
223 int_rem: dest:i src1:i src2:i len:8
224 int_rem_un: dest:i src1:i src2:i len:8
225 int_and: dest:i src1:i src2:i len:4
226 int_or: dest:i src1:i src2:i len:4
227 int_xor: dest:i src1:i src2:i len:4
228 int_shl: dest:i src1:i src2:i len:4
229 int_shr: dest:i src1:i src2:i len:4
230 int_shr_un: dest:i src1:i src2:i len:4
231 int_neg: dest:i src1:i len:4
232 int_not: dest:i src1:i len:4
233 int_conv_to_i1: dest:i src1:i len:8
234 int_conv_to_i2: dest:i src1:i len:8
235 int_conv_to_i4: dest:i src1:i len:4
236 int_conv_to_r4: dest:f src1:i len:84
237 int_conv_to_r8: dest:f src1:i len:84
238 int_conv_to_u4: dest:i src1:i
239 int_conv_to_r_un: dest:f src1:i len:56
240 int_conv_to_u2: dest:i src1:i len:8
241 int_conv_to_u1: dest:i src1:i len:4
252 int_add_ovf: dest:i src1:i src2:i len:16
253 int_add_ovf_un: dest:i src1:i src2:i len:16
254 int_mul_ovf: dest:i src1:i src2:i len:16
255 int_mul_ovf_un: dest:i src1:i src2:i len:16
256 int_sub_ovf: dest:i src1:i src2:i len:16
257 int_sub_ovf_un: dest:i src1:i src2:i len:16
258 add_ovf_carry: dest:i src1:i src2:i len:16
259 sub_ovf_carry: dest:i src1:i src2:i len:16
260 add_ovf_un_carry: dest:i src1:i src2:i len:16
261 sub_ovf_un_carry: dest:i src1:i src2:i len:16
263 arm_rsbs_imm: dest:i src1:i len:4
264 arm_rsc_imm: dest:i src1:i len:4
267 dummy_use: src1:i len:0
269 dummy_iconst: dest:i len:0
270 dummy_r8const: dest:f len:0
272 not_null: src1:i len:0
274 int_adc: dest:i src1:i src2:i len:4
275 int_addcc: dest:i src1:i src2:i len:4
276 int_subcc: dest:i src1:i src2:i len:4
277 int_sbb: dest:i src1:i src2:i len:4
278 int_adc_imm: dest:i src1:i len:12
279 int_sbb_imm: dest:i src1:i len:12
281 int_add_imm: dest:i src1:i len:12
282 int_sub_imm: dest:i src1:i len:12
283 int_mul_imm: dest:i src1:i len:12
284 int_div_imm: dest:i src1:i len:20
285 int_div_un_imm: dest:i src1:i len:12
286 int_rem_imm: dest:i src1:i len:28
287 int_rem_un_imm: dest:i src1:i len:16
288 int_and_imm: dest:i src1:i len:12
289 int_or_imm: dest:i src1:i len:12
290 int_xor_imm: dest:i src1:i len:12
291 int_shl_imm: dest:i src1:i len:8
292 int_shr_imm: dest:i src1:i len:8
293 int_shr_un_imm: dest:i src1:i len:8
295 int_ceq: dest:i len:12
296 int_cgt: dest:i len:12
297 int_cgt_un: dest:i len:12
298 int_clt: dest:i len:12
299 int_clt_un: dest:i len:12
301 int_cneq: dest:i len:12
302 int_cge: dest:i len:12
303 int_cle: dest:i len:12
304 int_cge_un: dest:i len:12
305 int_cle_un: dest:i len:12
308 cond_exc_ine_un: len:16
310 cond_exc_ilt_un: len:16
312 cond_exc_igt_un: len:16
314 cond_exc_ige_un: len:16
316 cond_exc_ile_un: len:16
322 icompare: src1:i src2:i len:4
323 icompare_imm: src1:i len:12
325 long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
327 vcall2: len:20 clob:c
328 vcall2_reg: src1:i len:8 clob:c
329 vcall2_membase: src1:b len:12 clob:c
330 dyn_call: src1:i src2:i len:120 clob:c
332 # This is different from the original JIT opcodes
344 liverange_start: len:0
346 gc_liveness_def: len:0
347 gc_liveness_use: len:0
348 gc_spill_slot_liveness_def: len:0
349 gc_param_slot_liveness_def: len:0
351 atomic_add_i4: dest:i src1:i src2:i len:64
352 atomic_exchange_i4: dest:i src1:i src2:i len:64
353 atomic_cas_i4: dest:i src1:i src2:i src3:i len:64