1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
20 # len:number describe the maximun length in bytes of the instruction
21 # number is a positive integer
23 # cost:number describe how many cycles are needed to complete the instruction (unused)
25 # clob:spec describe if the instruction clobbers registers or has special needs
27 # spec can be one of the following characters:
28 # c clobbers caller-save registers
29 # r 'reserves' the destination register until a later instruction unreserves it
30 # used mostly to set output registers in function calls
32 # flags:spec describe if the instruction uses or sets the flags (unused)
34 # spec can be one of the following chars:
37 # m uses and modifies the flags
39 # res:spec describe what units are used in the processor (unused)
41 # delay: describe delay slots (unused)
43 # the required specifiers are: len, clob (if registers are clobbered), the registers
44 # specifiers if the registers are actually used, flags (when scheduling is implemented).
46 # See the code in mini-x86.c for more details on how the specifiers are used.
88 call: dest:a clob:c len:20
118 ldind.i1: dest:i len:8
119 ldind.u1: dest:i len:8
120 ldind.i2: dest:i len:8
121 ldind.u2: dest:i len:8
122 ldind.i4: dest:i len:8
123 ldind.u4: dest:i len:8
125 ldind.i: dest:i len:8
128 ldind.ref: dest:i len:8
129 stind.ref: src1:b src2:i
130 stind.i1: src1:b src2:i
131 stind.i2: src1:b src2:i
132 stind.i4: src1:b src2:i
134 stind.r4: src1:b src2:f
135 stind.r8: src1:b src2:f
136 add: dest:i src1:i src2:i len:4
137 sub: dest:i src1:i src2:i len:4
138 mul: dest:i src1:i src2:i len:4
139 div: dest:i src1:i src2:i len:40
140 div.un: dest:i src1:i src2:i len:16
141 rem: dest:i src1:i src2:i len:48
142 rem.un: dest:i src1:i src2:i len:24
143 and: dest:i src1:i src2:i len:4
144 or: dest:i src1:i src2:i len:4
145 xor: dest:i src1:i src2:i len:4
146 shl: dest:i src1:i src2:i len:4
147 shr: dest:i src1:i src2:i len:4
148 shr.un: dest:i src1:i src2:i len:4
149 neg: dest:i src1:i len:4
150 not: dest:i src1:i len:4
151 conv.i1: dest:i src1:i len:8
152 conv.i2: dest:i src1:i len:8
153 conv.i4: dest:i src1:i len:4
155 conv.r4: dest:f src1:i len:36
156 conv.r8: dest:f src1:i len:36
157 conv.u4: dest:i src1:i
166 conv.r.un: dest:f src1:i len:56
169 op_rethrow: src1:i len:20
219 ckfinite: dest:f src1:f len:24
222 conv.u2: dest:i src1:i len:8
223 conv.u1: dest:i src1:i len:4
224 conv.i: dest:i src1:i len:4
227 add.ovf: dest:i src1:i src2:i len:16
228 add.ovf.un: dest:i src1:i src2:i len:16
229 mul.ovf: dest:i src1:i src2:i len:16
230 # this opcode is handled specially in the code generator
231 mul.ovf.un: dest:i src1:i src2:i len:16
232 sub.ovf: dest:i src1:i src2:i len:16
233 sub.ovf.un: dest:i src1:i src2:i len:16
234 add_ovf_carry: dest:i src1:i src2:i len:16
235 sub_ovf_carry: dest:i src1:i src2:i len:16
236 add_ovf_un_carry: dest:i src1:i src2:i len:16
237 sub_ovf_un_carry: dest:i src1:i src2:i len:16
238 start_handler: len:20
243 conv.u: dest:i src1:i len:4
255 cgt.un: dest:i len:12
257 clt.un: dest:i len:12
266 localloc: dest:i src1:i len:60
289 compare: src1:i src2:i len:4
290 compare_imm: src1:i len:12
291 fcompare: src1:f src2:f len:12
295 oparglist: src1:i len:12
299 setret: dest:a src1:i len:4
300 setlret: src1:i src2:i len:12
301 setreg: dest:i src1:i len:4 clob:r
302 setregimm: dest:i len:16 clob:r
303 setfreg: dest:f src1:f len:4 clob:r
304 checkthis: src1:b len:4
305 voidcall: len:20 clob:c
306 voidcall_reg: src1:i len:8 clob:c
307 voidcall_membase: src1:b len:12 clob:c
308 fcall: dest:f len:20 clob:c
309 fcall_reg: dest:f src1:i len:8 clob:c
310 fcall_membase: dest:f src1:b len:12 clob:c
311 lcall: dest:l len:20 clob:c
312 lcall_reg: dest:l src1:i len:8 clob:c
313 lcall_membase: dest:l src1:b len:12 clob:c
315 vcall_reg: src1:i len:8 clob:c
316 vcall_membase: src1:b len:12 clob:c
317 call_reg: dest:a src1:i len:8 clob:c
318 call_membase: dest:a src1:b len:12 clob:c
320 iconst: dest:i len:16
322 r4const: dest:f len:20
323 r8const: dest:f len:20
328 store_membase_imm: dest:b len:20
329 store_membase_reg: dest:b src1:i len:20
330 storei1_membase_imm: dest:b len:20
331 storei1_membase_reg: dest:b src1:i len:12
332 storei2_membase_imm: dest:b len:20
333 storei2_membase_reg: dest:b src1:i len:12
334 storei4_membase_imm: dest:b len:20
335 storei4_membase_reg: dest:b src1:i len:20
336 storei8_membase_imm: dest:b
337 storei8_membase_reg: dest:b src1:i
338 storer4_membase_reg: dest:b src1:f len:12
339 storer8_membase_reg: dest:b src1:f len:12
340 store_memindex: dest:b src1:i src2:i len:4
341 storei1_memindex: dest:b src1:i src2:i len:4
342 storei2_memindex: dest:b src1:i src2:i len:4
343 storei4_memindex: dest:b src1:i src2:i len:4
344 load_membase: dest:i src1:b len:20
345 loadi1_membase: dest:i src1:b len:4
346 loadu1_membase: dest:i src1:b len:4
347 loadi2_membase: dest:i src1:b len:4
348 loadu2_membase: dest:i src1:b len:4
349 loadi4_membase: dest:i src1:b len:4
350 loadu4_membase: dest:i src1:b len:4
351 loadi8_membase: dest:i src1:b
352 loadr4_membase: dest:f src1:b len:4
353 loadr8_membase: dest:f src1:b len:4
354 load_memindex: dest:i src1:b src2:i len:4
355 loadi1_memindex: dest:i src1:b src2:i len:4
356 loadu1_memindex: dest:i src1:b src2:i len:4
357 loadi2_memindex: dest:i src1:b src2:i len:4
358 loadu2_memindex: dest:i src1:b src2:i len:4
359 loadi4_memindex: dest:i src1:b src2:i len:4
360 loadu4_memindex: dest:i src1:b src2:i len:4
361 loadu4_mem: dest:i len:8
362 move: dest:i src1:i len:4
363 fmove: dest:f src1:f len:4
364 add_imm: dest:i src1:i len:12
365 sub_imm: dest:i src1:i len:12
366 mul_imm: dest:i src1:i len:12
367 # there is no actual support for division or reminder by immediate
368 # we simulate them, though (but we need to change the burg rules
369 # to allocate a symbolic reg for src2)
370 div_imm: dest:i src1:i src2:i len:20
371 div_un_imm: dest:i src1:i src2:i len:12
372 rem_imm: dest:i src1:i src2:i len:28
373 rem_un_imm: dest:i src1:i src2:i len:16
374 and_imm: dest:i src1:i len:12
375 or_imm: dest:i src1:i len:12
376 xor_imm: dest:i src1:i len:12
377 shl_imm: dest:i src1:i len:8
378 shr_imm: dest:i src1:i len:8
379 shr_un_imm: dest:i src1:i len:8
381 cond_exc_ne_un: len:8
383 cond_exc_lt_un: len:8
385 cond_exc_gt_un: len:8
387 cond_exc_ge_un: len:8
389 cond_exc_le_un: len:8
420 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
428 long_conv_to_ovf_i1_un:
429 long_conv_to_ovf_i2_un:
430 long_conv_to_ovf_i4_un:
431 long_conv_to_ovf_i8_un:
432 long_conv_to_ovf_u1_un:
433 long_conv_to_ovf_u2_un:
434 long_conv_to_ovf_u4_un:
435 long_conv_to_ovf_u8_un:
436 long_conv_to_ovf_i_un:
437 long_conv_to_ovf_u_un:
451 long_conv_to_r_un: dest:f src1:i src2:i len:37
468 float_beq: src1:f src2:f len:20
469 float_bne_un: src1:f src2:f len:20
470 float_blt: src1:f src2:f len:20
471 float_blt_un: src1:f src2:f len:20
472 float_bgt: src1:f src2:f len:20
473 float_btg_un: src1:f src2:f len:20
474 float_bge: src1:f src2:f len:20
475 float_bge_un: src1:f src2:f len:20
476 float_ble: src1:f src2:f len:20
477 float_ble_un: src1:f src2:f len:20
478 float_add: dest:f src1:f src2:f len:4
479 float_sub: dest:f src1:f src2:f len:4
480 float_mul: dest:f src1:f src2:f len:4
481 float_div: dest:f src1:f src2:f len:4
482 float_div_un: dest:f src1:f src2:f len:4
483 float_rem: dest:f src1:f src2:f len:16
484 float_rem_un: dest:f src1:f src2:f len:16
485 float_neg: dest:f src1:f len:4
486 float_not: dest:f src1:f len:4
487 float_conv_to_i1: dest:i src1:f len:40
488 float_conv_to_i2: dest:i src1:f len:40
489 float_conv_to_i4: dest:i src1:f len:40
490 float_conv_to_i8: dest:l src1:f len:40
491 float_conv_to_r4: dest:f src1:f len:4
493 float_conv_to_u4: dest:i src1:f len:40
494 float_conv_to_u8: dest:l src1:f len:40
495 float_conv_to_u2: dest:i src1:f len:40
496 float_conv_to_u1: dest:i src1:f len:40
497 float_conv_to_i: dest:i src1:f len:40
506 float_conv_to_ovf_i1_un:
507 float_conv_to_ovf_i2_un:
508 float_conv_to_ovf_i4_un:
509 float_conv_to_ovf_i8_un:
510 float_conv_to_ovf_u1_un:
511 float_conv_to_ovf_u2_un:
512 float_conv_to_ovf_u4_un:
513 float_conv_to_ovf_u8_un:
514 float_conv_to_ovf_i_un:
515 float_conv_to_ovf_u_un:
516 float_conv_to_ovf_i1:
517 float_conv_to_ovf_u1:
518 float_conv_to_ovf_i2:
519 float_conv_to_ovf_u2:
520 float_conv_to_ovf_i4:
521 float_conv_to_ovf_u4:
522 float_conv_to_ovf_i8:
523 float_conv_to_ovf_u8:
524 float_ceq: dest:i src1:f src2:f len:16
525 float_cgt: dest:i src1:f src2:f len:16
526 float_cgt_un: dest:i src1:f src2:f len:20
527 float_clt: dest:i src1:f src2:f len:16
528 float_clt_un: dest:i src1:f src2:f len:20
529 float_conv_to_u: dest:i src1:f len:36
531 op_endfilter: src1:i len:16
532 aot_const: dest:i len:8
533 sqrt: dest:f src1:f len:4
534 adc: dest:i src1:i src2:i len:4
535 addcc: dest:i src1:i src2:i len:4
536 subcc: dest:i src1:i src2:i len:4
537 adc_imm: dest:i src1:i len:12
538 addcc_imm: dest:i src1:i len:12
539 subcc_imm: dest:i src1:i len:12
540 sbb: dest:i src1:i src2:i len:4
541 sbb_imm: dest:i src1:i len:12
543 arm_rsbs_imm: dest:i src1:i len:4
544 arm_rsc_imm: dest:i src1:i len:4
545 op_bigmul: len:8 dest:l src1:i src2:i
546 op_bigmul_un: len:8 dest:l src1:i src2:i
547 tls_get: len:8 dest:i