1 # Copyright 2003-2011 Novell, Inc (http://www.novell.com)
2 # Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
3 # arm cpu description file
4 # this file is read by genmdesc to pruduce a table with all the relevant information
5 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
6 # and other parts of the arch-dependent part of mini.
8 # An opcode name is followed by a colon and optional specifiers.
9 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
10 # Here is a description of the specifiers valid for this file and their possible values.
12 # dest:register describes the destination register of an instruction
13 # src1:register describes the first source register of an instruction
14 # src2:register describes the second source register of an instruction
16 # register may have the following values:
18 # a r0 register (first argument/result reg)
19 # b base register (used in address references)
20 # f floating point register
21 # g floating point register returned in r0:r1 for soft-float mode
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer
26 # cost:number describe how many cycles are needed to complete the instruction (unused)
28 # clob:spec describe if the instruction clobbers registers or has special needs
30 # spec can be one of the following characters:
31 # c clobbers caller-save registers
32 # r 'reserves' the destination register until a later instruction unreserves it
33 # used mostly to set output registers in function calls
35 # flags:spec describe if the instruction uses or sets the flags (unused)
37 # spec can be one of the following chars:
40 # m uses and modifies the flags
42 # res:spec describe what units are used in the processor (unused)
44 # delay: describe delay slots (unused)
46 # the required specifiers are: len, clob (if registers are clobbered), the registers
47 # specifiers if the registers are actually used, flags (when scheduling is implemented).
49 # See the code in mini-x86.c for more details on how the specifiers are used.
56 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
57 # since the corresponding sigctx structures are not well defined.
58 seq_point: len:52 clob:c
62 rethrow: src1:i len:20
65 call_handler: len:16 clob:c
66 endfilter: src1:i len:16
67 get_ex_obj: dest:i len:16
69 ckfinite: dest:f src1:f len:112
75 localloc: dest:i src1:i len:60
76 compare: src1:i src2:i len:4
77 compare_imm: src1:i len:12
78 fcompare: src1:f src2:f len:12
79 rcompare: src1:f src2:f len:12
80 oparglist: src1:i len:12
81 setlret: src1:i src2:i len:12
82 checkthis: src1:b len:4
83 call: dest:a clob:c len:20
84 call_reg: dest:a src1:i len:8 clob:c
85 call_membase: dest:a src1:b len:30 clob:c
86 voidcall: len:20 clob:c
87 voidcall_reg: src1:i len:8 clob:c
88 voidcall_membase: src1:b len:24 clob:c
89 fcall: dest:g len:28 clob:c
90 fcall_reg: dest:g src1:i len:16 clob:c
91 fcall_membase: dest:g src1:b len:30 clob:c
92 rcall: dest:g len:28 clob:c
93 rcall_reg: dest:g src1:i len:16 clob:c
94 rcall_membase: dest:g src1:b len:30 clob:c
95 lcall: dest:l len:20 clob:c
96 lcall_reg: dest:l src1:i len:8 clob:c
97 lcall_membase: dest:l src1:b len:24 clob:c
99 vcall_reg: src1:i len:64 clob:c
100 vcall_membase: src1:b len:70 clob:c
101 tailcall: len:160 clob:c
102 iconst: dest:i len:16
103 r4const: dest:f len:24
104 r8const: dest:f len:20
106 store_membase_imm: dest:b len:20
107 store_membase_reg: dest:b src1:i len:20
108 storei1_membase_imm: dest:b len:20
109 storei1_membase_reg: dest:b src1:i len:12
110 storei2_membase_imm: dest:b len:20
111 storei2_membase_reg: dest:b src1:i len:12
112 storei4_membase_imm: dest:b len:20
113 storei4_membase_reg: dest:b src1:i len:20
114 storei8_membase_imm: dest:b
115 storei8_membase_reg: dest:b src1:i
116 storer4_membase_reg: dest:b src1:f len:60
117 storer8_membase_reg: dest:b src1:f len:24
118 store_memindex: dest:b src1:i src2:i len:4
119 storei1_memindex: dest:b src1:i src2:i len:4
120 storei2_memindex: dest:b src1:i src2:i len:4
121 storei4_memindex: dest:b src1:i src2:i len:4
122 load_membase: dest:i src1:b len:20
123 loadi1_membase: dest:i src1:b len:4
124 loadu1_membase: dest:i src1:b len:4
125 loadi2_membase: dest:i src1:b len:4
126 loadu2_membase: dest:i src1:b len:4
127 loadi4_membase: dest:i src1:b len:4
128 loadu4_membase: dest:i src1:b len:4
129 loadi8_membase: dest:i src1:b
130 loadr4_membase: dest:f src1:b len:56
131 loadr8_membase: dest:f src1:b len:24
132 load_memindex: dest:i src1:b src2:i len:4
133 loadi1_memindex: dest:i src1:b src2:i len:4
134 loadu1_memindex: dest:i src1:b src2:i len:4
135 loadi2_memindex: dest:i src1:b src2:i len:4
136 loadu2_memindex: dest:i src1:b src2:i len:4
137 loadi4_memindex: dest:i src1:b src2:i len:4
138 loadu4_memindex: dest:i src1:b src2:i len:4
139 loadu4_mem: dest:i len:8
140 move: dest:i src1:i len:4
141 fmove: dest:f src1:f len:4
142 move_f_to_i4: dest:i src1:f len:28
143 move_i4_to_f: dest:f src1:i len:8
144 add_imm: dest:i src1:i len:12
145 sub_imm: dest:i src1:i len:12
146 mul_imm: dest:i src1:i len:12
147 and_imm: dest:i src1:i len:12
148 or_imm: dest:i src1:i len:12
149 xor_imm: dest:i src1:i len:12
150 shl_imm: dest:i src1:i len:8
151 shr_imm: dest:i src1:i len:8
152 shr_un_imm: dest:i src1:i len:8
154 cond_exc_ne_un: len:8
156 cond_exc_lt_un: len:8
158 cond_exc_gt_un: len:8
160 cond_exc_ge_un: len:8
162 cond_exc_le_un: len:8
167 #float_beq: src1:f src2:f len:20
168 #float_bne_un: src1:f src2:f len:20
169 #float_blt: src1:f src2:f len:20
170 #float_blt_un: src1:f src2:f len:20
171 #float_bgt: src1:f src2:f len:20
172 #float_bgt_un: src1:f src2:f len:20
173 #float_bge: src1:f src2:f len:20
174 #float_bge_un: src1:f src2:f len:20
175 #float_ble: src1:f src2:f len:20
176 #float_ble_un: src1:f src2:f len:20
177 float_add: dest:f src1:f src2:f len:4
178 float_sub: dest:f src1:f src2:f len:4
179 float_mul: dest:f src1:f src2:f len:4
180 float_div: dest:f src1:f src2:f len:4
181 float_div_un: dest:f src1:f src2:f len:4
182 float_rem: dest:f src1:f src2:f len:16
183 float_rem_un: dest:f src1:f src2:f len:16
184 float_neg: dest:f src1:f len:4
185 float_not: dest:f src1:f len:4
186 float_conv_to_i1: dest:i src1:f len:88
187 float_conv_to_i2: dest:i src1:f len:88
188 float_conv_to_i4: dest:i src1:f len:88
189 float_conv_to_i8: dest:l src1:f len:88
190 float_conv_to_r4: dest:f src1:f len:8
191 float_conv_to_u4: dest:i src1:f len:88
192 float_conv_to_u8: dest:l src1:f len:88
193 float_conv_to_u2: dest:i src1:f len:88
194 float_conv_to_u1: dest:i src1:f len:88
195 float_conv_to_i: dest:i src1:f len:40
196 float_ceq: dest:i src1:f src2:f len:16
197 float_cgt: dest:i src1:f src2:f len:16
198 float_cgt_un: dest:i src1:f src2:f len:20
199 float_clt: dest:i src1:f src2:f len:16
200 float_clt_un: dest:i src1:f src2:f len:20
201 float_cneq: dest:y src1:f src2:f len:20
202 float_cge: dest:y src1:f src2:f len:20
203 float_cle: dest:y src1:f src2:f len:20
204 float_conv_to_u: dest:i src1:f len:36
207 rmove: dest:f src1:f len:4
208 r4_conv_to_i1: dest:i src1:f len:88
209 r4_conv_to_i2: dest:i src1:f len:88
210 r4_conv_to_i4: dest:i src1:f len:88
211 r4_conv_to_u1: dest:i src1:f len:88
212 r4_conv_to_u2: dest:i src1:f len:88
213 r4_conv_to_u4: dest:i src1:f len:88
214 r4_conv_to_r4: dest:f src1:f len:16
215 r4_conv_to_r8: dest:f src1:f len:16
216 r4_add: dest:f src1:f src2:f len:4
217 r4_sub: dest:f src1:f src2:f len:4
218 r4_mul: dest:f src1:f src2:f len:4
219 r4_div: dest:f src1:f src2:f len:4
220 r4_rem: dest:f src1:f src2:f len:16
221 r4_neg: dest:f src1:f len:4
222 r4_ceq: dest:i src1:f src2:f len:16
223 r4_cgt: dest:i src1:f src2:f len:16
224 r4_cgt_un: dest:i src1:f src2:f len:20
225 r4_clt: dest:i src1:f src2:f len:16
226 r4_clt_un: dest:i src1:f src2:f len:20
227 r4_cneq: dest:y src1:f src2:f len:20
228 r4_cge: dest:y src1:f src2:f len:20
229 r4_cle: dest:y src1:f src2:f len:20
231 setfret: src1:f len:12
232 aot_const: dest:i len:16
233 objc_get_selector: dest:i len:32
234 sqrt: dest:f src1:f len:4
235 adc: dest:i src1:i src2:i len:4
236 addcc: dest:i src1:i src2:i len:4
237 subcc: dest:i src1:i src2:i len:4
238 adc_imm: dest:i src1:i len:12
239 addcc_imm: dest:i src1:i len:12
240 subcc_imm: dest:i src1:i len:12
241 sbb: dest:i src1:i src2:i len:4
242 sbb_imm: dest:i src1:i len:12
244 bigmul: len:8 dest:l src1:i src2:i
245 bigmul_un: len:8 dest:l src1:i src2:i
246 tls_get: len:24 dest:i clob:c
247 tls_get_reg: len:28 dest:i src1:i clob:c
248 tls_set: len:24 src1:i clob:c
249 tls_set_reg: len:28 src1:i src2:i clob:c
252 int_add: dest:i src1:i src2:i len:4
253 int_sub: dest:i src1:i src2:i len:4
254 int_mul: dest:i src1:i src2:i len:4
255 int_div: dest:i src1:i src2:i len:4
256 int_div_un: dest:i src1:i src2:i len:4
257 int_rem: dest:i src1:i src2:i len:8
258 int_rem_un: dest:i src1:i src2:i len:8
259 int_and: dest:i src1:i src2:i len:4
260 int_or: dest:i src1:i src2:i len:4
261 int_xor: dest:i src1:i src2:i len:4
262 int_shl: dest:i src1:i src2:i len:4
263 int_shr: dest:i src1:i src2:i len:4
264 int_shr_un: dest:i src1:i src2:i len:4
265 int_neg: dest:i src1:i len:4
266 int_not: dest:i src1:i len:4
267 int_conv_to_i1: dest:i src1:i len:8
268 int_conv_to_i2: dest:i src1:i len:8
269 int_conv_to_i4: dest:i src1:i len:4
270 int_conv_to_r4: dest:f src1:i len:84
271 int_conv_to_r8: dest:f src1:i len:84
272 int_conv_to_u4: dest:i src1:i
273 int_conv_to_r_un: dest:f src1:i len:56
274 int_conv_to_u2: dest:i src1:i len:8
275 int_conv_to_u1: dest:i src1:i len:4
286 int_add_ovf: dest:i src1:i src2:i len:16
287 int_add_ovf_un: dest:i src1:i src2:i len:16
288 int_mul_ovf: dest:i src1:i src2:i len:16
289 int_mul_ovf_un: dest:i src1:i src2:i len:16
290 int_sub_ovf: dest:i src1:i src2:i len:16
291 int_sub_ovf_un: dest:i src1:i src2:i len:16
292 add_ovf_carry: dest:i src1:i src2:i len:16
293 sub_ovf_carry: dest:i src1:i src2:i len:16
294 add_ovf_un_carry: dest:i src1:i src2:i len:16
295 sub_ovf_un_carry: dest:i src1:i src2:i len:16
297 arm_rsbs_imm: dest:i src1:i len:4
298 arm_rsc_imm: dest:i src1:i len:4
301 dummy_use: src1:i len:0
303 dummy_iconst: dest:i len:0
304 dummy_r8const: dest:f len:0
306 not_null: src1:i len:0
308 int_adc: dest:i src1:i src2:i len:4
309 int_addcc: dest:i src1:i src2:i len:4
310 int_subcc: dest:i src1:i src2:i len:4
311 int_sbb: dest:i src1:i src2:i len:4
312 int_adc_imm: dest:i src1:i len:12
313 int_sbb_imm: dest:i src1:i len:12
315 int_add_imm: dest:i src1:i len:12
316 int_sub_imm: dest:i src1:i len:12
317 int_mul_imm: dest:i src1:i len:12
318 int_div_imm: dest:i src1:i len:20
319 int_div_un_imm: dest:i src1:i len:12
320 int_rem_imm: dest:i src1:i len:28
321 int_rem_un_imm: dest:i src1:i len:16
322 int_and_imm: dest:i src1:i len:12
323 int_or_imm: dest:i src1:i len:12
324 int_xor_imm: dest:i src1:i len:12
325 int_shl_imm: dest:i src1:i len:8
326 int_shr_imm: dest:i src1:i len:8
327 int_shr_un_imm: dest:i src1:i len:8
329 int_ceq: dest:i len:12
330 int_cgt: dest:i len:12
331 int_cgt_un: dest:i len:12
332 int_clt: dest:i len:12
333 int_clt_un: dest:i len:12
335 int_cneq: dest:i len:12
336 int_cge: dest:i len:12
337 int_cle: dest:i len:12
338 int_cge_un: dest:i len:12
339 int_cle_un: dest:i len:12
342 cond_exc_ine_un: len:16
344 cond_exc_ilt_un: len:16
346 cond_exc_igt_un: len:16
348 cond_exc_ige_un: len:16
350 cond_exc_ile_un: len:16
356 icompare: src1:i src2:i len:4
357 icompare_imm: src1:i len:12
359 long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
361 vcall2: len:64 clob:c
362 vcall2_reg: src1:i len:64 clob:c
363 vcall2_membase: src1:b len:64 clob:c
364 dyn_call: src1:i src2:i len:136 clob:c
366 # This is different from the original JIT opcodes
378 liverange_start: len:0
380 gc_liveness_def: len:0
381 gc_liveness_use: len:0
382 gc_spill_slot_liveness_def: len:0
383 gc_param_slot_liveness_def: len:0
384 gc_safe_point: clob:c src1:i len:40
386 atomic_add_i4: dest:i src1:i src2:i len:64
387 atomic_exchange_i4: dest:i src1:i src2:i len:64
388 atomic_cas_i4: dest:i src1:i src2:i src3:i len:64
389 memory_barrier: len:8 clob:a
390 atomic_load_i1: dest:i src1:b len:28
391 atomic_load_u1: dest:i src1:b len:28
392 atomic_load_i2: dest:i src1:b len:28
393 atomic_load_u2: dest:i src1:b len:28
394 atomic_load_i4: dest:i src1:b len:28
395 atomic_load_u4: dest:i src1:b len:28
396 atomic_load_r4: dest:f src1:b len:80
397 atomic_load_r8: dest:f src1:b len:32
398 atomic_store_i1: dest:b src1:i len:28
399 atomic_store_u1: dest:b src1:i len:28
400 atomic_store_i2: dest:b src1:i len:28
401 atomic_store_u2: dest:b src1:i len:28
402 atomic_store_i4: dest:b src1:i len:28
403 atomic_store_u4: dest:b src1:i len:28
404 atomic_store_r4: dest:b src1:f len:80
405 atomic_store_r8: dest:b src1:f len:32
407 generic_class_init: src1:a len:44 clob:c