1 # arm cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
19 # g floating point register returned in r0:r1 for soft-float mode
21 # len:number describe the maximun length in bytes of the instruction
22 # number is a positive integer
24 # cost:number describe how many cycles are needed to complete the instruction (unused)
26 # clob:spec describe if the instruction clobbers registers or has special needs
28 # spec can be one of the following characters:
29 # c clobbers caller-save registers
30 # r 'reserves' the destination register until a later instruction unreserves it
31 # used mostly to set output registers in function calls
33 # flags:spec describe if the instruction uses or sets the flags (unused)
35 # spec can be one of the following chars:
38 # m uses and modifies the flags
40 # res:spec describe what units are used in the processor (unused)
42 # delay: describe delay slots (unused)
44 # the required specifiers are: len, clob (if registers are clobbered), the registers
45 # specifiers if the registers are actually used, flags (when scheduling is implemented).
47 # See the code in mini-x86.c for more details on how the specifiers are used.
58 rethrow: src1:i len:20
62 endfilter: src1:i len:16
64 ckfinite: dest:f src1:f len:64
70 localloc: dest:i src1:i len:60
71 compare: src1:i src2:i len:4
72 compare_imm: src1:i len:12
73 fcompare: src1:f src2:f len:12
74 oparglist: src1:i len:12
77 setret: dest:a src1:i len:4
78 setlret: src1:i src2:i len:12
79 checkthis: src1:b len:4
80 call: dest:a clob:c len:20
81 call_reg: dest:a src1:i len:8 clob:c
82 call_membase: dest:a src1:b len:12 clob:c
83 voidcall: len:20 clob:c
84 voidcall_reg: src1:i len:8 clob:c
85 voidcall_membase: src1:b len:12 clob:c
86 fcall: dest:g len:20 clob:c
87 fcall_reg: dest:g src1:i len:8 clob:c
88 fcall_membase: dest:g src1:b len:12 clob:c
89 lcall: dest:l len:20 clob:c
90 lcall_reg: dest:l src1:i len:8 clob:c
91 lcall_membase: dest:l src1:b len:12 clob:c
93 vcall_reg: src1:i len:8 clob:c
94 vcall_membase: src1:b len:12 clob:c
96 r4const: dest:f len:20
97 r8const: dest:f len:20
99 store_membase_imm: dest:b len:20
100 store_membase_reg: dest:b src1:i len:20
101 storei1_membase_imm: dest:b len:20
102 storei1_membase_reg: dest:b src1:i len:12
103 storei2_membase_imm: dest:b len:20
104 storei2_membase_reg: dest:b src1:i len:12
105 storei4_membase_imm: dest:b len:20
106 storei4_membase_reg: dest:b src1:i len:20
107 storei8_membase_imm: dest:b
108 storei8_membase_reg: dest:b src1:i
109 storer4_membase_reg: dest:b src1:f len:12
110 storer8_membase_reg: dest:b src1:f len:12
111 store_memindex: dest:b src1:i src2:i len:4
112 storei1_memindex: dest:b src1:i src2:i len:4
113 storei2_memindex: dest:b src1:i src2:i len:4
114 storei4_memindex: dest:b src1:i src2:i len:4
115 load_membase: dest:i src1:b len:20
116 loadi1_membase: dest:i src1:b len:4
117 loadu1_membase: dest:i src1:b len:4
118 loadi2_membase: dest:i src1:b len:4
119 loadu2_membase: dest:i src1:b len:4
120 loadi4_membase: dest:i src1:b len:4
121 loadu4_membase: dest:i src1:b len:4
122 loadi8_membase: dest:i src1:b
123 loadr4_membase: dest:f src1:b len:4
124 loadr8_membase: dest:f src1:b len:20
125 load_memindex: dest:i src1:b src2:i len:4
126 loadi1_memindex: dest:i src1:b src2:i len:4
127 loadu1_memindex: dest:i src1:b src2:i len:4
128 loadi2_memindex: dest:i src1:b src2:i len:4
129 loadu2_memindex: dest:i src1:b src2:i len:4
130 loadi4_memindex: dest:i src1:b src2:i len:4
131 loadu4_memindex: dest:i src1:b src2:i len:4
132 loadu4_mem: dest:i len:8
133 move: dest:i src1:i len:4
134 fmove: dest:f src1:f len:4
135 add_imm: dest:i src1:i len:12
136 sub_imm: dest:i src1:i len:12
137 mul_imm: dest:i src1:i len:12
138 div_imm: dest:i src1:i src2:i len:20
139 div_un_imm: dest:i src1:i src2:i len:12
140 rem_imm: dest:i src1:i src2:i len:28
141 rem_un_imm: dest:i src1:i src2:i len:16
142 and_imm: dest:i src1:i len:12
143 or_imm: dest:i src1:i len:12
144 xor_imm: dest:i src1:i len:12
145 shl_imm: dest:i src1:i len:8
146 shr_imm: dest:i src1:i len:8
147 shr_un_imm: dest:i src1:i len:8
149 cond_exc_ne_un: len:8
151 cond_exc_lt_un: len:8
153 cond_exc_gt_un: len:8
155 cond_exc_ge_un: len:8
157 cond_exc_le_un: len:8
162 #float_beq: src1:f src2:f len:20
163 #float_bne_un: src1:f src2:f len:20
164 #float_blt: src1:f src2:f len:20
165 #float_blt_un: src1:f src2:f len:20
166 #float_bgt: src1:f src2:f len:20
167 #float_bgt_un: src1:f src2:f len:20
168 #float_bge: src1:f src2:f len:20
169 #float_bge_un: src1:f src2:f len:20
170 #float_ble: src1:f src2:f len:20
171 #float_ble_un: src1:f src2:f len:20
172 float_add: dest:f src1:f src2:f len:4
173 float_sub: dest:f src1:f src2:f len:4
174 float_mul: dest:f src1:f src2:f len:4
175 float_div: dest:f src1:f src2:f len:4
176 float_div_un: dest:f src1:f src2:f len:4
177 float_rem: dest:f src1:f src2:f len:16
178 float_rem_un: dest:f src1:f src2:f len:16
179 float_neg: dest:f src1:f len:4
180 float_not: dest:f src1:f len:4
181 float_conv_to_i1: dest:i src1:f len:40
182 float_conv_to_i2: dest:i src1:f len:40
183 float_conv_to_i4: dest:i src1:f len:40
184 float_conv_to_i8: dest:l src1:f len:40
185 float_conv_to_r4: dest:f src1:f len:4
186 float_conv_to_u4: dest:i src1:f len:40
187 float_conv_to_u8: dest:l src1:f len:40
188 float_conv_to_u2: dest:i src1:f len:40
189 float_conv_to_u1: dest:i src1:f len:40
190 float_conv_to_i: dest:i src1:f len:40
191 float_ceq: dest:i src1:f src2:f len:16
192 float_cgt: dest:i src1:f src2:f len:16
193 float_cgt_un: dest:i src1:f src2:f len:20
194 float_clt: dest:i src1:f src2:f len:16
195 float_clt_un: dest:i src1:f src2:f len:20
196 float_conv_to_u: dest:i src1:f len:36
197 aot_const: dest:i len:16
198 sqrt: dest:f src1:f len:4
199 adc: dest:i src1:i src2:i len:4
200 addcc: dest:i src1:i src2:i len:4
201 subcc: dest:i src1:i src2:i len:4
202 adc_imm: dest:i src1:i len:12
203 addcc_imm: dest:i src1:i len:12
204 subcc_imm: dest:i src1:i len:12
205 sbb: dest:i src1:i src2:i len:4
206 sbb_imm: dest:i src1:i len:12
208 bigmul: len:8 dest:l src1:i src2:i
209 bigmul_un: len:8 dest:l src1:i src2:i
210 tls_get: len:8 dest:i
213 int_add: dest:i src1:i src2:i len:4
214 int_sub: dest:i src1:i src2:i len:4
215 int_mul: dest:i src1:i src2:i len:4
216 int_div: dest:i src1:i src2:i len:40
217 int_div_un: dest:i src1:i src2:i len:16
218 int_rem: dest:i src1:i src2:i len:48
219 int_rem_un: dest:i src1:i src2:i len:24
220 int_and: dest:i src1:i src2:i len:4
221 int_or: dest:i src1:i src2:i len:4
222 int_xor: dest:i src1:i src2:i len:4
223 int_shl: dest:i src1:i src2:i len:4
224 int_shr: dest:i src1:i src2:i len:4
225 int_shr_un: dest:i src1:i src2:i len:4
226 int_neg: dest:i src1:i len:4
227 int_not: dest:i src1:i len:4
228 int_conv_to_i1: dest:i src1:i len:8
229 int_conv_to_i2: dest:i src1:i len:8
230 int_conv_to_i4: dest:i src1:i len:4
231 int_conv_to_r4: dest:f src1:i len:36
232 int_conv_to_r8: dest:f src1:i len:36
233 int_conv_to_u4: dest:i src1:i
234 int_conv_to_r_un: dest:f src1:i len:56
235 int_conv_to_u2: dest:i src1:i len:8
236 int_conv_to_u1: dest:i src1:i len:4
247 int_add_ovf: dest:i src1:i src2:i len:16
248 int_add_ovf_un: dest:i src1:i src2:i len:16
249 int_mul_ovf: dest:i src1:i src2:i len:16
250 int_mul_ovf_un: dest:i src1:i src2:i len:16
251 int_sub_ovf: dest:i src1:i src2:i len:16
252 int_sub_ovf_un: dest:i src1:i src2:i len:16
253 add_ovf_carry: dest:i src1:i src2:i len:16
254 sub_ovf_carry: dest:i src1:i src2:i len:16
255 add_ovf_un_carry: dest:i src1:i src2:i len:16
256 sub_ovf_un_carry: dest:i src1:i src2:i len:16
258 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
260 arm_rsbs_imm: dest:i src1:i len:4
261 arm_rsc_imm: dest:i src1:i len:4
267 not_null: src1:i len:0
269 int_adc: dest:i src1:i src2:i len:4
270 int_addcc: dest:i src1:i src2:i len:4
271 int_subcc: dest:i src1:i src2:i len:4
272 int_sbb: dest:i src1:i src2:i len:4
273 int_adc_imm: dest:i src1:i len:12
274 int_sbb_imm: dest:i src1:i len:12
276 int_add_imm: dest:i src1:i len:12
277 int_sub_imm: dest:i src1:i len:12
278 int_mul_imm: dest:i src1:i len:12
279 int_div_imm: dest:i src1:i len:20
280 int_div_un_imm: dest:i src1:i len:12
281 int_rem_imm: dest:i src1:i len:28
282 int_rem_un_imm: dest:i src1:i len:16
283 int_and_imm: dest:i src1:i len:12
284 int_or_imm: dest:i src1:i len:12
285 int_xor_imm: dest:i src1:i len:12
286 int_shl_imm: dest:i src1:i len:8
287 int_shr_imm: dest:i src1:i len:8
288 int_shr_un_imm: dest:i src1:i len:8
290 int_ceq: dest:i len:12
291 int_cgt: dest:i len:12
292 int_cgt_un: dest:i len:12
293 int_clt: dest:i len:12
294 int_clt_un: dest:i len:12
297 cond_exc_ine_un: len:8
299 cond_exc_ilt_un: len:8
301 cond_exc_igt_un: len:8
303 cond_exc_ige_un: len:8
305 cond_exc_ile_un: len:8
311 icompare: src1:i src2:i len:4
312 icompare_imm: src1:i len:12
314 long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
316 vcall2: len:20 clob:c
317 vcall2_reg: src1:i len:8 clob:c
318 vcall2_membase: src1:b len:12 clob:c
320 # This is different from the original JIT opcodes