1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
20 # l long reg (forced eax:edx)
21 # L long reg (dynamic)
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer. If the length is not specified
25 # it defaults to zero. But lengths are only checked if the given opcode
26 # is encountered during compilation. Some opcodes, like CONV_U4 are
27 # transformed into other opcodes in the brg files, so they do not show up
28 # during code generation.
30 # cost:number describe how many cycles are needed to complete the instruction (unused)
32 # clob:spec describe if the instruction clobbers registers or has special needs
34 # spec can be one of the following characters:
35 # c clobbers caller-save registers
36 # 1 clobbers the first source register
38 # d EAX and EDX are clobbered
39 # s the src2 operand needs to be in ECX (shift opcodes)
40 # x both the source operands are clobbered (xchg)
42 # flags:spec describe if the instruction uses or sets the flags (unused)
44 # spec can be one of the following chars:
47 # m uses and modifies the flags
49 # res:spec describe what units are used in the processor (unused)
51 # delay: describe delay slots (unused)
53 # the required specifiers are: len, clob (if registers are clobbered), the registers
54 # specifiers if the registers are actually used, flags (when scheduling is implemented).
56 # See the code in mini-x86.c for more details on how the specifiers are used.
78 ldind.i1: dest:i len:7
79 ldind.u1: dest:i len:7
80 ldind.i2: dest:i len:7
81 ldind.u2: dest:i len:7
82 ldind.i4: dest:i len:9
83 ldind.u4: dest:i len:7
88 ldind.ref: dest:i len:7
89 stind.ref: src1:b src2:i
90 stind.i1: src1:b src2:i
91 stind.i2: src1:b src2:i
92 stind.i4: src1:b src2:i
94 stind.r4: dest:f src1:b
95 stind.r8: dest:f src1:b
96 add: dest:i src1:i src2:i len:3 clob:1
97 sub: dest:i src1:i src2:i len:3 clob:1
98 mul: dest:i src1:i src2:i len:4 clob:1
99 div: dest:a src1:i src2:i len:16 clob:d
100 div.un: dest:a src1:i src2:i len:16 clob:d
101 rem: dest:d src1:i src2:i len:16 clob:d
102 rem.un: dest:d src1:i src2:i len:16 clob:d
103 and: dest:i src1:i src2:i len:3 clob:1
104 or: dest:i src1:i src2:i len:3 clob:1
105 xor: dest:i src1:i src2:i len:3 clob:1
106 shl: dest:i src1:i src2:i clob:s len:3
107 shr: dest:i src1:i src2:i clob:s len:3
108 shr.un: dest:i src1:i src2:i clob:s len:3
109 neg: dest:i src1:i len:3 clob:1
110 not: dest:i src1:i len:3 clob:1
111 conv.i1: dest:i src1:i len:4
112 conv.i2: dest:i src1:i len:4
113 conv.i4: dest:i src1:i len:3
115 conv.r4: dest:f src1:i len:8
116 conv.r8: dest:f src1:i len:8
117 conv.u4: dest:i src1:i
174 conv.ovf.u4: dest:i src1:i len:4
178 ckfinite: dest:f src1:f len:32
181 conv.u2: dest:i src1:i len:4
182 conv.u1: dest:i src1:i len:4
183 conv.i: dest:i src1:i len:4
188 mul.ovf: dest:i src1:i src2:i clob:1 len:10
189 # this opcode is handled specially in the code generator
190 mul.ovf.un: dest:i src1:i src2:i len:17
197 conv.u: dest:i src1:i len:4
220 localloc: dest:i src1:i len:74
243 compare: src1:i src2:i len:3
244 lcompare: src1:i src2:i len:3
245 icompare: src1:i src2:i len:3
246 compare_imm: src1:i len:7
247 icompare_imm: src1:i len:7
248 fcompare: src1:f src2:f clob:a len:12
251 oparglist: src1:b len:11
255 setret: dest:a src1:i len:3
256 setlret: dest:l src1:i src2:i len:5
257 checkthis: src1:b len:5
258 call: dest:a clob:c len:18
260 voidcall: clob:c len:18
261 voidcall_reg: src1:i clob:c len:12
262 voidcall_membase: src1:b clob:c len:17
263 fcall: dest:f len:18 clob:c
264 fcall_reg: dest:f src1:i len:12 clob:c
265 fcall_membase: dest:f src1:b len:17 clob:c
266 lcall: dest:l len:18 clob:c
267 lcall_reg: dest:l src1:i len:12 clob:c
268 lcall_membase: dest:l src1:b len:17 clob:c
270 vcall_reg: src1:i len:12 clob:c
271 vcall_membase: src1:b len:17 clob:c
272 call_reg: dest:a src1:i len:12 clob:c
273 call_membase: dest:a src1:b len:17 clob:c
275 iconst: dest:i len:10
276 i8const: dest:i len:17
277 r4const: dest:f len:13
278 r8const: dest:f len:13
283 store_membase_imm: dest:b len:15
284 store_membase_reg: dest:b src1:i len:8
285 storei8_membase_reg: dest:b src1:i len:8
286 storei1_membase_imm: dest:b len:11
287 storei1_membase_reg: dest:b src1:i len:8
288 storei2_membase_imm: dest:b len:12
289 storei2_membase_reg: dest:b src1:i len:8
290 storei4_membase_imm: dest:b len:11
291 storei4_membase_reg: dest:b src1:i len:8
292 storei8_membase_imm: dest:b len:17
293 storer4_membase_reg: dest:b src1:f len:8
294 storer8_membase_reg: dest:b src1:f len:7
295 load_membase: dest:i src1:b len:14
296 loadi1_membase: dest:i src1:b len:8
297 loadu1_membase: dest:i src1:b len:8
298 loadi2_membase: dest:i src1:b len:8
299 loadu2_membase: dest:i src1:b len:8
300 loadi4_membase: dest:i src1:b len:7
301 loadu4_membase: dest:i src1:b len:7
302 loadi8_membase: dest:i src1:b len:17
303 loadr4_membase: dest:f src1:b len:7
304 loadr8_membase: dest:f src1:b len:7
305 loadr8_spill_membase: src1:b len:9
306 loadu4_mem: dest:i len:10
307 move: dest:i src1:i len:4
308 setreg: dest:i src1:i len:4
309 add_imm: dest:i src1:i len:7 clob:1
310 sub_imm: dest:i src1:i len:7 clob:1
311 mul_imm: dest:i src1:i len:7
312 # there is no actual support for division or reminder by immediate
313 # we simulate them, though (but we need to change the burg rules
314 # to allocate a symbolic reg for src2)
315 div_imm: dest:a src1:i src2:i len:16 clob:d
316 div_un_imm: dest:a src1:i src2:i len:16 clob:d
317 rem_imm: dest:d src1:i src2:i len:16 clob:d
318 rem_un_imm: dest:d src1:i src2:i len:16 clob:d
319 and_imm: dest:i src1:i len:8 clob:1
320 or_imm: dest:i src1:i len:8 clob:1
321 xor_imm: dest:i src1:i len:8 clob:1
322 shl_imm: dest:i src1:i len:8 clob:1
323 shr_imm: dest:i src1:i len:8 clob:1
324 shr_un_imm: dest:i src1:i len:8 clob:1
326 cond_exc_ne_un: len:7
328 cond_exc_lt_un: len:7
330 cond_exc_gt_un: len:7
332 cond_exc_ge_un: len:7
334 cond_exc_le_un: len:7
349 long_shl: dest:i src1:i src2:i clob:s len:31
350 long_shr: dest:i src1:i src2:i clob:s len:32
351 long_shr_un: dest:i src1:i src2:i clob:s len:32
365 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
373 long_conv_to_ovf_i1_un:
374 long_conv_to_ovf_i2_un:
375 long_conv_to_ovf_i4_un:
376 long_conv_to_ovf_i8_un:
377 long_conv_to_ovf_u1_un:
378 long_conv_to_ovf_u2_un:
379 long_conv_to_ovf_u4_un:
380 long_conv_to_ovf_u8_un:
381 long_conv_to_ovf_i_un:
382 long_conv_to_ovf_u_un:
396 long_conv_to_r_un: dest:f src1:i src2:i len:47
398 long_shr_imm: dest:i src1:i len:11
399 long_shr_un_imm: dest:i src1:i len:11
400 long_shl_imm: dest:i src1:i len:11
423 float_add: dest:f src1:f src2:f len:3
424 float_sub: dest:f src1:f src2:f len:3
425 float_mul: dest:f src1:f src2:f len:3
426 float_div: dest:f src1:f src2:f len:3
427 float_div_un: dest:f src1:f src2:f len:3
428 float_rem: dest:f src1:f src2:f len:18
429 float_rem_un: dest:f src1:f src2:f len:18
430 float_neg: dest:f src1:f len:3
431 float_not: dest:f src1:f len:3
432 float_conv_to_i1: dest:i src1:f len:49
433 float_conv_to_i2: dest:i src1:f len:49
434 float_conv_to_i4: dest:i src1:f len:49
435 float_conv_to_i8: dest:i src1:f len:49
438 float_conv_to_u4: dest:i src1:f len:49
439 float_conv_to_u8: dest:i src1:f len:49
440 float_conv_to_u2: dest:i src1:f len:49
441 float_conv_to_u1: dest:i src1:f len:49
442 float_conv_to_i: dest:i src1:f len:49
443 float_conv_to_ovf_i: dest:a src1:f len:40
444 float_conv_to_ovd_u: dest:a src1:f len:40
451 float_conv_to_ovf_i1_un:
452 float_conv_to_ovf_i2_un:
453 float_conv_to_ovf_i4_un:
454 float_conv_to_ovf_i8_un:
455 float_conv_to_ovf_u1_un:
456 float_conv_to_ovf_u2_un:
457 float_conv_to_ovf_u4_un:
458 float_conv_to_ovf_u8_un:
459 float_conv_to_ovf_i_un:
460 float_conv_to_ovf_u_un:
461 float_conv_to_ovf_i1:
462 float_conv_to_ovf_u1:
463 float_conv_to_ovf_i2:
464 float_conv_to_ovf_u2:
465 float_conv_to_ovf_i4:
466 float_conv_to_ovf_u4:
467 float_conv_to_ovf_i8:
468 float_conv_to_ovf_u8:
469 float_ceq: dest:i src1:f src2:f len:35
470 float_cgt: dest:i src1:f src2:f len:35
471 float_cgt_un: dest:i src1:f src2:f len:47
472 float_clt: dest:i src1:f src2:f len:35
473 float_clt_un: dest:i src1:f src2:f len:42
474 float_conv_to_u: dest:i src1:f len:46
476 aot_const: dest:i len:6
477 x86_test_null: src1:i len:5
478 x86_compare_membase_reg: src1:b src2:i len:7
479 x86_compare_membase_imm: src1:b len:12
480 x86_compare_reg_membase: src1:i src2:b len:7
481 x86_inc_reg: dest:i src1:i clob:1 len:3
482 x86_inc_membase: src1:b len:7
483 x86_dec_reg: dest:i src1:i clob:1 len:3
484 x86_dec_membase: src1:b len:7
485 x86_add_membase_imm: src1:b len:12
486 x86_sub_membase_imm: src1:b len:12
487 x86_push: src1:i len:3
489 x86_push_membase: src1:b len:7
490 x86_push_obj: src1:b len:40
491 x86_lea: dest:i src1:i src2:i len:8
492 x86_lea_membase: dest:i src1:i len:11
493 x86_xchg: src1:i src2:i clob:x len:2
494 x86_fpop: src1:f len:3
495 x86_fp_load_i8: dest:f src1:b len:8
496 x86_fp_load_i4: dest:f src1:b len:8
497 x86_seteq_membase: src1:b len:8
498 x86_add_membase: dest:i src1:i src2:b clob:1 len:12
499 x86_sub_membase: dest:i src1:i src2:b clob:1 len:12
500 x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
501 amd64_icompare_membase_reg: src1:b src2:i len:7
502 amd64_icompare_membase_imm: src1:b len:12
503 amd64_icompare_reg_membase: src1:i src2:b len:7
504 adc: dest:i src1:i src2:i len:3 clob:1
505 addcc: dest:i src1:i src2:i len:3 clob:1
506 subcc: dest:i src1:i src2:i len:3 clob:1
507 adc_imm: dest:i src1:i len:7 clob:1
508 sbb: dest:i src1:i src2:i len:3 clob:1
509 sbb_imm: dest:i src1:i len:7 clob:1
511 sin: dest:f src1:f len:7
512 cos: dest:f src1:f len:7
513 abs: dest:f src1:f len:3
514 tan: dest:f src1:f len:59
515 atan: dest:f src1:f len:9
516 sqrt: dest:f src1:f len:3
517 op_bigmul: len:3 dest:l src1:a src2:i
518 op_bigmul_un: len:3 dest:l src1:a src2:i
519 sext_i1: dest:i src1:i len:4
520 sext_i2: dest:i src1:i len:4
524 int_add: dest:i src1:i src2:i clob:1 len:64
525 int_sub: dest:i src1:i src2:i clob:1 len:64
526 int_mul: dest:i src1:i src2:i clob:1 len:64
527 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
528 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
529 int_div: dest:a src1:i src2:i clob:d len:64
530 int_div_un: dest:a src1:i src2:i clob:d len:64
531 int_rem: dest:d src1:i src2:i clob:d len:64
532 int_rem_un: dest:d src1:i src2:i clob:d len:64
533 int_and: dest:i src1:i src2:i clob:1 len:64
534 int_or: dest:i src1:i src2:i clob:1 len:64
535 int_xor: dest:i src1:i src2:i clob:1 len:64
536 int_shl: dest:i src1:i src2:i clob:s len:64
537 int_shr: dest:i src1:i src2:i clob:s len:64
538 int_shr_un: dest:i src1:i src2:i clob:s len:64
539 int_adc: dest:i src1:i src2:i clob:1 len:64
540 int_adc_imm: dest:i src1:i clob:1 len:64
541 int_sbb: dest:i src1:i src2:i clob:1 len:64
542 int_sbb_imm: dest:i src1:i clob:1 len:64
543 int_addcc: dest:i src1:i src2:i clob:1 len:64
544 int_subcc: dest:i src1:i src2:i clob:1 len:64
545 int_add_imm: dest:i src1:i clob:1 len:64
546 int_sub_imm: dest:i src1:i clob:1 len:64
547 int_mul_imm: dest:i src1:i clob:1 len:64
548 int_div_imm: dest:a src1:i clob:d len:64
549 int_div_un_imm: dest:a src1:i clob:d len:64
550 int_rem_imm: dest:d src1:i clob:d len:64
551 int_rem_un_imm: dest:d src1:i clob:d len:64
552 int_and_imm: dest:i src1:i clob:1 len:64
553 int_or_imm: dest:i src1:i clob:1 len:64
554 int_xor_imm: dest:i src1:i clob:1 len:64
555 int_shl_imm: dest:i src1:i clob:1 len:64
556 int_shr_imm: dest:i src1:i clob:1 len:64
557 int_shr_un_imm: dest:i src1:i clob:1 len:64
558 int_neg: dest:i src1:i clob:1 len:64
559 int_not: dest:i src1:i clob:1 len:64
560 int_ceq: dest:i len:64
561 int_cgt: dest:i len:64
562 int_cgt_un: dest:i len:64
563 int_clt: dest:i len:64
564 int_clt_un: dest:i len:64