1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
15 # b base register (used in address references)
16 # f floating point register
19 # l long reg (forced eax:edx)
21 # c register which can be used as a byte register (RAX..RDX)
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer. If the length is not specified
25 # it defaults to zero. But lengths are only checked if the given opcode
26 # is encountered during compilation. Some opcodes, like CONV_U4 are
27 # transformed into other opcodes in the brg files, so they do not show up
28 # during code generation.
30 # cost:number describe how many cycles are needed to complete the instruction (unused)
32 # clob:spec describe if the instruction clobbers registers or has special needs
34 # c clobbers caller-save registers
35 # 1 clobbers the first source register
38 # x both the source operands are clobbered (xchg)
41 # flags:spec describe if the instruction uses or sets the flags (unused)
45 # m uses and modifies the flags
47 # res:spec describe what units are used in the processor (unused)
49 # delay: describe delay slots (unused)
51 # the required specifiers are: len, clob (if registers are clobbered), the registers
52 # specifiers if the registers are actually used, flags (when scheduling is implemented).
54 # See the code in mini-x86.c for more details on how the specifiers are used.
70 ldind.i1: dest:i len:8
71 ldind.u1: dest:i len:8
72 ldind.i2: dest:i len:8
73 ldind.u2: dest:i len:8
74 ldind.i4: dest:i len:9
75 ldind.u4: dest:i len:8
77 ldind.ref: dest:i len:8
78 stind.ref: src1:b src2:i
79 stind.i1: src1:b src2:i
80 stind.i2: src1:b src2:i
81 stind.i4: src1:b src2:i
82 stind.r4: dest:f src1:b
83 stind.r8: dest:f src1:b
84 add: dest:i src1:i src2:i len:3 clob:1
85 sub: dest:i src1:i src2:i len:3 clob:1
86 mul: dest:i src1:i src2:i len:4 clob:1
87 div: dest:a src1:a src2:i len:16 clob:d
88 div.un: dest:a src1:a src2:i len:16 clob:d
89 rem: dest:d src1:a src2:i len:16 clob:a
90 rem.un: dest:d src1:a src2:i len:16 clob:a
91 and: dest:i src1:i src2:i len:3 clob:1
92 or: dest:i src1:i src2:i len:3 clob:1
93 xor: dest:i src1:i src2:i len:3 clob:1
94 shl: dest:i src1:i src2:s clob:1 len:3
95 shr: dest:i src1:i src2:s clob:1 len:3
96 shr.un: dest:i src1:i src2:s clob:1 len:3
97 neg: dest:i src1:i len:3 clob:1
98 not: dest:i src1:i len:3 clob:1
99 conv.i1: dest:i src1:i len:4
100 conv.i2: dest:i src1:i len:4
101 conv.i4: dest:i src1:i len:3
102 conv.i8: dest:i src1:i len:3
103 conv.r4: dest:f src1:i len:9
104 conv.r8: dest:f src1:i len:9
105 conv.u4: dest:i src1:i len:3
106 conv.u8: dest:i src1:i len:3
107 conv.r.un: dest:f src1:i len:8
110 op_rethrow: src1:i len:18
113 op_endfilter: src1:a len:9
115 conv.ovf.i4.un: dest:i src1:i len:16
117 conv.ovf.u4: dest:i src1:i len:15
118 ckfinite: dest:f src1:f len:43
119 conv.u2: dest:i src1:i len:4
120 conv.u1: dest:i src1:i len:4
121 conv.i: dest:i src1:i len:4
122 mul.ovf: dest:i src1:i src2:i clob:1 len:10
123 # this opcode is handled specially in the code generator
124 mul.ovf.un: dest:i src1:i src2:i len:18
125 conv.u: dest:i src1:i len:4
131 localloc: dest:i src1:i len:84
132 compare: src1:i src2:i len:3
133 lcompare: src1:i src2:i len:3
134 icompare: src1:i src2:i len:3
135 compare_imm: src1:i len:13
136 icompare_imm: src1:i len:8
137 fcompare: src1:f src2:f clob:a len:13
138 oparglist: src1:b len:11
141 setret: dest:a src1:i len:3
142 setlret: dest:i src1:i src2:i len:5
143 checkthis: src1:b len:5
144 call: dest:a clob:c len:64
146 voidcall: clob:c len:64
147 voidcall_reg: src1:i clob:c len:64
148 voidcall_membase: src1:b clob:c len:64
149 fcall: dest:f len:64 clob:c
150 fcall_reg: dest:f src1:i len:64 clob:c
151 fcall_membase: dest:f src1:b len:64 clob:c
152 lcall: dest:a len:64 clob:c
153 lcall_reg: dest:a src1:i len:64 clob:c
154 lcall_membase: dest:a src1:b len:64 clob:c
156 vcall_reg: src1:i len:64 clob:c
157 vcall_membase: src1:b len:64 clob:c
158 call_reg: dest:a src1:i len:64 clob:c
159 call_membase: dest:a src1:b len:64 clob:c
160 iconst: dest:i len:10
161 i8const: dest:i len:18
162 r4const: dest:f len:14
163 r8const: dest:f len:9
164 store_membase_imm: dest:b len:15
165 store_membase_reg: dest:b src1:i len:9
166 storei8_membase_reg: dest:b src1:i len:9
167 storei1_membase_imm: dest:b len:11
168 storei1_membase_reg: dest:b src1:c len:9
169 storei2_membase_imm: dest:b len:13
170 storei2_membase_reg: dest:b src1:i len:9
171 storei4_membase_imm: dest:b len:13
172 storei4_membase_reg: dest:b src1:i len:9
173 storei8_membase_imm: dest:b len:18
174 storer4_membase_reg: dest:b src1:f len:15
175 storer8_membase_reg: dest:b src1:f len:10
176 load_membase: dest:i src1:b len:15
177 loadi1_membase: dest:c src1:b len:9
178 loadu1_membase: dest:c src1:b len:9
179 loadi2_membase: dest:i src1:b len:9
180 loadu2_membase: dest:i src1:b len:9
181 loadi4_membase: dest:i src1:b len:9
182 loadu4_membase: dest:i src1:b len:9
183 loadi8_membase: dest:i src1:b len:18
184 loadr4_membase: dest:f src1:b len:16
185 loadr8_membase: dest:f src1:b len:16
186 loadr8_spill_membase: src1:b len:9
187 loadu4_mem: dest:i len:10
188 amd64_loadi8_memindex: dest:i src1:i src2:i len:10
189 move: dest:i src1:i len:4
190 add_imm: dest:i src1:i len:8 clob:1
191 sub_imm: dest:i src1:i len:8 clob:1
192 mul_imm: dest:i src1:i len:11
193 # there is no actual support for division or reminder by immediate
194 # we simulate them, though (but we need to change the burg rules
195 # to allocate a symbolic reg for src2)
196 div_imm: dest:a src1:i src2:i len:16 clob:d
197 div_un_imm: dest:a src1:i src2:i len:16 clob:d
198 rem_imm: dest:d src1:i src2:i len:16 clob:a
199 rem_un_imm: dest:d src1:i src2:i len:16 clob:a
200 and_imm: dest:i src1:i len:8 clob:1
201 or_imm: dest:i src1:i len:8 clob:1
202 xor_imm: dest:i src1:i len:8 clob:1
203 shl_imm: dest:i src1:i len:8 clob:1
204 shr_imm: dest:i src1:i len:8 clob:1
205 shr_un_imm: dest:i src1:i len:8 clob:1
207 cond_exc_ne_un: len:8
209 cond_exc_lt_un: len:8
211 cond_exc_gt_un: len:8
213 cond_exc_ge_un: len:8
215 cond_exc_le_un: len:8
223 long_add: dest:i src1:i src2:i len:3 clob:1
224 long_mul: dest:i src1:i src2:i clob:1 len:4
225 long_mul_imm: dest:i src1:i clob:1 len:12
226 long_div: dest:a src1:a src2:i len:16 clob:d
227 long_div_un: dest:a src1:a src2:i len:16 clob:d
228 long_rem: dest:d src1:a src2:i len:16 clob:a
229 long_rem_un: dest:d src1:a src2:i len:16 clob:a
230 long_and: dest:i src1:i src2:i len:3 clob:1
231 long_or: dest:i src1:i src2:i len:3 clob:1
232 long_xor: dest:i src1:i src2:i len:3 clob:1
233 long_shl: dest:i src1:i src2:s clob:1 len:31
234 long_shr: dest:i src1:i src2:s clob:1 len:32
235 long_shr_un: dest:i src1:i src2:s clob:1 len:32
236 long_min: dest:i src1:i src2:i len:16 clob:1
237 long_max: dest:i src1:i src2:i len:16 clob:1
239 long_conv_to_r4: dest:f src1:i len:8
240 long_conv_to_r8: dest:f src1:i len:8
241 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
242 long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
243 long_mul_ovf_un: dest:i src1:i src2:i len:22
244 long_conv_to_r_un: dest:f src1:i len:64
245 long_shr_imm: dest:i src1:i clob:1 len:11
246 long_shr_un_imm: dest:i src1:i clob:1 len:11
247 long_shl_imm: dest:i src1:i clob:1 len:11
259 float_add: dest:f src1:f src2:f len:5
260 float_sub: dest:f src1:f src2:f len:5
261 float_mul: dest:f src1:f src2:f len:5
262 float_div: dest:f src1:f src2:f len:5
263 float_div_un: dest:f src1:f src2:f len:5
264 float_rem: dest:f src1:f src2:f len:19
265 float_rem_un: dest:f src1:f src2:f len:19
266 float_neg: dest:f src1:f len:23
267 float_not: dest:f src1:f len:3
268 float_conv_to_i1: dest:i src1:f len:49
269 float_conv_to_i2: dest:i src1:f len:49
270 float_conv_to_i4: dest:i src1:f len:49
271 float_conv_to_i8: dest:i src1:f len:49
272 float_conv_to_u4: dest:i src1:f len:49
273 float_conv_to_u8: dest:i src1:f len:49
274 float_conv_to_u2: dest:i src1:f len:49
275 float_conv_to_u1: dest:i src1:f len:49
276 float_conv_to_i: dest:i src1:f len:49
277 float_conv_to_ovf_i: dest:a src1:f len:40
278 float_conv_to_ovd_u: dest:a src1:f len:40
280 float_ceq: dest:i src1:f src2:f len:35
281 float_cgt: dest:i src1:f src2:f len:35
282 float_cgt_un: dest:i src1:f src2:f len:48
283 float_clt: dest:i src1:f src2:f len:35
284 float_clt_un: dest:i src1:f src2:f len:42
285 float_ceq_membase: dest:i src1:f src2:b len:35
286 float_cgt_membase: dest:i src1:f src2:b len:35
287 float_cgt_un_membase: dest:i src1:f src2:b len:48
288 float_clt_membase: dest:i src1:f src2:b len:35
289 float_clt_un_membase: dest:i src1:f src2:b len:42
290 float_conv_to_u: dest:i src1:f len:46
291 fmove: dest:f src1:f len:8
293 aot_const: dest:i len:10
294 x86_test_null: src1:i len:5
295 x86_compare_membase_reg: src1:b src2:i len:9
296 x86_compare_membase_imm: src1:b len:13
297 x86_compare_reg_membase: src1:i src2:b len:8
298 x86_inc_reg: dest:i src1:i clob:1 len:3
299 x86_inc_membase: src1:b len:8
300 x86_dec_reg: dest:i src1:i clob:1 len:3
301 x86_dec_membase: src1:b len:8
302 x86_add_membase_imm: src1:b len:13
303 x86_sub_membase_imm: src1:b len:13
304 x86_push: src1:i len:3
306 x86_push_membase: src1:b len:8
307 x86_push_obj: src1:b len:40
308 x86_lea: dest:i src1:i src2:i len:8
309 x86_lea_membase: dest:i src1:i len:11
310 x86_xchg: src1:i src2:i clob:x len:2
311 x86_fpop: src1:f len:3
312 x86_fp_load_i8: dest:f src1:b len:8
313 x86_fp_load_i4: dest:f src1:b len:8
314 x86_seteq_membase: src1:b len:9
315 x86_add_membase: dest:i src1:i src2:b clob:1 len:13
316 x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
317 x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
318 tls_get: dest:i len:16
319 amd64_test_null: src1:i len:5
320 amd64_icompare_membase_reg: src1:b src2:i len:8
321 amd64_icompare_membase_imm: src1:b len:13
322 amd64_icompare_reg_membase: src1:i src2:b len:8
323 amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
324 amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
325 atomic_add_i4: src1:b src2:i dest:i len:32
326 atomic_add_new_i4: src1:b src2:i dest:i len:32
327 atomic_exchange_i4: src1:b src2:i dest:i len:32
328 atomic_add_i8: src1:b src2:i dest:i len:32
329 atomic_add_new_i8: src1:b src2:i dest:i len:32
330 atomic_exchange_i8: src1:b src2:i dest:i len:32
331 memory_barrier: len:16
332 adc: dest:i src1:i src2:i len:3 clob:1
333 addcc: dest:i src1:i src2:i len:3 clob:1
334 subcc: dest:i src1:i src2:i len:3 clob:1
335 adc_imm: dest:i src1:i len:8 clob:1
336 sbb: dest:i src1:i src2:i len:3 clob:1
337 sbb_imm: dest:i src1:i len:8 clob:1
339 sin: dest:f src1:f len:32
340 cos: dest:f src1:f len:32
341 abs: dest:f src1:f len:32
342 tan: dest:f src1:f len:59
343 atan: dest:f src1:f len:9
344 sqrt: dest:f src1:f len:32
345 op_bigmul: len:3 dest:i src1:a src2:i
346 op_bigmul_un: len:3 dest:i src1:a src2:i
347 sext_i1: dest:i src1:i len:4
348 sext_i2: dest:i src1:i len:4
349 sext_i4: dest:i src1:i len:8
353 int_add: dest:i src1:i src2:i clob:1 len:64
354 int_sub: dest:i src1:i src2:i clob:1 len:64
355 int_mul: dest:i src1:i src2:i clob:1 len:64
356 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
357 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
358 int_div: dest:a src1:a src2:i clob:d len:64
359 int_div_un: dest:a src1:a src2:i clob:d len:64
360 int_rem: dest:d src1:a src2:i clob:a len:64
361 int_rem_un: dest:d src1:a src2:i clob:a len:64
362 int_and: dest:i src1:i src2:i clob:1 len:64
363 int_or: dest:i src1:i src2:i clob:1 len:64
364 int_xor: dest:i src1:i src2:i clob:1 len:64
365 int_shl: dest:i src1:i src2:s clob:1 len:64
366 int_shr: dest:i src1:i src2:s clob:1 len:64
367 int_shr_un: dest:i src1:i src2:s clob:1 len:64
368 int_adc: dest:i src1:i src2:i clob:1 len:64
369 int_adc_imm: dest:i src1:i clob:1 len:64
370 int_sbb: dest:i src1:i src2:i clob:1 len:64
371 int_sbb_imm: dest:i src1:i clob:1 len:64
372 int_addcc: dest:i src1:i src2:i clob:1 len:64
373 int_subcc: dest:i src1:i src2:i clob:1 len:64
374 int_add_imm: dest:i src1:i clob:1 len:64
375 int_sub_imm: dest:i src1:i clob:1 len:64
376 int_mul_imm: dest:i src1:i clob:1 len:64
377 int_div_imm: dest:a src1:i clob:d len:64
378 int_div_un_imm: dest:a src1:i clob:d len:64
379 int_rem_imm: dest:d src1:i clob:a len:64
380 int_rem_un_imm: dest:d src1:i clob:a len:64
381 int_and_imm: dest:i src1:i clob:1 len:64
382 int_or_imm: dest:i src1:i clob:1 len:64
383 int_xor_imm: dest:i src1:i clob:1 len:64
384 int_shl_imm: dest:i src1:i clob:1 len:64
385 int_shr_imm: dest:i src1:i clob:1 len:64
386 int_shr_un_imm: dest:i src1:i clob:1 len:64
387 int_min: dest:i src1:i src2:i len:16 clob:1
388 int_max: dest:i src1:i src2:i len:16 clob:1
390 int_neg: dest:i src1:i clob:1 len:64
391 int_not: dest:i src1:i clob:1 len:64
392 int_ceq: dest:c len:64
393 int_cgt: dest:c len:64
394 int_cgt_un: dest:c len:64
395 int_clt: dest:c len:64
396 int_clt_un: dest:c len:64