1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
20 # l long reg (forced eax:edx)
22 # len:number describe the maximun length in bytes of the instruction
23 # number is a positive integer. If the length is not specified
24 # it defaults to zero. But lengths are only checked if the given opcode
25 # is encountered during compilation. Some opcodes, like CONV_U4 are
26 # transformed into other opcodes in the brg files, so they do not show up
27 # during code generation.
29 # cost:number describe how many cycles are needed to complete the instruction (unused)
31 # clob:spec describe if the instruction clobbers registers or has special needs
33 # spec can be one of the following characters:
34 # c clobbers caller-save registers
35 # 1 clobbers the first source register
37 # d EAX and EDX are clobbered
38 # s the src2 operand needs to be in ECX (shift opcodes)
39 # x both the source operands are clobbered (xchg)
42 # flags:spec describe if the instruction uses or sets the flags (unused)
44 # spec can be one of the following chars:
47 # m uses and modifies the flags
49 # res:spec describe what units are used in the processor (unused)
51 # delay: describe delay slots (unused)
53 # the required specifiers are: len, clob (if registers are clobbered), the registers
54 # specifiers if the registers are actually used, flags (when scheduling is implemented).
56 # See the code in mini-x86.c for more details on how the specifiers are used.
78 ldind.i1: dest:i len:8
79 ldind.u1: dest:i len:8
80 ldind.i2: dest:i len:8
81 ldind.u2: dest:i len:8
82 ldind.i4: dest:i len:9
83 ldind.u4: dest:i len:8
88 ldind.ref: dest:i len:8
89 stind.ref: src1:b src2:i
90 stind.i1: src1:b src2:i
91 stind.i2: src1:b src2:i
92 stind.i4: src1:b src2:i
94 stind.r4: dest:f src1:b
95 stind.r8: dest:f src1:b
96 add: dest:i src1:i src2:i len:3 clob:1
97 sub: dest:i src1:i src2:i len:3 clob:1
98 mul: dest:i src1:i src2:i len:4 clob:1
99 div: dest:a src1:a src2:i len:16 clob:d
100 div.un: dest:a src1:a src2:i len:16 clob:d
101 rem: dest:d src1:a src2:i len:16 clob:d
102 rem.un: dest:d src1:a src2:i len:16 clob:d
103 and: dest:i src1:i src2:i len:3 clob:1
104 or: dest:i src1:i src2:i len:3 clob:1
105 xor: dest:i src1:i src2:i len:3 clob:1
106 shl: dest:i src1:i src2:i clob:s len:3
107 shr: dest:i src1:i src2:i clob:s len:3
108 shr.un: dest:i src1:i src2:i clob:s len:3
109 neg: dest:i src1:i len:3 clob:1
110 not: dest:i src1:i len:3 clob:1
111 conv.i1: dest:i src1:i len:4
112 conv.i2: dest:i src1:i len:4
113 conv.i4: dest:i src1:i len:3
114 conv.i8: dest:i src1:i len:3
115 conv.r4: dest:f src1:i len:9
116 conv.r8: dest:f src1:i len:9
117 conv.u4: dest:i src1:i len:3
118 conv.u8: dest:i src1:i len:3
125 conv.r.un: dest:f src1:i len:8
128 op_rethrow: src1:i len:18
138 conv.ovf.i4.un: dest:i src1:i len:16
174 conv.ovf.u4: dest:i src1:i len:15
178 ckfinite: dest:f src1:f len:43
181 conv.u2: dest:i src1:i len:4
182 conv.u1: dest:i src1:i len:4
183 conv.i: dest:i src1:i len:4
188 mul.ovf: dest:i src1:i src2:i clob:1 len:10
189 # this opcode is handled specially in the code generator
190 mul.ovf.un: dest:i src1:i src2:i len:18
197 conv.u: dest:i src1:i len:4
220 localloc: dest:i src1:i len:84
242 compare: src1:i src2:i len:3
243 lcompare: src1:i src2:i len:3
244 icompare: src1:i src2:i len:3
245 compare_imm: src1:i len:13
246 icompare_imm: src1:i len:8
247 fcompare: src1:f src2:f clob:a len:13
250 oparglist: src1:b len:11
254 setret: dest:a src1:i len:3
255 setlret: dest:i src1:i src2:i len:5
256 checkthis: src1:b len:5
257 call: dest:a clob:c len:64
259 voidcall: clob:c len:64
260 voidcall_reg: src1:i clob:c len:64
261 voidcall_membase: src1:b clob:c len:64
262 fcall: dest:f len:64 clob:c
263 fcall_reg: dest:f src1:i len:64 clob:c
264 fcall_membase: dest:f src1:b len:64 clob:c
265 lcall: dest:i len:64 clob:c
266 lcall_reg: dest:i src1:i len:64 clob:c
267 lcall_membase: dest:i src1:b len:64 clob:c
269 vcall_reg: src1:i len:64 clob:c
270 vcall_membase: src1:b len:64 clob:c
271 call_reg: dest:a src1:i len:64 clob:c
272 call_membase: dest:a src1:b len:64 clob:c
274 iconst: dest:i len:10
275 i8const: dest:i len:18
276 r4const: dest:f len:13
277 r8const: dest:f len:9
282 store_membase_imm: dest:b len:15
283 store_membase_reg: dest:b src1:i len:9
284 storei8_membase_reg: dest:b src1:i len:9
285 storei1_membase_imm: dest:b len:11
286 storei1_membase_reg: dest:b src1:i len:9
287 storei2_membase_imm: dest:b len:13
288 storei2_membase_reg: dest:b src1:i len:9
289 storei4_membase_imm: dest:b len:13
290 storei4_membase_reg: dest:b src1:i len:9
291 storei8_membase_imm: dest:b len:18
292 storer4_membase_reg: dest:b src1:f len:15
293 storer8_membase_reg: dest:b src1:f len:10
294 load_membase: dest:i src1:b len:15
295 loadi1_membase: dest:i src1:b len:9
296 loadu1_membase: dest:i src1:b len:9
297 loadi2_membase: dest:i src1:b len:9
298 loadu2_membase: dest:i src1:b len:9
299 loadi4_membase: dest:i src1:b len:9
300 loadu4_membase: dest:i src1:b len:9
301 loadi8_membase: dest:i src1:b len:18
302 loadr4_membase: dest:f src1:b len:16
303 loadr8_membase: dest:f src1:b len:16
304 loadr8_spill_membase: src1:b len:9
305 loadu4_mem: dest:i len:10
306 move: dest:i src1:i len:4
307 setreg: dest:i src1:i len:4
308 add_imm: dest:i src1:i len:8 clob:1
309 sub_imm: dest:i src1:i len:8 clob:1
310 mul_imm: dest:i src1:i len:8
311 # there is no actual support for division or reminder by immediate
312 # we simulate them, though (but we need to change the burg rules
313 # to allocate a symbolic reg for src2)
314 div_imm: dest:a src1:i src2:i len:16 clob:d
315 div_un_imm: dest:a src1:i src2:i len:16 clob:d
316 rem_imm: dest:d src1:i src2:i len:16 clob:d
317 rem_un_imm: dest:d src1:i src2:i len:16 clob:d
318 and_imm: dest:i src1:i len:8 clob:1
319 or_imm: dest:i src1:i len:8 clob:1
320 xor_imm: dest:i src1:i len:8 clob:1
321 shl_imm: dest:i src1:i len:8 clob:1
322 shr_imm: dest:i src1:i len:8 clob:1
323 shr_un_imm: dest:i src1:i len:8 clob:1
325 cond_exc_ne_un: len:8
327 cond_exc_lt_un: len:8
329 cond_exc_gt_un: len:8
331 cond_exc_ge_un: len:8
333 cond_exc_le_un: len:8
342 long_mul: dest:i src1:i src2:i clob:1 len:4
343 long_mul_imm: dest:i src1:i src2:i clob:1 len:8
344 long_div: dest:a src1:a src2:i len:16 clob:d
345 long_div_un: dest:a src1:a src2:i len:16 clob:d
346 long_rem: dest:d src1:a src2:i len:16 clob:d
347 long_rem_un: dest:d src1:a src2:i len:16 clob:d
351 long_shl: dest:i src1:i src2:i clob:s len:31
352 long_shr: dest:i src1:i src2:i clob:s len:32
353 long_shr_un: dest:i src1:i src2:i clob:s len:32
360 long_conv_to_r4: dest:f src1:i len:8
361 long_conv_to_r8: dest:f src1:i len:8
367 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
371 long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
372 long_mul_ovf_un: dest:i src1:i src2:i len:22
375 long_conv_to_ovf_i1_un:
376 long_conv_to_ovf_i2_un:
377 long_conv_to_ovf_i4_un:
378 long_conv_to_ovf_i8_un:
379 long_conv_to_ovf_u1_un:
380 long_conv_to_ovf_u2_un:
381 long_conv_to_ovf_u4_un:
382 long_conv_to_ovf_u8_un:
383 long_conv_to_ovf_i_un:
384 long_conv_to_ovf_u_un:
398 long_conv_to_r_un: dest:f src1:i src2:i len:48
400 long_shr_imm: dest:i src1:i clob:1 len:11
401 long_shr_un_imm: dest:i src1:i clob:1 len:11
402 long_shl_imm: dest:i src1:i clob:1 len:11
425 float_add: dest:f src1:f src2:f len:5
426 float_sub: dest:f src1:f src2:f len:5
427 float_mul: dest:f src1:f src2:f len:5
428 float_div: dest:f src1:f src2:f len:5
429 float_div_un: dest:f src1:f src2:f len:5
430 float_rem: dest:f src1:f src2:f len:19
431 float_rem_un: dest:f src1:f src2:f len:19
432 float_neg: dest:f src1:f len:19
433 float_not: dest:f src1:f len:3
434 float_conv_to_i1: dest:i src1:f len:49
435 float_conv_to_i2: dest:i src1:f len:49
436 float_conv_to_i4: dest:i src1:f len:49
437 float_conv_to_i8: dest:i src1:f len:49
440 float_conv_to_u4: dest:i src1:f len:49
441 float_conv_to_u8: dest:i src1:f len:49
442 float_conv_to_u2: dest:i src1:f len:49
443 float_conv_to_u1: dest:i src1:f len:49
444 float_conv_to_i: dest:i src1:f len:49
445 float_conv_to_ovf_i: dest:a src1:f len:40
446 float_conv_to_ovd_u: dest:a src1:f len:40
453 float_conv_to_ovf_i1_un:
454 float_conv_to_ovf_i2_un:
455 float_conv_to_ovf_i4_un:
456 float_conv_to_ovf_i8_un:
457 float_conv_to_ovf_u1_un:
458 float_conv_to_ovf_u2_un:
459 float_conv_to_ovf_u4_un:
460 float_conv_to_ovf_u8_un:
461 float_conv_to_ovf_i_un:
462 float_conv_to_ovf_u_un:
463 float_conv_to_ovf_i1:
464 float_conv_to_ovf_u1:
465 float_conv_to_ovf_i2:
466 float_conv_to_ovf_u2:
467 float_conv_to_ovf_i4:
468 float_conv_to_ovf_u4:
469 float_conv_to_ovf_i8:
470 float_conv_to_ovf_u8:
471 float_ceq: dest:i src1:f src2:f len:35
472 float_cgt: dest:i src1:f src2:f len:35
473 float_cgt_un: dest:i src1:f src2:f len:48
474 float_clt: dest:i src1:f src2:f len:35
475 float_clt_un: dest:i src1:f src2:f len:42
476 float_ceq_membase: dest:i src1:f src2:b len:35
477 float_cgt_membase: dest:i src1:f src2:b len:35
478 float_cgt_un_membase: dest:i src1:f src2:b len:48
479 float_clt_membase: dest:i src1:f src2:b len:35
480 float_clt_un_membase: dest:i src1:f src2:b len:42
481 float_conv_to_u: dest:i src1:f len:46
482 fmove: dest:f src1:f len:8
484 aot_const: dest:i len:10
485 x86_test_null: src1:i len:5
486 x86_compare_membase_reg: src1:b src2:i len:9
487 x86_compare_membase_imm: src1:b len:13
488 x86_compare_reg_membase: src1:i src2:b len:8
489 x86_inc_reg: dest:i src1:i clob:1 len:3
490 x86_inc_membase: src1:b len:8
491 x86_dec_reg: dest:i src1:i clob:1 len:3
492 x86_dec_membase: src1:b len:8
493 x86_add_membase_imm: src1:b len:13
494 x86_sub_membase_imm: src1:b len:13
495 x86_push: src1:i len:3
497 x86_push_membase: src1:b len:8
498 x86_push_obj: src1:b len:40
499 x86_lea: dest:i src1:i src2:i len:8
500 x86_lea_membase: dest:i src1:i len:11
501 x86_xchg: src1:i src2:i clob:x len:2
502 x86_fpop: src1:f len:3
503 x86_fp_load_i8: dest:f src1:b len:8
504 x86_fp_load_i4: dest:f src1:b len:8
505 x86_seteq_membase: src1:b len:9
506 x86_add_membase: dest:i src1:i src2:b clob:1 len:13
507 x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
508 x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
509 tls_get: dest:i len:13
510 amd64_test_null: src1:i len:5
511 amd64_icompare_membase_reg: src1:b src2:i len:8
512 amd64_icompare_membase_imm: src1:b len:13
513 amd64_icompare_reg_membase: src1:i src2:b len:8
514 amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
515 amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
516 atomic_add_i4: src1:b src2:i dest:i len:32
517 atomic_add_new_i4: src1:b src2:i dest:i len:32
518 atomic_exchange_i4: src1:b src2:i dest:i len:32
519 atomic_add_i8: src1:b src2:i dest:i len:32
520 atomic_add_new_i8: src1:b src2:i dest:i len:32
521 atomic_exchange_i8: src1:b src2:i dest:i len:32
522 adc: dest:i src1:i src2:i len:3 clob:1
523 addcc: dest:i src1:i src2:i len:3 clob:1
524 subcc: dest:i src1:i src2:i len:3 clob:1
525 adc_imm: dest:i src1:i len:8 clob:1
526 sbb: dest:i src1:i src2:i len:3 clob:1
527 sbb_imm: dest:i src1:i len:8 clob:1
529 sin: dest:f src1:f len:32
530 cos: dest:f src1:f len:32
531 abs: dest:f src1:f len:32
532 tan: dest:f src1:f len:59
533 atan: dest:f src1:f len:9
534 sqrt: dest:f src1:f len:32
535 op_bigmul: len:3 dest:i src1:a src2:i
536 op_bigmul_un: len:3 dest:i src1:a src2:i
537 sext_i1: dest:i src1:i len:4
538 sext_i2: dest:i src1:i len:4
542 int_add: dest:i src1:i src2:i clob:1 len:64
543 int_sub: dest:i src1:i src2:i clob:1 len:64
544 int_mul: dest:i src1:i src2:i clob:1 len:64
545 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
546 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
547 int_div: dest:a src1:a src2:i clob:d len:64
548 int_div_un: dest:a src1:a src2:i clob:d len:64
549 int_rem: dest:d src1:a src2:i clob:d len:64
550 int_rem_un: dest:d src1:a src2:i clob:d len:64
551 int_and: dest:i src1:i src2:i clob:1 len:64
552 int_or: dest:i src1:i src2:i clob:1 len:64
553 int_xor: dest:i src1:i src2:i clob:1 len:64
554 int_shl: dest:i src1:i src2:i clob:s len:64
555 int_shr: dest:i src1:i src2:i clob:s len:64
556 int_shr_un: dest:i src1:i src2:i clob:s len:64
557 int_adc: dest:i src1:i src2:i clob:1 len:64
558 int_adc_imm: dest:i src1:i clob:1 len:64
559 int_sbb: dest:i src1:i src2:i clob:1 len:64
560 int_sbb_imm: dest:i src1:i clob:1 len:64
561 int_addcc: dest:i src1:i src2:i clob:1 len:64
562 int_subcc: dest:i src1:i src2:i clob:1 len:64
563 int_add_imm: dest:i src1:i clob:1 len:64
564 int_sub_imm: dest:i src1:i clob:1 len:64
565 int_mul_imm: dest:i src1:i clob:1 len:64
566 int_div_imm: dest:a src1:i clob:d len:64
567 int_div_un_imm: dest:a src1:i clob:d len:64
568 int_rem_imm: dest:d src1:i clob:d len:64
569 int_rem_un_imm: dest:d src1:i clob:d len:64
570 int_and_imm: dest:i src1:i clob:1 len:64
571 int_or_imm: dest:i src1:i clob:1 len:64
572 int_xor_imm: dest:i src1:i clob:1 len:64
573 int_shl_imm: dest:i src1:i clob:1 len:64
574 int_shr_imm: dest:i src1:i clob:1 len:64
575 int_shr_un_imm: dest:i src1:i clob:1 len:64
576 int_neg: dest:i src1:i clob:1 len:64
577 int_not: dest:i src1:i clob:1 len:64
578 int_ceq: dest:i len:64
579 int_cgt: dest:i len:64
580 int_cgt_un: dest:i len:64
581 int_clt: dest:i len:64
582 int_clt_un: dest:i len:64