1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
15 # b base register (used in address references)
16 # f floating point register
19 # l long reg (forced eax:edx)
21 # c register which can be used as a byte register (RAX..RDX)
23 # len:number describe the maximun length in bytes of the instruction
24 # number is a positive integer. If the length is not specified
25 # it defaults to zero. But lengths are only checked if the given opcode
26 # is encountered during compilation. Some opcodes, like CONV_U4 are
27 # transformed into other opcodes in the brg files, so they do not show up
28 # during code generation.
30 # cost:number describe how many cycles are needed to complete the instruction (unused)
32 # clob:spec describe if the instruction clobbers registers or has special needs
34 # c clobbers caller-save registers
35 # 1 clobbers the first source register
38 # x both the source operands are clobbered (xchg)
41 # flags:spec describe if the instruction uses or sets the flags (unused)
45 # m uses and modifies the flags
47 # res:spec describe what units are used in the processor (unused)
49 # delay: describe delay slots (unused)
51 # the required specifiers are: len, clob (if registers are clobbered), the registers
52 # specifiers if the registers are actually used, flags (when scheduling is implemented).
54 # See the code in mini-x86.c for more details on how the specifiers are used.
70 ldind.i1: dest:i len:8
71 ldind.u1: dest:i len:8
72 ldind.i2: dest:i len:8
73 ldind.u2: dest:i len:8
74 ldind.i4: dest:i len:9
75 ldind.u4: dest:i len:8
77 ldind.ref: dest:i len:8
78 stind.ref: src1:b src2:i
79 stind.i1: src1:b src2:i
80 stind.i2: src1:b src2:i
81 stind.i4: src1:b src2:i
82 stind.r4: dest:f src1:b
83 stind.r8: dest:f src1:b
84 add: dest:i src1:i src2:i len:3 clob:1
85 sub: dest:i src1:i src2:i len:3 clob:1
86 mul: dest:i src1:i src2:i len:4 clob:1
87 div: dest:a src1:a src2:i len:16 clob:d
88 div.un: dest:a src1:a src2:i len:16 clob:d
89 rem: dest:d src1:a src2:i len:16 clob:a
90 rem.un: dest:d src1:a src2:i len:16 clob:a
91 and: dest:i src1:i src2:i len:3 clob:1
92 or: dest:i src1:i src2:i len:3 clob:1
93 xor: dest:i src1:i src2:i len:3 clob:1
94 shl: dest:i src1:i src2:s clob:1 len:3
95 shr: dest:i src1:i src2:s clob:1 len:3
96 shr.un: dest:i src1:i src2:s clob:1 len:3
97 neg: dest:i src1:i len:3 clob:1
98 not: dest:i src1:i len:3 clob:1
99 conv.i1: dest:i src1:i len:4
100 conv.i2: dest:i src1:i len:4
101 conv.i4: dest:i src1:i len:3
102 conv.i8: dest:i src1:i len:3
103 conv.r4: dest:f src1:i len:9
104 conv.r8: dest:f src1:i len:9
105 conv.u4: dest:i src1:i len:3
106 conv.u8: dest:i src1:i len:3
107 conv.r.un: dest:f src1:i len:8
109 op_rethrow: src1:i len:18
110 conv.ovf.i4.un: dest:i src1:i len:16
112 conv.ovf.u4: dest:i src1:i len:15
113 ckfinite: dest:f src1:f len:43
114 conv.u2: dest:i src1:i len:4
115 conv.u1: dest:i src1:i len:4
116 conv.i: dest:i src1:i len:4
117 mul.ovf: dest:i src1:i src2:i clob:1 len:10
118 # this opcode is handled specially in the code generator
119 mul.ovf.un: dest:i src1:i src2:i len:18
120 conv.u: dest:i src1:i len:4
126 localloc: dest:i src1:i len:84
127 compare: src1:i src2:i len:3
128 lcompare: src1:i src2:i len:3
129 icompare: src1:i src2:i len:3
130 compare_imm: src1:i len:13
131 icompare_imm: src1:i len:8
132 fcompare: src1:f src2:f clob:a len:13
133 oparglist: src1:b len:11
136 setret: dest:a src1:i len:3
137 setlret: dest:i src1:i src2:i len:5
138 checkthis: src1:b len:5
139 call: dest:a clob:c len:64
141 voidcall: clob:c len:64
142 voidcall_reg: src1:i clob:c len:64
143 voidcall_membase: src1:b clob:c len:64
144 fcall: dest:f len:64 clob:c
145 fcall_reg: dest:f src1:i len:64 clob:c
146 fcall_membase: dest:f src1:b len:64 clob:c
147 lcall: dest:a len:64 clob:c
148 lcall_reg: dest:a src1:i len:64 clob:c
149 lcall_membase: dest:a src1:b len:64 clob:c
151 vcall_reg: src1:i len:64 clob:c
152 vcall_membase: src1:b len:64 clob:c
153 call_reg: dest:a src1:i len:64 clob:c
154 call_membase: dest:a src1:b len:64 clob:c
155 iconst: dest:i len:10
156 i8const: dest:i len:18
157 r4const: dest:f len:13
158 r8const: dest:f len:9
159 store_membase_imm: dest:b len:15
160 store_membase_reg: dest:b src1:i len:9
161 storei8_membase_reg: dest:b src1:i len:9
162 storei1_membase_imm: dest:b len:11
163 storei1_membase_reg: dest:b src1:c len:9
164 storei2_membase_imm: dest:b len:13
165 storei2_membase_reg: dest:b src1:i len:9
166 storei4_membase_imm: dest:b len:13
167 storei4_membase_reg: dest:b src1:i len:9
168 storei8_membase_imm: dest:b len:18
169 storer4_membase_reg: dest:b src1:f len:15
170 storer8_membase_reg: dest:b src1:f len:10
171 load_membase: dest:i src1:b len:15
172 loadi1_membase: dest:c src1:b len:9
173 loadu1_membase: dest:c src1:b len:9
174 loadi2_membase: dest:i src1:b len:9
175 loadu2_membase: dest:i src1:b len:9
176 loadi4_membase: dest:i src1:b len:9
177 loadu4_membase: dest:i src1:b len:9
178 loadi8_membase: dest:i src1:b len:18
179 loadr4_membase: dest:f src1:b len:16
180 loadr8_membase: dest:f src1:b len:16
181 loadr8_spill_membase: src1:b len:9
182 loadu4_mem: dest:i len:10
183 amd64_loadi8_memindex: dest:i src1:i src2:i len:10
184 move: dest:i src1:i len:4
185 add_imm: dest:i src1:i len:8 clob:1
186 sub_imm: dest:i src1:i len:8 clob:1
187 mul_imm: dest:i src1:i len:11
188 # there is no actual support for division or reminder by immediate
189 # we simulate them, though (but we need to change the burg rules
190 # to allocate a symbolic reg for src2)
191 div_imm: dest:a src1:i src2:i len:16 clob:d
192 div_un_imm: dest:a src1:i src2:i len:16 clob:d
193 rem_imm: dest:d src1:i src2:i len:16 clob:a
194 rem_un_imm: dest:d src1:i src2:i len:16 clob:a
195 and_imm: dest:i src1:i len:8 clob:1
196 or_imm: dest:i src1:i len:8 clob:1
197 xor_imm: dest:i src1:i len:8 clob:1
198 shl_imm: dest:i src1:i len:8 clob:1
199 shr_imm: dest:i src1:i len:8 clob:1
200 shr_un_imm: dest:i src1:i len:8 clob:1
202 cond_exc_ne_un: len:8
204 cond_exc_lt_un: len:8
206 cond_exc_gt_un: len:8
208 cond_exc_ge_un: len:8
210 cond_exc_le_un: len:8
217 long_mul: dest:i src1:i src2:i clob:1 len:4
218 long_mul_imm: dest:i src1:i clob:1 len:12
219 long_div: dest:a src1:a src2:i len:16 clob:d
220 long_div_un: dest:a src1:a src2:i len:16 clob:d
221 long_rem: dest:d src1:a src2:i len:16 clob:a
222 long_rem_un: dest:d src1:a src2:i len:16 clob:a
223 long_shl: dest:i src1:i src2:s clob:1 len:31
224 long_shr: dest:i src1:i src2:s clob:1 len:32
225 long_shr_un: dest:i src1:i src2:s clob:1 len:32
226 long_conv_to_r4: dest:f src1:i len:8
227 long_conv_to_r8: dest:f src1:i len:8
228 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
229 long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
230 long_mul_ovf_un: dest:i src1:i src2:i len:22
231 long_conv_to_r_un: dest:f src1:i src2:i len:48
232 long_shr_imm: dest:i src1:i clob:1 len:11
233 long_shr_un_imm: dest:i src1:i clob:1 len:11
234 long_shl_imm: dest:i src1:i clob:1 len:11
245 float_add: dest:f src1:f src2:f len:5
246 float_sub: dest:f src1:f src2:f len:5
247 float_mul: dest:f src1:f src2:f len:5
248 float_div: dest:f src1:f src2:f len:5
249 float_div_un: dest:f src1:f src2:f len:5
250 float_rem: dest:f src1:f src2:f len:19
251 float_rem_un: dest:f src1:f src2:f len:19
252 float_neg: dest:f src1:f len:23
253 float_not: dest:f src1:f len:3
254 float_conv_to_i1: dest:i src1:f len:49
255 float_conv_to_i2: dest:i src1:f len:49
256 float_conv_to_i4: dest:i src1:f len:49
257 float_conv_to_i8: dest:i src1:f len:49
258 float_conv_to_u4: dest:i src1:f len:49
259 float_conv_to_u8: dest:i src1:f len:49
260 float_conv_to_u2: dest:i src1:f len:49
261 float_conv_to_u1: dest:i src1:f len:49
262 float_conv_to_i: dest:i src1:f len:49
263 float_conv_to_ovf_i: dest:a src1:f len:40
264 float_conv_to_ovd_u: dest:a src1:f len:40
266 float_ceq: dest:i src1:f src2:f len:35
267 float_cgt: dest:i src1:f src2:f len:35
268 float_cgt_un: dest:i src1:f src2:f len:48
269 float_clt: dest:i src1:f src2:f len:35
270 float_clt_un: dest:i src1:f src2:f len:42
271 float_ceq_membase: dest:i src1:f src2:b len:35
272 float_cgt_membase: dest:i src1:f src2:b len:35
273 float_cgt_un_membase: dest:i src1:f src2:b len:48
274 float_clt_membase: dest:i src1:f src2:b len:35
275 float_clt_un_membase: dest:i src1:f src2:b len:42
276 float_conv_to_u: dest:i src1:f len:46
277 fmove: dest:f src1:f len:8
279 aot_const: dest:i len:10
280 x86_test_null: src1:i len:5
281 x86_compare_membase_reg: src1:b src2:i len:9
282 x86_compare_membase_imm: src1:b len:13
283 x86_compare_reg_membase: src1:i src2:b len:8
284 x86_inc_reg: dest:i src1:i clob:1 len:3
285 x86_inc_membase: src1:b len:8
286 x86_dec_reg: dest:i src1:i clob:1 len:3
287 x86_dec_membase: src1:b len:8
288 x86_add_membase_imm: src1:b len:13
289 x86_sub_membase_imm: src1:b len:13
290 x86_push: src1:i len:3
292 x86_push_membase: src1:b len:8
293 x86_push_obj: src1:b len:40
294 x86_lea: dest:i src1:i src2:i len:8
295 x86_lea_membase: dest:i src1:i len:11
296 x86_xchg: src1:i src2:i clob:x len:2
297 x86_fpop: src1:f len:3
298 x86_fp_load_i8: dest:f src1:b len:8
299 x86_fp_load_i4: dest:f src1:b len:8
300 x86_seteq_membase: src1:b len:9
301 x86_add_membase: dest:i src1:i src2:b clob:1 len:13
302 x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
303 x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
304 tls_get: dest:i len:13
305 amd64_test_null: src1:i len:5
306 amd64_icompare_membase_reg: src1:b src2:i len:8
307 amd64_icompare_membase_imm: src1:b len:13
308 amd64_icompare_reg_membase: src1:i src2:b len:8
309 amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
310 amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
311 atomic_add_i4: src1:b src2:i dest:i len:32
312 atomic_add_new_i4: src1:b src2:i dest:i len:32
313 atomic_exchange_i4: src1:b src2:i dest:i len:32
314 atomic_add_i8: src1:b src2:i dest:i len:32
315 atomic_add_new_i8: src1:b src2:i dest:i len:32
316 atomic_exchange_i8: src1:b src2:i dest:i len:32
317 memory_barrier: len:16
318 adc: dest:i src1:i src2:i len:3 clob:1
319 addcc: dest:i src1:i src2:i len:3 clob:1
320 subcc: dest:i src1:i src2:i len:3 clob:1
321 adc_imm: dest:i src1:i len:8 clob:1
322 sbb: dest:i src1:i src2:i len:3 clob:1
323 sbb_imm: dest:i src1:i len:8 clob:1
325 sin: dest:f src1:f len:32
326 cos: dest:f src1:f len:32
327 abs: dest:f src1:f len:32
328 tan: dest:f src1:f len:59
329 atan: dest:f src1:f len:9
330 sqrt: dest:f src1:f len:32
331 op_bigmul: len:3 dest:i src1:a src2:i
332 op_bigmul_un: len:3 dest:i src1:a src2:i
333 sext_i1: dest:i src1:i len:4
334 sext_i2: dest:i src1:i len:4
335 sext_i4: dest:i src1:i len:8
339 int_add: dest:i src1:i src2:i clob:1 len:64
340 int_sub: dest:i src1:i src2:i clob:1 len:64
341 int_mul: dest:i src1:i src2:i clob:1 len:64
342 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
343 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
344 int_div: dest:a src1:a src2:i clob:d len:64
345 int_div_un: dest:a src1:a src2:i clob:d len:64
346 int_rem: dest:d src1:a src2:i clob:a len:64
347 int_rem_un: dest:d src1:a src2:i clob:a len:64
348 int_and: dest:i src1:i src2:i clob:1 len:64
349 int_or: dest:i src1:i src2:i clob:1 len:64
350 int_xor: dest:i src1:i src2:i clob:1 len:64
351 int_shl: dest:i src1:i src2:s clob:1 len:64
352 int_shr: dest:i src1:i src2:s clob:1 len:64
353 int_shr_un: dest:i src1:i src2:s clob:1 len:64
354 int_adc: dest:i src1:i src2:i clob:1 len:64
355 int_adc_imm: dest:i src1:i clob:1 len:64
356 int_sbb: dest:i src1:i src2:i clob:1 len:64
357 int_sbb_imm: dest:i src1:i clob:1 len:64
358 int_addcc: dest:i src1:i src2:i clob:1 len:64
359 int_subcc: dest:i src1:i src2:i clob:1 len:64
360 int_add_imm: dest:i src1:i clob:1 len:64
361 int_sub_imm: dest:i src1:i clob:1 len:64
362 int_mul_imm: dest:i src1:i clob:1 len:64
363 int_div_imm: dest:a src1:i clob:d len:64
364 int_div_un_imm: dest:a src1:i clob:d len:64
365 int_rem_imm: dest:d src1:i clob:a len:64
366 int_rem_un_imm: dest:d src1:i clob:a len:64
367 int_and_imm: dest:i src1:i clob:1 len:64
368 int_or_imm: dest:i src1:i clob:1 len:64
369 int_xor_imm: dest:i src1:i clob:1 len:64
370 int_shl_imm: dest:i src1:i clob:1 len:64
371 int_shr_imm: dest:i src1:i clob:1 len:64
372 int_shr_un_imm: dest:i src1:i clob:1 len:64
373 int_neg: dest:i src1:i clob:1 len:64
374 int_not: dest:i src1:i clob:1 len:64
375 int_ceq: dest:c len:64
376 int_cgt: dest:c len:64
377 int_cgt_un: dest:c len:64
378 int_clt: dest:c len:64
379 int_clt_un: dest:c len:64