1 # x86-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # b base register (used in address references)
17 # f floating point register
20 # l long reg (forced eax:edx)
22 # c register which can be used as a byte register (RAX..RDX)
24 # len:number describe the maximun length in bytes of the instruction
25 # number is a positive integer. If the length is not specified
26 # it defaults to zero. But lengths are only checked if the given opcode
27 # is encountered during compilation. Some opcodes, like CONV_U4 are
28 # transformed into other opcodes in the brg files, so they do not show up
29 # during code generation.
31 # cost:number describe how many cycles are needed to complete the instruction (unused)
33 # clob:spec describe if the instruction clobbers registers or has special needs
35 # spec can be one of the following characters:
36 # c clobbers caller-save registers
37 # 1 clobbers the first source register
40 # x both the source operands are clobbered (xchg)
43 # flags:spec describe if the instruction uses or sets the flags (unused)
45 # spec can be one of the following chars:
48 # m uses and modifies the flags
50 # res:spec describe what units are used in the processor (unused)
52 # delay: describe delay slots (unused)
54 # the required specifiers are: len, clob (if registers are clobbered), the registers
55 # specifiers if the registers are actually used, flags (when scheduling is implemented).
57 # See the code in mini-x86.c for more details on how the specifiers are used.
79 ldind.i1: dest:i len:8
80 ldind.u1: dest:i len:8
81 ldind.i2: dest:i len:8
82 ldind.u2: dest:i len:8
83 ldind.i4: dest:i len:9
84 ldind.u4: dest:i len:8
89 ldind.ref: dest:i len:8
90 stind.ref: src1:b src2:i
91 stind.i1: src1:b src2:i
92 stind.i2: src1:b src2:i
93 stind.i4: src1:b src2:i
95 stind.r4: dest:f src1:b
96 stind.r8: dest:f src1:b
97 add: dest:i src1:i src2:i len:3 clob:1
98 sub: dest:i src1:i src2:i len:3 clob:1
99 mul: dest:i src1:i src2:i len:4 clob:1
100 div: dest:a src1:a src2:i len:16 clob:d
101 div.un: dest:a src1:a src2:i len:16 clob:d
102 rem: dest:d src1:a src2:i len:16 clob:a
103 rem.un: dest:d src1:a src2:i len:16 clob:a
104 and: dest:i src1:i src2:i len:3 clob:1
105 or: dest:i src1:i src2:i len:3 clob:1
106 xor: dest:i src1:i src2:i len:3 clob:1
107 shl: dest:i src1:i src2:s clob:1 len:3
108 shr: dest:i src1:i src2:s clob:1 len:3
109 shr.un: dest:i src1:i src2:s clob:1 len:3
110 neg: dest:i src1:i len:3 clob:1
111 not: dest:i src1:i len:3 clob:1
112 conv.i1: dest:i src1:i len:4
113 conv.i2: dest:i src1:i len:4
114 conv.i4: dest:i src1:i len:3
115 conv.i8: dest:i src1:i len:3
116 conv.r4: dest:f src1:i len:9
117 conv.r8: dest:f src1:i len:9
118 conv.u4: dest:i src1:i len:3
119 conv.u8: dest:i src1:i len:3
126 conv.r.un: dest:f src1:i len:8
129 op_rethrow: src1:i len:18
139 conv.ovf.i4.un: dest:i src1:i len:16
175 conv.ovf.u4: dest:i src1:i len:15
179 ckfinite: dest:f src1:f len:43
182 conv.u2: dest:i src1:i len:4
183 conv.u1: dest:i src1:i len:4
184 conv.i: dest:i src1:i len:4
189 mul.ovf: dest:i src1:i src2:i clob:1 len:10
190 # this opcode is handled specially in the code generator
191 mul.ovf.un: dest:i src1:i src2:i len:18
198 conv.u: dest:i src1:i len:4
221 localloc: dest:i src1:i len:84
243 compare: src1:i src2:i len:3
244 lcompare: src1:i src2:i len:3
245 icompare: src1:i src2:i len:3
246 compare_imm: src1:i len:13
247 icompare_imm: src1:i len:8
248 fcompare: src1:f src2:f clob:a len:13
251 oparglist: src1:b len:11
255 setret: dest:a src1:i len:3
256 setlret: dest:i src1:i src2:i len:5
257 checkthis: src1:b len:5
258 call: dest:a clob:c len:64
260 voidcall: clob:c len:64
261 voidcall_reg: src1:i clob:c len:64
262 voidcall_membase: src1:b clob:c len:64
263 fcall: dest:f len:64 clob:c
264 fcall_reg: dest:f src1:i len:64 clob:c
265 fcall_membase: dest:f src1:b len:64 clob:c
266 lcall: dest:a len:64 clob:c
267 lcall_reg: dest:a src1:i len:64 clob:c
268 lcall_membase: dest:a src1:b len:64 clob:c
270 vcall_reg: src1:i len:64 clob:c
271 vcall_membase: src1:b len:64 clob:c
272 call_reg: dest:a src1:i len:64 clob:c
273 call_membase: dest:a src1:b len:64 clob:c
275 iconst: dest:i len:10
276 i8const: dest:i len:18
277 r4const: dest:f len:13
278 r8const: dest:f len:9
283 store_membase_imm: dest:b len:15
284 store_membase_reg: dest:b src1:i len:9
285 storei8_membase_reg: dest:b src1:i len:9
286 storei1_membase_imm: dest:b len:11
287 storei1_membase_reg: dest:b src1:c len:9
288 storei2_membase_imm: dest:b len:13
289 storei2_membase_reg: dest:b src1:i len:9
290 storei4_membase_imm: dest:b len:13
291 storei4_membase_reg: dest:b src1:i len:9
292 storei8_membase_imm: dest:b len:18
293 storer4_membase_reg: dest:b src1:f len:15
294 storer8_membase_reg: dest:b src1:f len:10
295 load_membase: dest:i src1:b len:15
296 loadi1_membase: dest:c src1:b len:9
297 loadu1_membase: dest:c src1:b len:9
298 loadi2_membase: dest:i src1:b len:9
299 loadu2_membase: dest:i src1:b len:9
300 loadi4_membase: dest:i src1:b len:9
301 loadu4_membase: dest:i src1:b len:9
302 loadi8_membase: dest:i src1:b len:18
303 loadr4_membase: dest:f src1:b len:16
304 loadr8_membase: dest:f src1:b len:16
305 loadr8_spill_membase: src1:b len:9
306 loadu4_mem: dest:i len:10
307 amd64_loadi8_memindex: dest:i src1:i src2:i len:10
308 move: dest:i src1:i len:4
309 setreg: dest:i src1:i len:4
310 add_imm: dest:i src1:i len:8 clob:1
311 sub_imm: dest:i src1:i len:8 clob:1
312 mul_imm: dest:i src1:i len:8
313 # there is no actual support for division or reminder by immediate
314 # we simulate them, though (but we need to change the burg rules
315 # to allocate a symbolic reg for src2)
316 div_imm: dest:a src1:i src2:i len:16 clob:d
317 div_un_imm: dest:a src1:i src2:i len:16 clob:d
318 rem_imm: dest:d src1:i src2:i len:16 clob:a
319 rem_un_imm: dest:d src1:i src2:i len:16 clob:a
320 and_imm: dest:i src1:i len:8 clob:1
321 or_imm: dest:i src1:i len:8 clob:1
322 xor_imm: dest:i src1:i len:8 clob:1
323 shl_imm: dest:i src1:i len:8 clob:1
324 shr_imm: dest:i src1:i len:8 clob:1
325 shr_un_imm: dest:i src1:i len:8 clob:1
327 cond_exc_ne_un: len:8
329 cond_exc_lt_un: len:8
331 cond_exc_gt_un: len:8
333 cond_exc_ge_un: len:8
335 cond_exc_le_un: len:8
344 long_mul: dest:i src1:i src2:i clob:1 len:4
345 long_mul_imm: dest:i src1:i src2:i clob:1 len:8
346 long_div: dest:a src1:a src2:i len:16 clob:d
347 long_div_un: dest:a src1:a src2:i len:16 clob:d
348 long_rem: dest:d src1:a src2:i len:16 clob:a
349 long_rem_un: dest:d src1:a src2:i len:16 clob:a
353 long_shl: dest:i src1:i src2:s clob:1 len:31
354 long_shr: dest:i src1:i src2:s clob:1 len:32
355 long_shr_un: dest:i src1:i src2:s clob:1 len:32
362 long_conv_to_r4: dest:f src1:i len:8
363 long_conv_to_r8: dest:f src1:i len:8
369 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
373 long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
374 long_mul_ovf_un: dest:i src1:i src2:i len:22
377 long_conv_to_ovf_i1_un:
378 long_conv_to_ovf_i2_un:
379 long_conv_to_ovf_i4_un:
380 long_conv_to_ovf_i8_un:
381 long_conv_to_ovf_u1_un:
382 long_conv_to_ovf_u2_un:
383 long_conv_to_ovf_u4_un:
384 long_conv_to_ovf_u8_un:
385 long_conv_to_ovf_i_un:
386 long_conv_to_ovf_u_un:
400 long_conv_to_r_un: dest:f src1:i src2:i len:48
402 long_shr_imm: dest:i src1:i clob:1 len:11
403 long_shr_un_imm: dest:i src1:i clob:1 len:11
404 long_shl_imm: dest:i src1:i clob:1 len:11
427 float_add: dest:f src1:f src2:f len:5
428 float_sub: dest:f src1:f src2:f len:5
429 float_mul: dest:f src1:f src2:f len:5
430 float_div: dest:f src1:f src2:f len:5
431 float_div_un: dest:f src1:f src2:f len:5
432 float_rem: dest:f src1:f src2:f len:19
433 float_rem_un: dest:f src1:f src2:f len:19
434 float_neg: dest:f src1:f len:23
435 float_not: dest:f src1:f len:3
436 float_conv_to_i1: dest:i src1:f len:49
437 float_conv_to_i2: dest:i src1:f len:49
438 float_conv_to_i4: dest:i src1:f len:49
439 float_conv_to_i8: dest:i src1:f len:49
442 float_conv_to_u4: dest:i src1:f len:49
443 float_conv_to_u8: dest:i src1:f len:49
444 float_conv_to_u2: dest:i src1:f len:49
445 float_conv_to_u1: dest:i src1:f len:49
446 float_conv_to_i: dest:i src1:f len:49
447 float_conv_to_ovf_i: dest:a src1:f len:40
448 float_conv_to_ovd_u: dest:a src1:f len:40
455 float_conv_to_ovf_i1_un:
456 float_conv_to_ovf_i2_un:
457 float_conv_to_ovf_i4_un:
458 float_conv_to_ovf_i8_un:
459 float_conv_to_ovf_u1_un:
460 float_conv_to_ovf_u2_un:
461 float_conv_to_ovf_u4_un:
462 float_conv_to_ovf_u8_un:
463 float_conv_to_ovf_i_un:
464 float_conv_to_ovf_u_un:
465 float_conv_to_ovf_i1:
466 float_conv_to_ovf_u1:
467 float_conv_to_ovf_i2:
468 float_conv_to_ovf_u2:
469 float_conv_to_ovf_i4:
470 float_conv_to_ovf_u4:
471 float_conv_to_ovf_i8:
472 float_conv_to_ovf_u8:
473 float_ceq: dest:i src1:f src2:f len:35
474 float_cgt: dest:i src1:f src2:f len:35
475 float_cgt_un: dest:i src1:f src2:f len:48
476 float_clt: dest:i src1:f src2:f len:35
477 float_clt_un: dest:i src1:f src2:f len:42
478 float_ceq_membase: dest:i src1:f src2:b len:35
479 float_cgt_membase: dest:i src1:f src2:b len:35
480 float_cgt_un_membase: dest:i src1:f src2:b len:48
481 float_clt_membase: dest:i src1:f src2:b len:35
482 float_clt_un_membase: dest:i src1:f src2:b len:42
483 float_conv_to_u: dest:i src1:f len:46
484 fmove: dest:f src1:f len:8
486 aot_const: dest:i len:10
487 x86_test_null: src1:i len:5
488 x86_compare_membase_reg: src1:b src2:i len:9
489 x86_compare_membase_imm: src1:b len:13
490 x86_compare_reg_membase: src1:i src2:b len:8
491 x86_inc_reg: dest:i src1:i clob:1 len:3
492 x86_inc_membase: src1:b len:8
493 x86_dec_reg: dest:i src1:i clob:1 len:3
494 x86_dec_membase: src1:b len:8
495 x86_add_membase_imm: src1:b len:13
496 x86_sub_membase_imm: src1:b len:13
497 x86_push: src1:i len:3
499 x86_push_membase: src1:b len:8
500 x86_push_obj: src1:b len:40
501 x86_lea: dest:i src1:i src2:i len:8
502 x86_lea_membase: dest:i src1:i len:11
503 x86_xchg: src1:i src2:i clob:x len:2
504 x86_fpop: src1:f len:3
505 x86_fp_load_i8: dest:f src1:b len:8
506 x86_fp_load_i4: dest:f src1:b len:8
507 x86_seteq_membase: src1:b len:9
508 x86_add_membase: dest:i src1:i src2:b clob:1 len:13
509 x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
510 x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
511 tls_get: dest:i len:13
512 amd64_test_null: src1:i len:5
513 amd64_icompare_membase_reg: src1:b src2:i len:8
514 amd64_icompare_membase_imm: src1:b len:13
515 amd64_icompare_reg_membase: src1:i src2:b len:8
516 amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
517 amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
518 atomic_add_i4: src1:b src2:i dest:i len:32
519 atomic_add_new_i4: src1:b src2:i dest:i len:32
520 atomic_exchange_i4: src1:b src2:i dest:i len:32
521 atomic_add_i8: src1:b src2:i dest:i len:32
522 atomic_add_new_i8: src1:b src2:i dest:i len:32
523 atomic_exchange_i8: src1:b src2:i dest:i len:32
524 adc: dest:i src1:i src2:i len:3 clob:1
525 addcc: dest:i src1:i src2:i len:3 clob:1
526 subcc: dest:i src1:i src2:i len:3 clob:1
527 adc_imm: dest:i src1:i len:8 clob:1
528 sbb: dest:i src1:i src2:i len:3 clob:1
529 sbb_imm: dest:i src1:i len:8 clob:1
531 sin: dest:f src1:f len:32
532 cos: dest:f src1:f len:32
533 abs: dest:f src1:f len:32
534 tan: dest:f src1:f len:59
535 atan: dest:f src1:f len:9
536 sqrt: dest:f src1:f len:32
537 op_bigmul: len:3 dest:i src1:a src2:i
538 op_bigmul_un: len:3 dest:i src1:a src2:i
539 sext_i1: dest:i src1:i len:4
540 sext_i2: dest:i src1:i len:4
541 sext_i4: dest:i src1:i len:8
545 int_add: dest:i src1:i src2:i clob:1 len:64
546 int_sub: dest:i src1:i src2:i clob:1 len:64
547 int_mul: dest:i src1:i src2:i clob:1 len:64
548 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
549 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
550 int_div: dest:a src1:a src2:i clob:d len:64
551 int_div_un: dest:a src1:a src2:i clob:d len:64
552 int_rem: dest:d src1:a src2:i clob:a len:64
553 int_rem_un: dest:d src1:a src2:i clob:a len:64
554 int_and: dest:i src1:i src2:i clob:1 len:64
555 int_or: dest:i src1:i src2:i clob:1 len:64
556 int_xor: dest:i src1:i src2:i clob:1 len:64
557 int_shl: dest:i src1:i src2:s clob:1 len:64
558 int_shr: dest:i src1:i src2:s clob:1 len:64
559 int_shr_un: dest:i src1:i src2:s clob:1 len:64
560 int_adc: dest:i src1:i src2:i clob:1 len:64
561 int_adc_imm: dest:i src1:i clob:1 len:64
562 int_sbb: dest:i src1:i src2:i clob:1 len:64
563 int_sbb_imm: dest:i src1:i clob:1 len:64
564 int_addcc: dest:i src1:i src2:i clob:1 len:64
565 int_subcc: dest:i src1:i src2:i clob:1 len:64
566 int_add_imm: dest:i src1:i clob:1 len:64
567 int_sub_imm: dest:i src1:i clob:1 len:64
568 int_mul_imm: dest:i src1:i clob:1 len:64
569 int_div_imm: dest:a src1:i clob:d len:64
570 int_div_un_imm: dest:a src1:i clob:d len:64
571 int_rem_imm: dest:d src1:i clob:a len:64
572 int_rem_un_imm: dest:d src1:i clob:a len:64
573 int_and_imm: dest:i src1:i clob:1 len:64
574 int_or_imm: dest:i src1:i clob:1 len:64
575 int_xor_imm: dest:i src1:i clob:1 len:64
576 int_shl_imm: dest:i src1:i clob:1 len:64
577 int_shr_imm: dest:i src1:i clob:1 len:64
578 int_shr_un_imm: dest:i src1:i clob:1 len:64
579 int_neg: dest:i src1:i clob:1 len:64
580 int_not: dest:i src1:i clob:1 len:64
581 int_ceq: dest:c len:64
582 int_cgt: dest:c len:64
583 int_cgt_un: dest:c len:64
584 int_clt: dest:c len:64
585 int_clt_un: dest:c len:64