1 # Alpha-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
15 # b base register (used in address references)
16 # f floating point register
20 # l long reg (forced eax:edx)
22 # c register which can be used as a byte register (RAX..RDX)
24 # len:number describe the maximun length in bytes of the instruction
25 # number is a positive integer. If the length is not specified
26 # it defaults to zero. But lengths are only checked if the given opcode
27 # is encountered during compilation. Some opcodes, like CONV_U4 are
28 # transformed into other opcodes in the brg files, so they do not show up
29 # during code generation.
31 # cost:number describe how many cycles are needed to complete the instruction (unused)
33 # clob:spec describe if the instruction clobbers registers or has special needs
35 # c clobbers caller-save registers
36 # 1 clobbers the first source register
39 # x both the source operands are clobbered (xchg)
42 # flags:spec describe if the instruction uses or sets the flags (unused)
46 # m uses and modifies the flags
48 # res:spec describe what units are used in the processor (unused)
50 # delay: describe delay slots (unused)
52 # the required specifiers are: len, clob (if registers are clobbered), the registers
53 # specifiers if the registers are actually used, flags (when scheduling is implemented).
55 # See the code in mini-x86.c for more details on how the specifiers are used.
73 ldind.i1: dest:i len:8
74 ldind.u1: dest:i len:8
75 ldind.i2: dest:i len:8
76 ldind.u2: dest:i len:8
77 ldind.i4: dest:i len:9
78 ldind.u4: dest:i len:8
80 ldind.ref: dest:i len:8
81 stind.ref: src1:b src2:i
82 stind.i1: src1:b src2:i
83 stind.i2: src1:b src2:i
84 stind.i4: src1:b src2:i
85 stind.r4: dest:f src1:b
86 stind.r8: dest:f src1:b
87 add: dest:i src1:i src2:i len:4
88 sub: dest:i src1:i src2:i len:4
89 mul: dest:i src1:i src2:i len:4
90 div: dest:a src1:a src2:i len:16 clob:d
91 div.un: dest:a src1:a src2:i len:16 clob:d
92 rem: dest:d src1:a src2:i len:16 clob:a
93 rem.un: dest:d src1:a src2:i len:16 clob:a
94 and: dest:i src1:i src2:i len:4
95 or: dest:i src1:i src2:i len:4
96 xor: dest:i src1:i src2:i len:4
97 shl: dest:i src1:i src2:s len:4
98 shr: dest:i src1:i src2:s len:8
99 shr.un: dest:i src1:i src2:s len:8
100 neg: dest:i src1:i len:4
101 not: dest:i src1:i len:4
102 conv.i1: dest:i src1:i len:4
103 conv.i2: dest:i src1:i len:4
104 conv.i4: dest:i src1:i len:4
105 conv.i8: dest:i src1:i len:4
106 conv.r4: dest:f src1:i len:20
107 conv.r8: dest:f src1:i len:20
108 conv.u4: dest:i src1:i len:4
109 conv.u8: dest:i src1:i len:4
110 conv.r.un: dest:f src1:i len:8
112 op_rethrow: src1:i len:20
113 conv.ovf.i4.un: dest:i src1:i len:16
115 conv.ovf.u4: dest:i src1:i len:15
116 ckfinite: dest:f src1:f len:43
117 conv.u2: dest:i src1:i len:4
118 conv.u1: dest:i src1:i len:4
119 conv.i: dest:i src1:i len:4
120 mul.ovf: dest:i src1:i src2:i clob:1 len:10
121 # this opcode is handled specially in the code generator
122 mul.ovf.un: dest:i src1:i src2:i len:18
123 conv.u: dest:i src1:i len:4
129 localloc: dest:i src1:i len:84
130 compare: src1:i src2:i len:4
131 lcompare: src1:i src2:i len:4
132 icompare: src1:i src2:i len:4
133 compare_imm: src1:i len:4
134 icompare_imm: src1:i len:4
135 fcompare: src1:f src2:f len:4
137 alpha_cmp_eq: src1:i src2:i len:4
138 alpha_cmp_imm_eq: src1:i len:4
139 alpha_cmp_ule: src1:i src2:i len:4
140 alpha_cmp_imm_ule: src1:i len:4
141 alpha_cmp_le: src1:i src2:i len:4
142 alpha_cmp_imm_le: src1:i len:4
143 alpha_cmp_lt: src1:i src2:i len:4
144 alpha_cmp_imm_lt: src1:i len:4
145 alpha_cmp_ult: src1:i src2:i len:4
146 alpha_cmp_imm_ult: src1:i len:4
148 alpha_cmpt_eq: src1:f src2:f len:4
150 oparglist: src1:b len:11
153 setret: dest:a src1:i len:4
154 setlret: dest:i src1:i src2:i len:4
155 checkthis: src1:b len:4
156 call: dest:a clob:c len:64
158 voidcall: clob:c len:64
159 voidcall_reg: src1:i clob:c len:64
160 voidcall_membase: src1:b clob:c len:64
161 fcall: dest:f len:64 clob:c
162 fcall_reg: dest:f src1:i len:64 clob:c
163 fcall_membase: dest:f src1:b len:64 clob:c
164 lcall: dest:a len:64 clob:c
165 lcall_reg: dest:a src1:i len:64 clob:c
166 lcall_membase: dest:a src1:b len:64 clob:c
168 vcall_reg: src1:i len:64 clob:c
169 vcall_membase: src1:b len:64 clob:c
170 call_reg: dest:a src1:i len:64 clob:c
171 call_membase: dest:a src1:b len:64 clob:c
172 iconst: dest:i len:40
173 i8const: dest:i len:40
174 r4const: dest:f len:40
175 r8const: dest:f len:40
176 store_membase_imm: dest:b len:4
177 store_membase_reg: dest:b src1:i len:4
178 storei8_membase_reg: dest:b src1:i len:4
179 storei1_membase_imm: dest:b len:4
180 storei1_membase_reg: dest:b src1:c len:24
181 storei2_membase_imm: dest:b len:4
182 storei2_membase_reg: dest:b src1:i len:44
183 storei4_membase_imm: dest:b len:4
184 storei4_membase_reg: dest:b src1:i len:4
185 storei8_membase_imm: dest:b len:4
186 storer4_membase_reg: dest:b src1:f len:4
187 storer8_membase_reg: dest:b src1:f len:4
188 load_membase: dest:i src1:b len:4
189 loadi1_membase: dest:c src1:b len:16
190 loadu1_membase: dest:c src1:b len:12
191 loadi2_membase: dest:i src1:b len:28
192 loadu2_membase: dest:i src1:b len:24
193 loadi4_membase: dest:i src1:b len:4
194 loadu4_membase: dest:i src1:b len:8
195 loadi8_membase: dest:i src1:b len:4
196 loadr4_membase: dest:f src1:b len:4
197 loadr8_membase: dest:f src1:b len:4
198 loadr8_spill_membase: src1:b len:4
199 loadu4_mem: dest:i len:4
200 # amd64_loadi8_memindex: dest:i src1:i src2:i len:10
201 move: dest:i src1:i len:4
202 add_imm: dest:i src1:i len:4
203 sub_imm: dest:i src1:i len:4
204 mul_imm: dest:i src1:i len:11
205 # there is no actual support for division or reminder by immediate
206 # we simulate them, though (but we need to change the burg rules
207 # to allocate a symbolic reg for src2)
208 div_imm: dest:a src1:i src2:i len:16 clob:d
209 div_un_imm: dest:a src1:i src2:i len:16 clob:d
210 rem_imm: dest:d src1:i src2:i len:16 clob:a
211 rem_un_imm: dest:d src1:i src2:i len:16 clob:a
212 and_imm: dest:i src1:i len:4
213 or_imm: dest:i src1:i len:4
214 xor_imm: dest:i src1:i len:4
215 shl_imm: dest:i src1:i len:4
216 shr_imm: dest:i src1:i len:8
217 shr_un_imm: dest:i src1:i len:8
219 cond_exc_ne_un: len:8
221 cond_exc_lt_un: len:8
223 cond_exc_gt_un: len:28
225 cond_exc_ge_un: len:8
227 cond_exc_le_un: len:8
234 long_mul: dest:i src1:i src2:i clob:1 len:4
235 long_mul_imm: dest:i src1:i clob:1 len:12
236 long_div: dest:a src1:a src2:i len:16 clob:d
237 long_div_un: dest:a src1:a src2:i len:16 clob:d
238 long_rem: dest:d src1:a src2:i len:16 clob:a
239 long_rem_un: dest:d src1:a src2:i len:16 clob:a
240 long_shl: dest:i src1:i src2:s clob:1 len:31
241 long_shr: dest:i src1:i src2:s len:4
242 long_shr_un: dest:i src1:i src2:s len:4
243 long_conv_to_r4: dest:f src1:i len:20
244 long_conv_to_r8: dest:f src1:i len:20
245 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
246 long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
247 long_mul_ovf_un: dest:i src1:i src2:i len:22
248 long_conv_to_r_un: dest:f src1:i src2:i len:48
249 long_shr_imm: dest:i src1:i len:4
250 long_shr_un_imm: dest:i src1:i len:4
251 long_shl_imm: dest:i src1:i clob:1 len:11
262 float_add: dest:f src1:f src2:f len:4
263 float_sub: dest:f src1:f src2:f len:4
264 float_mul: dest:f src1:f src2:f len:5
265 float_div: dest:f src1:f src2:f len:5
266 float_div_un: dest:f src1:f src2:f len:5
267 float_rem: dest:f src1:f src2:f len:19
268 float_rem_un: dest:f src1:f src2:f len:19
269 float_neg: dest:f src1:f len:23
270 float_not: dest:f src1:f len:3
271 float_conv_to_i1: dest:i src1:f len:49
272 float_conv_to_i2: dest:i src1:f len:49
273 float_conv_to_i4: dest:i src1:f len:49
274 float_conv_to_i8: dest:i src1:f len:49
275 float_conv_to_u4: dest:i src1:f len:49
276 float_conv_to_u8: dest:i src1:f len:49
277 float_conv_to_u2: dest:i src1:f len:49
278 float_conv_to_u1: dest:i src1:f len:49
279 float_conv_to_i: dest:i src1:f len:49
280 float_conv_to_ovf_i: dest:a src1:f len:40
281 float_conv_to_ovd_u: dest:a src1:f len:40
282 float_conv_to_r4: dest:f src1:f len:8
283 float_conv_to_r8: dest:f src1:f len:8
285 float_ceq: dest:i src1:f src2:f len:35
286 float_cgt: dest:i src1:f src2:f len:35
287 float_cgt_un: dest:i src1:f src2:f len:48
288 float_clt: dest:i src1:f src2:f len:35
289 float_clt_un: dest:i src1:f src2:f len:42
290 float_ceq_membase: dest:i src1:f src2:b len:35
291 float_cgt_membase: dest:i src1:f src2:b len:35
292 float_cgt_un_membase: dest:i src1:f src2:b len:48
293 float_clt_membase: dest:i src1:f src2:b len:35
294 float_clt_un_membase: dest:i src1:f src2:b len:42
295 float_conv_to_u: dest:i src1:f len:46
296 fmove: dest:f src1:f len:8
298 start_handler: len:96
301 aot_const: dest:i len:10
302 # x86_test_null: src1:i len:5
303 # x86_compare_membase_reg: src1:b src2:i len:9
304 # x86_compare_membase_imm: src1:b len:13
305 # x86_compare_reg_membase: src1:i src2:b len:8
306 # x86_inc_reg: dest:i src1:i clob:1 len:3
307 # x86_inc_membase: src1:b len:8
308 # x86_dec_reg: dest:i src1:i clob:1 len:3
309 # x86_dec_membase: src1:b len:8
310 # x86_add_membase_imm: src1:b len:13
311 # x86_sub_membase_imm: src1:b len:13
312 # x86_push: src1:i len:3
313 # x86_push_imm: len:6
314 # x86_push_membase: src1:b len:8
315 # x86_push_obj: src1:b len:40
316 # x86_lea: dest:i src1:i src2:i len:8
317 # x86_lea_membase: dest:i src1:i len:11
318 # x86_xchg: src1:i src2:i clob:x len:2
319 # x86_fpop: src1:f len:3
320 # x86_fp_load_i8: dest:f src1:b len:8
321 # x86_fp_load_i4: dest:f src1:b len:8
322 # x86_seteq_membase: src1:b len:9
323 # x86_add_membase: dest:i src1:i src2:b clob:1 len:13
324 # x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
325 # x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
326 tls_get: dest:i len:13
327 # amd64_test_null: src1:i len:5
328 # amd64_icompare_membase_reg: src1:b src2:i len:8
329 # amd64_icompare_membase_imm: src1:b len:13
330 # amd64_icompare_reg_membase: src1:i src2:b len:8
331 # amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
332 # amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
333 atomic_add_i4: src1:b src2:i dest:i len:32
334 atomic_add_new_i4: src1:b src2:i dest:i len:32
335 atomic_exchange_i4: src1:b src2:i dest:i len:32
336 atomic_add_i8: src1:b src2:i dest:i len:32
337 atomic_add_new_i8: src1:b src2:i dest:i len:32
338 atomic_exchange_i8: src1:b src2:i dest:i len:32
339 memory_barrier: len:16
340 adc: dest:i src1:i src2:i len:3 clob:1
341 addcc: dest:i src1:i src2:i len:3 clob:1
342 subcc: dest:i src1:i src2:i len:3 clob:1
343 adc_imm: dest:i src1:i len:8 clob:1
344 sbb: dest:i src1:i src2:i len:3 clob:1
345 sbb_imm: dest:i src1:i len:8 clob:1
347 sin: dest:f src1:f len:32
348 cos: dest:f src1:f len:32
349 abs: dest:f src1:f len:32
350 tan: dest:f src1:f len:59
351 atan: dest:f src1:f len:9
352 sqrt: dest:f src1:f len:32
353 op_bigmul: len:3 dest:i src1:a src2:i
354 op_bigmul_un: len:3 dest:i src1:a src2:i
355 sext_i1: dest:i src1:i len:8
356 sext_i2: dest:i src1:i len:8
357 sext_i4: dest:i src1:i len:8
361 int_add: dest:i src1:i src2:i len:4
362 int_sub: dest:i src1:i src2:i len:4
363 int_mul: dest:i src1:i src2:i clob:1 len:64
364 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
365 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
366 int_div: dest:a src1:a src2:i clob:d len:64
367 int_div_un: dest:a src1:a src2:i clob:d len:64
368 int_rem: dest:d src1:a src2:i clob:a len:64
369 int_rem_un: dest:d src1:a src2:i clob:a len:64
370 int_and: dest:i src1:i src2:i len:4
371 int_or: dest:i src1:i src2:i len:4
372 int_xor: dest:i src1:i src2:i len:4
373 int_shl: dest:i src1:i src2:s len:4
374 int_shr: dest:i src1:i src2:s len:8
375 int_shr_un: dest:i src1:i src2:s len:8
376 int_adc: dest:i src1:i src2:i clob:1 len:64
377 int_adc_imm: dest:i src1:i clob:1 len:64
378 int_sbb: dest:i src1:i src2:i clob:1 len:64
379 int_sbb_imm: dest:i src1:i clob:1 len:64
380 int_addcc: dest:i src1:i src2:i len:4
381 int_subcc: dest:i src1:i src2:i len:4
382 int_add_imm: dest:i src1:i len:4
383 int_sub_imm: dest:i src1:i len:4
384 int_mul_imm: dest:i src1:i clob:1 len:64
385 int_div_imm: dest:a src1:i clob:d len:64
386 int_div_un_imm: dest:a src1:i clob:d len:64
387 int_rem_imm: dest:d src1:i clob:a len:64
388 int_rem_un_imm: dest:d src1:i clob:a len:64
389 int_and_imm: dest:i src1:i len:4
390 int_or_imm: dest:i src1:i len:4
391 int_xor_imm: dest:i src1:i len:4
392 int_shl_imm: dest:i src1:i len:4
393 int_shr_imm: dest:i src1:i len:8
394 int_shr_un_imm: dest:i src1:i len:8
395 int_neg: dest:i src1:i len:4
396 int_not: dest:i src1:i len:4
397 int_ceq: dest:c len:64
398 int_cgt: dest:c len:64
399 int_cgt_un: dest:c len:64
400 int_clt: dest:c len:64
401 int_clt_un: dest:c len:64