2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 // x86 register numbers
33 // opcodes for alu instructions
47 // opcodes for shift instructions
62 // opcodes for floating-point instructions
76 // integer conditions codes
79 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
80 X86_CC_NE = 1, X86_CC_NZ = 1,
81 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
82 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
83 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
84 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
85 X86_CC_LZ = 6, X86_CC_S = 6,
86 X86_CC_GEZ = 7, X86_CC_NS = 7,
87 X86_CC_P = 8, X86_CC_PE = 8,
88 X86_CC_NP = 9, X86_CC_PO = 9,
100 X86_FP_CC_MASK = 0x4500
103 /* FP control word */
105 X86_FPCW_INVOPEX_MASK = 0x1,
106 X86_FPCW_DENOPEX_MASK = 0x2,
107 X86_FPCW_ZERODIV_MASK = 0x4,
108 X86_FPCW_OVFEX_MASK = 0x8,
109 X86_FPCW_UNDFEX_MASK = 0x10,
110 X86_FPCW_PRECEX_MASK = 0x20,
111 X86_FPCW_PRECC_MASK = 0x300,
112 X86_FPCW_ROUNDC_MASK = 0xc00,
114 /* values for precision control */
115 X86_FPCW_PREC_SINGLE = 0,
116 X86_FPCW_PREC_DOUBLE = 0x200,
117 X86_FPCW_PREC_EXTENDED = 0x300,
119 /* values for rounding control */
120 X86_FPCW_ROUND_NEAREST = 0,
121 X86_FPCW_ROUND_DOWN = 0x400,
122 X86_FPCW_ROUND_UP = 0x800,
123 X86_FPCW_ROUND_TOZERO = 0xc00
130 X86_LOCK_PREFIX = 0xF0,
131 X86_REPNZ_PREFIX = 0xF2,
132 X86_REPZ_PREFIX = 0xF3,
133 X86_REP_PREFIX = 0xF3,
134 X86_CS_PREFIX = 0x2E,
135 X86_SS_PREFIX = 0x36,
136 X86_DS_PREFIX = 0x3E,
137 X86_ES_PREFIX = 0x26,
138 X86_FS_PREFIX = 0x64,
139 X86_GS_PREFIX = 0x65,
140 X86_UNLIKELY_PREFIX = 0x2E,
141 X86_LIKELY_PREFIX = 0x3E,
142 X86_OPERAND_PREFIX = 0x66,
143 X86_ADDRESS_PREFIX = 0x67
146 static const unsigned char
147 x86_cc_unsigned_map [X86_NCC] = {
162 static const unsigned char
163 x86_cc_signed_map [X86_NCC] = {
183 #define X86_NOBASEREG (-1)
186 // bitvector mask for callee-saved registers
188 #define X86_ESI_MASK (1<<X86_ESI)
189 #define X86_EDI_MASK (1<<X86_EDI)
190 #define X86_EBX_MASK (1<<X86_EBX)
191 #define X86_EBP_MASK (1<<X86_EBP)
193 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
194 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
195 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
197 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
198 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
200 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
205 // +--------------------------------+
206 // | in_arg[0] = var[0] |
207 // | in_arg[1] = var[1] |
209 // | in_arg[n_arg-1] = var[n_arg-1] |
210 // +--------------------------------+
212 // +--------------------------------+
213 // | saved EBP | <-- frame pointer (EBP)
214 // +--------------------------------+
216 // +--------------------------------+
218 // | var[n_arg+1] | local variables area
221 // +--------------------------------+
224 // | spill area | area for spilling mimic stack
226 // +--------------------------------|
228 // | ebp [ESP_Frame only] |
229 // | esi | 0..3 callee-saved regs
230 // | edi | <-- stack pointer (ESP)
231 // +--------------------------------+
233 // | stk1 | operand stack area/
234 // | . . . | out args
236 // +--------------------------------|
243 * useful building blocks
245 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
246 #define x86_imm_emit32(inst,imm) \
248 x86_imm_buf imb; imb.val = (int) (imm); \
249 *(inst)++ = imb.b [0]; \
250 *(inst)++ = imb.b [1]; \
251 *(inst)++ = imb.b [2]; \
252 *(inst)++ = imb.b [3]; \
254 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
255 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
256 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
257 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
259 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
260 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
261 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
262 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
264 #define x86_membase_emit(inst,r,basereg,disp) do {\
265 if ((basereg) == X86_ESP) { \
267 x86_address_byte ((inst), 0, (r), X86_ESP); \
268 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
269 } else if (x86_is_imm8((disp))) { \
270 x86_address_byte ((inst), 1, (r), X86_ESP); \
271 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
272 x86_imm_emit8 ((inst), (disp)); \
274 x86_address_byte ((inst), 2, (r), X86_ESP); \
275 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
276 x86_imm_emit32 ((inst), (disp)); \
280 if ((disp) == 0 && (basereg) != X86_EBP) { \
281 x86_address_byte ((inst), 0, (r), (basereg)); \
284 if (x86_is_imm8((disp))) { \
285 x86_address_byte ((inst), 1, (r), (basereg)); \
286 x86_imm_emit8 ((inst), (disp)); \
288 x86_address_byte ((inst), 2, (r), (basereg)); \
289 x86_imm_emit32 ((inst), (disp)); \
293 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
295 if ((basereg) == X86_NOBASEREG) { \
296 x86_address_byte ((inst), 0, (r), 4); \
297 x86_address_byte ((inst), (shift), (indexreg), 5); \
298 x86_imm_emit32 ((inst), (disp)); \
299 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
300 x86_address_byte ((inst), 0, (r), 4); \
301 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
302 } else if (x86_is_imm8((disp))) { \
303 x86_address_byte ((inst), 1, (r), 4); \
304 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
305 x86_imm_emit8 ((inst), (disp)); \
307 x86_address_byte ((inst), 2, (r), 4); \
308 x86_address_byte ((inst), (shift), (indexreg), 5); \
309 x86_imm_emit32 ((inst), (disp)); \
314 * target is the position in the code where to jump to:
316 * .. output loop code...
317 * x86_mov_reg_imm (code, X86_EAX, 0);
319 * x86_loop (code, -1);
323 * x86_patch (loop, target);
325 * ins should point at the start of the instruction that encodes a target.
326 * the instruction is inspected for validity and the correct displacement
329 #define x86_patch(ins,target) \
331 unsigned char* pos = (ins) + 1; \
332 int disp, size = 0; \
333 switch (*(unsigned char*)(ins)) { \
334 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
335 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
336 ++size; ++pos; break; /* prefix for 32-bit disp */ \
337 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
338 case 0xeb: /* jump8 */ \
339 /* conditional jump opcodes */ \
340 case 0x70: case 0x71: case 0x72: case 0x73: \
341 case 0x74: case 0x75: case 0x76: case 0x77: \
342 case 0x78: case 0x79: case 0x7a: case 0x7b: \
343 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
345 default: assert (0); \
347 disp = (target) - pos; \
348 if (size) x86_imm_emit32 (pos, disp - 4); \
349 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
353 #define x86_breakpoint(inst) \
358 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
359 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
360 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
361 #define x86_stosd(inst) x86_stosl((inst))
362 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
363 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
364 #define x86_movsd(inst) x86_movsl((inst))
366 #define x86_prefix(inst,p) do { *(inst)++ =(unsigned char) (p); } while (0)
368 #define x86_rdtsc(inst) \
374 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
376 *(inst)++ = (unsigned char)0x0f; \
377 *(inst)++ = (unsigned char)0xb1; \
378 x86_reg_emit ((inst), (reg), (dreg)); \
381 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
383 *(inst)++ = (unsigned char)0x0f; \
384 *(inst)++ = (unsigned char)0xb1; \
385 x86_mem_emit ((inst), (reg), (mem)); \
388 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
390 *(inst)++ = (unsigned char)0x0f; \
391 *(inst)++ = (unsigned char)0xb1; \
392 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
395 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
398 *(inst)++ = (unsigned char)0x86; \
400 *(inst)++ = (unsigned char)0x87; \
401 x86_reg_emit ((inst), (reg), (dreg)); \
404 #define x86_xchg_mem_reg(inst,mem,reg,size) \
407 *(inst)++ = (unsigned char)0x86; \
409 *(inst)++ = (unsigned char)0x87; \
410 x86_mem_emit ((inst), (reg), (mem)); \
413 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
416 *(inst)++ = (unsigned char)0x86; \
418 *(inst)++ = (unsigned char)0x87; \
419 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
422 #define x86_inc_mem(inst,mem) \
424 *(inst)++ = (unsigned char)0xff; \
425 x86_mem_emit ((inst), 0, (mem)); \
428 #define x86_inc_membase(inst,basereg,disp) \
430 *(inst)++ = (unsigned char)0xff; \
431 x86_membase_emit ((inst), 0, (basereg), (disp)); \
434 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
436 #define x86_dec_mem(inst,mem) \
438 *(inst)++ = (unsigned char)0xff; \
439 x86_mem_emit ((inst), 1, (mem)); \
442 #define x86_dec_membase(inst,basereg,disp) \
444 *(inst)++ = (unsigned char)0xff; \
445 x86_membase_emit ((inst), 1, (basereg), (disp)); \
448 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
450 #define x86_not_mem(inst,mem) \
452 *(inst)++ = (unsigned char)0xf7; \
453 x86_mem_emit ((inst), 2, (mem)); \
456 #define x86_not_membase(inst,basereg,disp) \
458 *(inst)++ = (unsigned char)0xf7; \
459 x86_membase_emit ((inst), 2, (basereg), (disp)); \
462 #define x86_not_reg(inst,reg) \
464 *(inst)++ = (unsigned char)0xf7; \
465 x86_reg_emit ((inst), 2, (reg)); \
468 #define x86_neg_mem(inst,mem) \
470 *(inst)++ = (unsigned char)0xf7; \
471 x86_mem_emit ((inst), 3, (mem)); \
474 #define x86_neg_membase(inst,basereg,disp) \
476 *(inst)++ = (unsigned char)0xf7; \
477 x86_membase_emit ((inst), 3, (basereg), (disp)); \
480 #define x86_neg_reg(inst,reg) \
482 *(inst)++ = (unsigned char)0xf7; \
483 x86_reg_emit ((inst), 3, (reg)); \
486 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
488 #define x86_alu_reg_imm(inst,opc,reg,imm) \
490 if ((reg) == X86_EAX) { \
491 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
492 x86_imm_emit32 ((inst), (imm)); \
495 if (x86_is_imm8((imm))) { \
496 *(inst)++ = (unsigned char)0x83; \
497 x86_reg_emit ((inst), (opc), (reg)); \
498 x86_imm_emit8 ((inst), (imm)); \
500 *(inst)++ = (unsigned char)0x81; \
501 x86_reg_emit ((inst), (opc), (reg)); \
502 x86_imm_emit32 ((inst), (imm)); \
506 #define x86_alu_mem_imm(inst,opc,mem,imm) \
508 if (x86_is_imm8((imm))) { \
509 *(inst)++ = (unsigned char)0x83; \
510 x86_mem_emit ((inst), (opc), (mem)); \
511 x86_imm_emit8 ((inst), (imm)); \
513 *(inst)++ = (unsigned char)0x81; \
514 x86_mem_emit ((inst), (opc), (mem)); \
515 x86_imm_emit32 ((inst), (imm)); \
519 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
521 if (x86_is_imm8((imm))) { \
522 *(inst)++ = (unsigned char)0x83; \
523 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
524 x86_imm_emit8 ((inst), (imm)); \
526 *(inst)++ = (unsigned char)0x81; \
527 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
528 x86_imm_emit32 ((inst), (imm)); \
532 #define x86_alu_mem_reg(inst,opc,mem,reg) \
534 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
535 x86_mem_emit ((inst), (reg), (mem)); \
538 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
540 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
541 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
544 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
546 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
547 x86_reg_emit ((inst), (dreg), (reg)); \
551 * @x86_alu_reg8_reg8:
552 * Supports ALU operations between two 8-bit registers.
553 * dreg := dreg opc reg
554 * X86_Reg_No enum is used to specify the registers.
555 * Additionally is_*_h flags are used to specify what part
556 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
557 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
559 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
561 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
562 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
565 #define x86_alu_reg_mem(inst,opc,reg,mem) \
567 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
568 x86_mem_emit ((inst), (reg), (mem)); \
571 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
573 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
574 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
577 #define x86_test_reg_imm(inst,reg,imm) \
579 if ((reg) == X86_EAX) { \
580 *(inst)++ = (unsigned char)0xa9; \
582 *(inst)++ = (unsigned char)0xf7; \
583 x86_reg_emit ((inst), 0, (reg)); \
585 x86_imm_emit32 ((inst), (imm)); \
588 #define x86_test_mem_imm(inst,mem,imm) \
590 *(inst)++ = (unsigned char)0xf7; \
591 x86_mem_emit ((inst), 0, (mem)); \
592 x86_imm_emit32 ((inst), (imm)); \
595 #define x86_test_membase_imm(inst,basereg,disp,imm) \
597 *(inst)++ = (unsigned char)0xf7; \
598 x86_membase_emit ((inst), 0, (basereg), (disp)); \
599 x86_imm_emit32 ((inst), (imm)); \
602 #define x86_test_reg_reg(inst,dreg,reg) \
604 *(inst)++ = (unsigned char)0x85; \
605 x86_reg_emit ((inst), (reg), (dreg)); \
608 #define x86_test_mem_reg(inst,mem,reg) \
610 *(inst)++ = (unsigned char)0x85; \
611 x86_mem_emit ((inst), (reg), (mem)); \
614 #define x86_test_membase_reg(inst,basereg,disp,reg) \
616 *(inst)++ = (unsigned char)0x85; \
617 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
620 #define x86_shift_reg_imm(inst,opc,reg,imm) \
623 *(inst)++ = (unsigned char)0xd1; \
624 x86_reg_emit ((inst), (opc), (reg)); \
626 *(inst)++ = (unsigned char)0xc1; \
627 x86_reg_emit ((inst), (opc), (reg)); \
628 x86_imm_emit8 ((inst), (imm)); \
632 #define x86_shift_mem_imm(inst,opc,mem,imm) \
635 *(inst)++ = (unsigned char)0xd1; \
636 x86_mem_emit ((inst), (opc), (mem)); \
638 *(inst)++ = (unsigned char)0xc1; \
639 x86_mem_emit ((inst), (opc), (mem)); \
640 x86_imm_emit8 ((inst), (imm)); \
644 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
647 *(inst)++ = (unsigned char)0xd1; \
648 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
650 *(inst)++ = (unsigned char)0xc1; \
651 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
652 x86_imm_emit8 ((inst), (imm)); \
656 #define x86_shift_reg(inst,opc,reg) \
658 *(inst)++ = (unsigned char)0xd3; \
659 x86_reg_emit ((inst), (opc), (reg)); \
662 #define x86_shift_mem(inst,opc,mem) \
664 *(inst)++ = (unsigned char)0xd3; \
665 x86_mem_emit ((inst), (opc), (mem)); \
668 #define x86_shift_membase(inst,opc,basereg,disp) \
670 *(inst)++ = (unsigned char)0xd3; \
671 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
675 * Multi op shift missing.
678 #define x86_shrd_reg(inst,dreg,reg) \
680 *(inst)++ = (unsigned char)0x0f; \
681 *(inst)++ = (unsigned char)0xad; \
682 x86_reg_emit ((inst), (reg), (dreg)); \
685 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
687 *(inst)++ = (unsigned char)0x0f; \
688 *(inst)++ = (unsigned char)0xac; \
689 x86_reg_emit ((inst), (reg), (dreg)); \
690 x86_imm_emit8 ((inst), (shamt)); \
693 #define x86_shld_reg(inst,dreg,reg) \
695 *(inst)++ = (unsigned char)0x0f; \
696 *(inst)++ = (unsigned char)0xa5; \
697 x86_reg_emit ((inst), (reg), (dreg)); \
700 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
702 *(inst)++ = (unsigned char)0x0f; \
703 *(inst)++ = (unsigned char)0xa4; \
704 x86_reg_emit ((inst), (reg), (dreg)); \
705 x86_imm_emit8 ((inst), (shamt)); \
711 #define x86_mul_reg(inst,reg,is_signed) \
713 *(inst)++ = (unsigned char)0xf7; \
714 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
717 #define x86_mul_mem(inst,mem,is_signed) \
719 *(inst)++ = (unsigned char)0xf7; \
720 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
723 #define x86_mul_membase(inst,basereg,disp,is_signed) \
725 *(inst)++ = (unsigned char)0xf7; \
726 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
732 #define x86_imul_reg_reg(inst,dreg,reg) \
734 *(inst)++ = (unsigned char)0x0f; \
735 *(inst)++ = (unsigned char)0xaf; \
736 x86_reg_emit ((inst), (dreg), (reg)); \
739 #define x86_imul_reg_mem(inst,reg,mem) \
741 *(inst)++ = (unsigned char)0x0f; \
742 *(inst)++ = (unsigned char)0xaf; \
743 x86_mem_emit ((inst), (reg), (mem)); \
746 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
748 *(inst)++ = (unsigned char)0x0f; \
749 *(inst)++ = (unsigned char)0xaf; \
750 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
756 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
758 if (x86_is_imm8 ((imm))) { \
759 *(inst)++ = (unsigned char)0x6b; \
760 x86_reg_emit ((inst), (dreg), (reg)); \
761 x86_imm_emit8 ((inst), (imm)); \
763 *(inst)++ = (unsigned char)0x69; \
764 x86_reg_emit ((inst), (dreg), (reg)); \
765 x86_imm_emit32 ((inst), (imm)); \
769 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
771 if (x86_is_imm8 ((imm))) { \
772 *(inst)++ = (unsigned char)0x6b; \
773 x86_mem_emit ((inst), (reg), (mem)); \
774 x86_imm_emit8 ((inst), (imm)); \
776 *(inst)++ = (unsigned char)0x69; \
777 x86_reg_emit ((inst), (reg), (mem)); \
778 x86_imm_emit32 ((inst), (imm)); \
782 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
784 if (x86_is_imm8 ((imm))) { \
785 *(inst)++ = (unsigned char)0x6b; \
786 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
787 x86_imm_emit8 ((inst), (imm)); \
789 *(inst)++ = (unsigned char)0x69; \
790 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
791 x86_imm_emit32 ((inst), (imm)); \
796 * divide EDX:EAX by rm;
797 * eax = quotient, edx = remainder
800 #define x86_div_reg(inst,reg,is_signed) \
802 *(inst)++ = (unsigned char)0xf7; \
803 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
806 #define x86_div_mem(inst,mem,is_signed) \
808 *(inst)++ = (unsigned char)0xf7; \
809 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
812 #define x86_div_membase(inst,basereg,disp,is_signed) \
814 *(inst)++ = (unsigned char)0xf7; \
815 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
818 #define x86_mov_mem_reg(inst,mem,reg,size) \
821 case 1: *(inst)++ = (unsigned char)0x88; break; \
822 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
823 case 4: *(inst)++ = (unsigned char)0x89; break; \
824 default: assert (0); \
826 x86_mem_emit ((inst), (reg), (mem)); \
829 #define x86_mov_regp_reg(inst,regp,reg,size) \
832 case 1: *(inst)++ = (unsigned char)0x88; break; \
833 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
834 case 4: *(inst)++ = (unsigned char)0x89; break; \
835 default: assert (0); \
837 x86_regp_emit ((inst), (reg), (regp)); \
840 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
843 case 1: *(inst)++ = (unsigned char)0x88; break; \
844 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
845 case 4: *(inst)++ = (unsigned char)0x89; break; \
846 default: assert (0); \
848 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
851 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
854 case 1: *(inst)++ = (unsigned char)0x88; break; \
855 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
856 case 4: *(inst)++ = (unsigned char)0x89; break; \
857 default: assert (0); \
859 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
862 #define x86_mov_reg_reg(inst,dreg,reg,size) \
865 case 1: *(inst)++ = (unsigned char)0x8a; break; \
866 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
867 case 4: *(inst)++ = (unsigned char)0x8b; break; \
868 default: assert (0); \
870 x86_reg_emit ((inst), (dreg), (reg)); \
873 #define x86_mov_reg_mem(inst,reg,mem,size) \
876 case 1: *(inst)++ = (unsigned char)0x8a; break; \
877 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
878 case 4: *(inst)++ = (unsigned char)0x8b; break; \
879 default: assert (0); \
881 x86_mem_emit ((inst), (reg), (mem)); \
884 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
887 case 1: *(inst)++ = (unsigned char)0x8a; break; \
888 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
889 case 4: *(inst)++ = (unsigned char)0x8b; break; \
890 default: assert (0); \
892 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
895 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
898 case 1: *(inst)++ = (unsigned char)0x8a; break; \
899 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
900 case 4: *(inst)++ = (unsigned char)0x8b; break; \
901 default: assert (0); \
903 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
907 * Note: x86_clear_reg () chacnges the condition code!
909 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
911 #define x86_mov_reg_imm(inst,reg,imm) \
913 *(inst)++ = (unsigned char)0xb8 + (reg); \
914 x86_imm_emit32 ((inst), (imm)); \
917 #define x86_mov_mem_imm(inst,mem,imm,size) \
920 *(inst)++ = (unsigned char)0xc6; \
921 x86_mem_emit ((inst), 0, (mem)); \
922 x86_imm_emit8 ((inst), (imm)); \
923 } else if ((size) == 2) { \
924 *(inst)++ = (unsigned char)0x66; \
925 *(inst)++ = (unsigned char)0xc7; \
926 x86_mem_emit ((inst), 0, (mem)); \
927 x86_imm_emit16 ((inst), (imm)); \
929 *(inst)++ = (unsigned char)0xc7; \
930 x86_mem_emit ((inst), 0, (mem)); \
931 x86_imm_emit32 ((inst), (imm)); \
935 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
938 *(inst)++ = (unsigned char)0xc6; \
939 x86_membase_emit ((inst), 0, (basereg), (disp)); \
940 x86_imm_emit8 ((inst), (imm)); \
941 } else if ((size) == 2) { \
942 *(inst)++ = (unsigned char)0x66; \
943 *(inst)++ = (unsigned char)0xc7; \
944 x86_membase_emit ((inst), 0, (basereg), (disp)); \
945 x86_imm_emit16 ((inst), (imm)); \
947 *(inst)++ = (unsigned char)0xc7; \
948 x86_membase_emit ((inst), 0, (basereg), (disp)); \
949 x86_imm_emit32 ((inst), (imm)); \
953 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
956 *(inst)++ = (unsigned char)0xc6; \
957 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
958 x86_imm_emit8 ((inst), (imm)); \
959 } else if ((size) == 2) { \
960 *(inst)++ = (unsigned char)0x66; \
961 *(inst)++ = (unsigned char)0xc7; \
962 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
963 x86_imm_emit16 ((inst), (imm)); \
965 *(inst)++ = (unsigned char)0xc7; \
966 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
967 x86_imm_emit32 ((inst), (imm)); \
971 #define x86_lea_mem(inst,reg,mem) \
973 *(inst)++ = (unsigned char)0x8d; \
974 x86_mem_emit ((inst), (reg), (mem)); \
977 #define x86_lea_membase(inst,reg,basereg,disp) \
979 *(inst)++ = (unsigned char)0x8d; \
980 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
983 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
985 *(inst)++ = (unsigned char)0x8d; \
986 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
989 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
991 unsigned char op = 0xb6; \
992 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
993 *(inst)++ = (unsigned char)0x0f; \
994 if ((is_signed)) op += 0x08; \
995 if ((is_half)) op += 0x01; \
997 x86_reg_emit ((inst), (dreg), (reg)); \
1000 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1002 unsigned char op = 0xb6; \
1003 *(inst)++ = (unsigned char)0x0f; \
1004 if ((is_signed)) op += 0x08; \
1005 if ((is_half)) op += 0x01; \
1007 x86_mem_emit ((inst), (dreg), (mem)); \
1010 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1012 unsigned char op = 0xb6; \
1013 *(inst)++ = (unsigned char)0x0f; \
1014 if ((is_signed)) op += 0x08; \
1015 if ((is_half)) op += 0x01; \
1017 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1020 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1022 unsigned char op = 0xb6; \
1023 *(inst)++ = (unsigned char)0x0f; \
1024 if ((is_signed)) op += 0x08; \
1025 if ((is_half)) op += 0x01; \
1027 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1030 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1031 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1033 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1035 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1036 x86_mem_emit ((inst), (opc), (mem)); \
1039 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1041 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1042 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1045 #define x86_fp_op(inst,opc,index) \
1047 *(inst)++ = (unsigned char)0xd8; \
1048 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1051 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1053 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1054 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1055 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1059 * @x86_fp_int_op_membase
1060 * Supports FPU operations between ST(0) and integer operand in memory.
1061 * Operation encoded using X86_FP_Opcode enum.
1062 * Operand is addressed by [basereg + disp].
1063 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1065 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1067 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1068 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1071 #define x86_fstp(inst,index) \
1073 *(inst)++ = (unsigned char)0xdd; \
1074 *(inst)++ = (unsigned char)0xd8+(index); \
1077 #define x86_fcompp(inst) \
1079 *(inst)++ = (unsigned char)0xde; \
1080 *(inst)++ = (unsigned char)0xd9; \
1083 #define x86_fucompp(inst) \
1085 *(inst)++ = (unsigned char)0xda; \
1086 *(inst)++ = (unsigned char)0xe9; \
1089 #define x86_fnstsw(inst) \
1091 *(inst)++ = (unsigned char)0xdf; \
1092 *(inst)++ = (unsigned char)0xe0; \
1095 #define x86_fnstcw(inst,mem) \
1097 *(inst)++ = (unsigned char)0xd9; \
1098 x86_mem_emit ((inst), 7, (mem)); \
1101 #define x86_fnstcw_membase(inst,basereg,disp) \
1103 *(inst)++ = (unsigned char)0xd9; \
1104 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1107 #define x86_fldcw(inst,mem) \
1109 *(inst)++ = (unsigned char)0xd9; \
1110 x86_mem_emit ((inst), 5, (mem)); \
1113 #define x86_fldcw_membase(inst,basereg,disp) \
1115 *(inst)++ = (unsigned char)0xd9; \
1116 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1119 #define x86_fchs(inst) \
1121 *(inst)++ = (unsigned char)0xd9; \
1122 *(inst)++ = (unsigned char)0xe0; \
1125 #define x86_frem(inst) \
1127 *(inst)++ = (unsigned char)0xd9; \
1128 *(inst)++ = (unsigned char)0xf8; \
1131 #define x86_fxch(inst,index) \
1133 *(inst)++ = (unsigned char)0xd9; \
1134 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1137 #define x86_fcomi(inst,index) \
1139 *(inst)++ = (unsigned char)0xdb; \
1140 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1143 #define x86_fcomip(inst,index) \
1145 *(inst)++ = (unsigned char)0xdf; \
1146 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1149 #define x86_fucomi(inst,index) \
1151 *(inst)++ = (unsigned char)0xdb; \
1152 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1155 #define x86_fucomip(inst,index) \
1157 *(inst)++ = (unsigned char)0xdf; \
1158 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1161 #define x86_fld(inst,mem,is_double) \
1163 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1164 x86_mem_emit ((inst), 0, (mem)); \
1167 #define x86_fld_membase(inst,basereg,disp,is_double) \
1169 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1170 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1173 #define x86_fld80_mem(inst,mem) \
1175 *(inst)++ = (unsigned char)0xdb; \
1176 x86_mem_emit ((inst), 5, (mem)); \
1179 #define x86_fld80_membase(inst,basereg,disp) \
1181 *(inst)++ = (unsigned char)0xdb; \
1182 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1185 #define x86_fild(inst,mem,is_long) \
1188 *(inst)++ = (unsigned char)0xdf; \
1189 x86_mem_emit ((inst), 5, (mem)); \
1191 *(inst)++ = (unsigned char)0xdb; \
1192 x86_mem_emit ((inst), 0, (mem)); \
1196 #define x86_fild_membase(inst,basereg,disp,is_long) \
1199 *(inst)++ = (unsigned char)0xdf; \
1200 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1202 *(inst)++ = (unsigned char)0xdb; \
1203 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1207 #define x86_fld_reg(inst,index) \
1209 *(inst)++ = (unsigned char)0xd9; \
1210 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1213 #define x86_fldz(inst) \
1215 *(inst)++ = (unsigned char)0xd9; \
1216 *(inst)++ = (unsigned char)0xee; \
1219 #define x86_fld1(inst) \
1221 *(inst)++ = (unsigned char)0xd9; \
1222 *(inst)++ = (unsigned char)0xe8; \
1225 #define x86_fldpi(inst) \
1227 *(inst)++ = (unsigned char)0xd9; \
1228 *(inst)++ = (unsigned char)0xeb; \
1231 #define x86_fst(inst,mem,is_double,pop_stack) \
1233 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1234 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1237 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1239 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1240 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1243 #define x86_fst80_mem(inst,mem) \
1245 *(inst)++ = (unsigned char)0xdb; \
1246 x86_mem_emit ((inst), 7, (mem)); \
1250 #define x86_fst80_membase(inst,basereg,disp) \
1252 *(inst)++ = (unsigned char)0xdb; \
1253 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1257 #define x86_fist_pop(inst,mem,is_long) \
1260 *(inst)++ = (unsigned char)0xdf; \
1261 x86_mem_emit ((inst), 7, (mem)); \
1263 *(inst)++ = (unsigned char)0xdb; \
1264 x86_mem_emit ((inst), 3, (mem)); \
1268 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1271 *(inst)++ = (unsigned char)0xdf; \
1272 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1274 *(inst)++ = (unsigned char)0xdb; \
1275 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1279 #define x86_fstsw(inst) \
1281 *(inst)++ = (unsigned char)0x9b; \
1282 *(inst)++ = (unsigned char)0xdf; \
1283 *(inst)++ = (unsigned char)0xe0; \
1288 * Converts content of ST(0) to integer and stores it at memory location
1289 * addressed by [basereg + disp].
1290 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1292 #define x86_fist_membase(inst,basereg,disp,is_int) \
1295 *(inst)++ = (unsigned char)0xdb; \
1296 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1298 *(inst)++ = (unsigned char)0xdf; \
1299 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1304 #define x86_push_reg(inst,reg) \
1306 *(inst)++ = (unsigned char)0x50 + (reg); \
1309 #define x86_push_regp(inst,reg) \
1311 *(inst)++ = (unsigned char)0xff; \
1312 x86_regp_emit ((inst), 6, (reg)); \
1315 #define x86_push_mem(inst,mem) \
1317 *(inst)++ = (unsigned char)0xff; \
1318 x86_mem_emit ((inst), 6, (mem)); \
1321 #define x86_push_membase(inst,basereg,disp) \
1323 *(inst)++ = (unsigned char)0xff; \
1324 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1327 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1329 *(inst)++ = (unsigned char)0xff; \
1330 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1333 #define x86_push_imm(inst,imm) \
1335 *(inst)++ = (unsigned char)0x68; \
1336 x86_imm_emit32 ((inst), (imm)); \
1339 #define x86_pop_reg(inst,reg) \
1341 *(inst)++ = (unsigned char)0x58 + (reg); \
1344 #define x86_pop_mem(inst,mem) \
1346 *(inst)++ = (unsigned char)0x87; \
1347 x86_mem_emit ((inst), 0, (mem)); \
1350 #define x86_pop_membase(inst,basereg,disp) \
1352 *(inst)++ = (unsigned char)0x87; \
1353 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1356 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1357 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1358 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1359 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1361 #define x86_loop(inst,imm) \
1363 *(inst)++ = (unsigned char)0xe2; \
1364 x86_imm_emit8 ((inst), (imm)); \
1367 #define x86_loope(inst,imm) \
1369 *(inst)++ = (unsigned char)0xe1; \
1370 x86_imm_emit8 ((inst), (imm)); \
1373 #define x86_loopne(inst,imm) \
1375 *(inst)++ = (unsigned char)0xe0; \
1376 x86_imm_emit8 ((inst), (imm)); \
1379 #define x86_jump32(inst,imm) \
1381 *(inst)++ = (unsigned char)0xe9; \
1382 x86_imm_emit32 ((inst), (imm)); \
1385 #define x86_jump8(inst,imm) \
1387 *(inst)++ = (unsigned char)0xeb; \
1388 x86_imm_emit8 ((inst), (imm)); \
1391 #define x86_jump_reg(inst,reg) \
1393 *(inst)++ = (unsigned char)0xff; \
1394 x86_reg_emit ((inst), 4, (reg)); \
1397 #define x86_jump_mem(inst,mem) \
1399 *(inst)++ = (unsigned char)0xff; \
1400 x86_mem_emit ((inst), 4, (mem)); \
1403 #define x86_jump_membase(inst,basereg,disp) \
1405 *(inst)++ = (unsigned char)0xff; \
1406 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1410 * target is a pointer in our buffer.
1412 #define x86_jump_code(inst,target) \
1414 int t = (unsigned char*)(target) - (inst) - 2; \
1415 if (x86_is_imm8(t)) { \
1416 x86_jump8 ((inst), t); \
1419 x86_jump32 ((inst), t); \
1423 #define x86_jump_disp(inst,disp) \
1425 int t = (disp) - 2; \
1426 if (x86_is_imm8(t)) { \
1427 x86_jump8 ((inst), t); \
1430 x86_jump32 ((inst), t); \
1434 #define x86_branch8(inst,cond,imm,is_signed) \
1437 *(inst)++ = x86_cc_signed_map [(cond)]; \
1439 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1440 x86_imm_emit8 ((inst), (imm)); \
1443 #define x86_branch32(inst,cond,imm,is_signed) \
1445 *(inst)++ = (unsigned char)0x0f; \
1447 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1449 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1450 x86_imm_emit32 ((inst), (imm)); \
1453 #define x86_branch(inst,cond,target,is_signed) \
1455 int offset = (target) - (inst) - 2; \
1456 if (x86_is_imm8 ((offset))) \
1457 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1460 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1464 #define x86_branch_disp(inst,cond,disp,is_signed) \
1466 int offset = (disp) - 2; \
1467 if (x86_is_imm8 ((offset))) \
1468 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1471 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1475 #define x86_set_reg(inst,cond,reg,is_signed) \
1477 g_assert (X86_IS_BYTE_REG (reg)); \
1478 *(inst)++ = (unsigned char)0x0f; \
1480 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1482 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1483 x86_reg_emit ((inst), 0, (reg)); \
1486 #define x86_set_mem(inst,cond,mem,is_signed) \
1488 *(inst)++ = (unsigned char)0x0f; \
1490 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1492 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1493 x86_mem_emit ((inst), 0, (mem)); \
1496 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
1498 *(inst)++ = (unsigned char)0x0f; \
1500 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1502 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1503 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1506 #define x86_call_imm(inst,disp) \
1508 *(inst)++ = (unsigned char)0xe8; \
1509 x86_imm_emit32 ((inst), (int)(disp)); \
1512 #define x86_call_reg(inst,reg) \
1514 *(inst)++ = (unsigned char)0xff; \
1515 x86_reg_emit ((inst), 2, (reg)); \
1518 #define x86_call_mem(inst,mem) \
1520 *(inst)++ = (unsigned char)0xff; \
1521 x86_mem_emit ((inst), 2, (mem)); \
1524 #define x86_call_membase(inst,basereg,disp) \
1526 *(inst)++ = (unsigned char)0xff; \
1527 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1530 #define x86_call_code(inst,target) \
1532 int _x86_offset = (unsigned char*)(target) - (inst); \
1534 x86_call_imm ((inst), _x86_offset); \
1537 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
1539 #define x86_ret_imm(inst,imm) \
1544 *(inst)++ = (unsigned char)0xc2; \
1545 x86_imm_emit16 ((inst), (imm)); \
1549 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
1551 *(inst)++ = (unsigned char) 0x0f; \
1553 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1555 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1556 x86_reg_emit ((inst), (dreg), (reg)); \
1559 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
1561 *(inst)++ = (unsigned char) 0x0f; \
1563 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1565 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1566 x86_mem_emit ((inst), (reg), (mem)); \
1569 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
1571 *(inst)++ = (unsigned char) 0x0f; \
1573 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1575 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1576 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1579 #define x86_enter(inst,framesize) \
1581 *(inst)++ = (unsigned char)0xc8; \
1582 x86_imm_emit16 ((inst), (framesize)); \
1586 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
1587 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
1589 #define x86_fsin(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
1590 #define x86_fcos(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
1591 #define x86_fabs(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
1592 #define x86_ftst(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
1593 #define x86_fxam(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
1594 #define x86_fpatan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
1595 #define x86_fprem(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
1596 #define x86_fprem1(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
1597 #define x86_frndint(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
1598 #define x86_fsqrt(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
1599 #define x86_fptan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
1601 #define x86_padding(inst,size) \
1604 case 1: x86_nop ((inst)); break; \
1605 case 2: *(inst)++ = 0x8b; \
1606 *(inst)++ = 0xc0; break; \
1607 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
1608 *(inst)++ = 0x00; break; \
1609 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1610 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1612 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1613 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1614 x86_nop ((inst)); break; \
1615 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
1616 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1617 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1619 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
1620 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1621 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1622 *(inst)++ = 0x00; break; \
1623 default: assert (0); \
1627 #define x86_prolog(inst,frame_size,reg_mask) \
1629 unsigned i, m = 1; \
1630 x86_enter ((inst), (frame_size)); \
1631 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
1632 if ((reg_mask) & m) \
1633 x86_push_reg ((inst), i); \
1637 #define x86_epilog(inst,reg_mask) \
1639 unsigned i, m = 1 << X86_EDI; \
1640 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
1641 if ((reg_mask) & m) \
1642 x86_pop_reg ((inst), i); \
1644 x86_leave ((inst)); \