2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 // x86 register numbers
46 // opcodes for alu instructions
60 // opcodes for shift instructions
75 // opcodes for floating-point instructions
89 // integer conditions codes
92 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
93 X86_CC_NE = 1, X86_CC_NZ = 1,
94 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
95 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
96 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
97 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
98 X86_CC_LZ = 6, X86_CC_S = 6,
99 X86_CC_GEZ = 7, X86_CC_NS = 7,
100 X86_CC_P = 8, X86_CC_PE = 8,
101 X86_CC_NP = 9, X86_CC_PO = 9,
113 X86_FP_CC_MASK = 0x4500
116 /* FP control word */
118 X86_FPCW_INVOPEX_MASK = 0x1,
119 X86_FPCW_DENOPEX_MASK = 0x2,
120 X86_FPCW_ZERODIV_MASK = 0x4,
121 X86_FPCW_OVFEX_MASK = 0x8,
122 X86_FPCW_UNDFEX_MASK = 0x10,
123 X86_FPCW_PRECEX_MASK = 0x20,
124 X86_FPCW_PRECC_MASK = 0x300,
125 X86_FPCW_ROUNDC_MASK = 0xc00,
127 /* values for precision control */
128 X86_FPCW_PREC_SINGLE = 0,
129 X86_FPCW_PREC_DOUBLE = 0x200,
130 X86_FPCW_PREC_EXTENDED = 0x300,
132 /* values for rounding control */
133 X86_FPCW_ROUND_NEAREST = 0,
134 X86_FPCW_ROUND_DOWN = 0x400,
135 X86_FPCW_ROUND_UP = 0x800,
136 X86_FPCW_ROUND_TOZERO = 0xc00
143 X86_LOCK_PREFIX = 0xF0,
144 X86_REPNZ_PREFIX = 0xF2,
145 X86_REPZ_PREFIX = 0xF3,
146 X86_REP_PREFIX = 0xF3,
147 X86_CS_PREFIX = 0x2E,
148 X86_SS_PREFIX = 0x36,
149 X86_DS_PREFIX = 0x3E,
150 X86_ES_PREFIX = 0x26,
151 X86_FS_PREFIX = 0x64,
152 X86_GS_PREFIX = 0x65,
153 X86_UNLIKELY_PREFIX = 0x2E,
154 X86_LIKELY_PREFIX = 0x3E,
155 X86_OPERAND_PREFIX = 0x66,
156 X86_ADDRESS_PREFIX = 0x67
159 static const unsigned char
160 x86_cc_unsigned_map [X86_NCC] = {
175 static const unsigned char
176 x86_cc_signed_map [X86_NCC] = {
196 #define X86_NOBASEREG (-1)
199 // bitvector mask for callee-saved registers
201 #define X86_ESI_MASK (1<<X86_ESI)
202 #define X86_EDI_MASK (1<<X86_EDI)
203 #define X86_EBX_MASK (1<<X86_EBX)
204 #define X86_EBP_MASK (1<<X86_EBP)
206 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
207 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
208 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
210 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
211 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
213 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
218 // +--------------------------------+
219 // | in_arg[0] = var[0] |
220 // | in_arg[1] = var[1] |
222 // | in_arg[n_arg-1] = var[n_arg-1] |
223 // +--------------------------------+
225 // +--------------------------------+
226 // | saved EBP | <-- frame pointer (EBP)
227 // +--------------------------------+
229 // +--------------------------------+
231 // | var[n_arg+1] | local variables area
234 // +--------------------------------+
237 // | spill area | area for spilling mimic stack
239 // +--------------------------------|
241 // | ebp [ESP_Frame only] |
242 // | esi | 0..3 callee-saved regs
243 // | edi | <-- stack pointer (ESP)
244 // +--------------------------------+
246 // | stk1 | operand stack area/
247 // | . . . | out args
249 // +--------------------------------|
256 * useful building blocks
258 #define x86_modrm_mod(modrm) ((modrm) >> 6)
259 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
260 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
262 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
263 #define x86_imm_emit32(inst,imm) \
265 x86_imm_buf imb; imb.val = (int) (imm); \
266 *(inst)++ = imb.b [0]; \
267 *(inst)++ = imb.b [1]; \
268 *(inst)++ = imb.b [2]; \
269 *(inst)++ = imb.b [3]; \
271 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
272 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
273 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
274 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
276 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
277 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
278 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
279 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
281 #define x86_membase_emit(inst,r,basereg,disp) do {\
282 if ((basereg) == X86_ESP) { \
284 x86_address_byte ((inst), 0, (r), X86_ESP); \
285 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
286 } else if (x86_is_imm8((disp))) { \
287 x86_address_byte ((inst), 1, (r), X86_ESP); \
288 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
289 x86_imm_emit8 ((inst), (disp)); \
291 x86_address_byte ((inst), 2, (r), X86_ESP); \
292 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
293 x86_imm_emit32 ((inst), (disp)); \
297 if ((disp) == 0 && (basereg) != X86_EBP) { \
298 x86_address_byte ((inst), 0, (r), (basereg)); \
301 if (x86_is_imm8((disp))) { \
302 x86_address_byte ((inst), 1, (r), (basereg)); \
303 x86_imm_emit8 ((inst), (disp)); \
305 x86_address_byte ((inst), 2, (r), (basereg)); \
306 x86_imm_emit32 ((inst), (disp)); \
310 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
312 if ((basereg) == X86_NOBASEREG) { \
313 x86_address_byte ((inst), 0, (r), 4); \
314 x86_address_byte ((inst), (shift), (indexreg), 5); \
315 x86_imm_emit32 ((inst), (disp)); \
316 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
317 x86_address_byte ((inst), 0, (r), 4); \
318 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
319 } else if (x86_is_imm8((disp))) { \
320 x86_address_byte ((inst), 1, (r), 4); \
321 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
322 x86_imm_emit8 ((inst), (disp)); \
324 x86_address_byte ((inst), 2, (r), 4); \
325 x86_address_byte ((inst), (shift), (indexreg), 5); \
326 x86_imm_emit32 ((inst), (disp)); \
331 * target is the position in the code where to jump to:
333 * .. output loop code...
334 * x86_mov_reg_imm (code, X86_EAX, 0);
336 * x86_loop (code, -1);
340 * x86_patch (loop, target);
342 * ins should point at the start of the instruction that encodes a target.
343 * the instruction is inspected for validity and the correct displacement
346 #define x86_patch(ins,target) \
348 unsigned char* pos = (ins) + 1; \
349 int disp, size = 0; \
350 switch (*(unsigned char*)(ins)) { \
351 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
352 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
353 ++size; ++pos; break; /* prefix for 32-bit disp */ \
354 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
355 case 0xeb: /* jump8 */ \
356 /* conditional jump opcodes */ \
357 case 0x70: case 0x71: case 0x72: case 0x73: \
358 case 0x74: case 0x75: case 0x76: case 0x77: \
359 case 0x78: case 0x79: case 0x7a: case 0x7b: \
360 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
362 default: assert (0); \
364 disp = (target) - pos; \
365 if (size) x86_imm_emit32 (pos, disp - 4); \
366 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
370 #define x86_breakpoint(inst) \
375 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
376 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
377 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
378 #define x86_stosd(inst) x86_stosl((inst))
379 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
380 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
381 #define x86_movsd(inst) x86_movsl((inst))
383 #define x86_prefix(inst,p) do { *(inst)++ =(unsigned char) (p); } while (0)
385 #define x86_rdtsc(inst) \
391 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
393 *(inst)++ = (unsigned char)0x0f; \
394 *(inst)++ = (unsigned char)0xb1; \
395 x86_reg_emit ((inst), (reg), (dreg)); \
398 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
400 *(inst)++ = (unsigned char)0x0f; \
401 *(inst)++ = (unsigned char)0xb1; \
402 x86_mem_emit ((inst), (reg), (mem)); \
405 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
407 *(inst)++ = (unsigned char)0x0f; \
408 *(inst)++ = (unsigned char)0xb1; \
409 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
412 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
415 *(inst)++ = (unsigned char)0x86; \
417 *(inst)++ = (unsigned char)0x87; \
418 x86_reg_emit ((inst), (reg), (dreg)); \
421 #define x86_xchg_mem_reg(inst,mem,reg,size) \
424 *(inst)++ = (unsigned char)0x86; \
426 *(inst)++ = (unsigned char)0x87; \
427 x86_mem_emit ((inst), (reg), (mem)); \
430 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
433 *(inst)++ = (unsigned char)0x86; \
435 *(inst)++ = (unsigned char)0x87; \
436 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
439 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
441 *(inst)++ = (unsigned char)0x0F; \
443 *(inst)++ = (unsigned char)0xC0; \
445 *(inst)++ = (unsigned char)0xC1; \
446 x86_reg_emit ((inst), (reg), (dreg)); \
449 #define x86_xadd_mem_reg(inst,mem,reg,size) \
451 *(inst)++ = (unsigned char)0x0F; \
453 *(inst)++ = (unsigned char)0xC0; \
455 *(inst)++ = (unsigned char)0xC1; \
456 x86_mem_emit ((inst), (reg), (mem)); \
459 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
461 *(inst)++ = (unsigned char)0x0F; \
463 *(inst)++ = (unsigned char)0xC0; \
465 *(inst)++ = (unsigned char)0xC1; \
466 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
469 #define x86_inc_mem(inst,mem) \
471 *(inst)++ = (unsigned char)0xff; \
472 x86_mem_emit ((inst), 0, (mem)); \
475 #define x86_inc_membase(inst,basereg,disp) \
477 *(inst)++ = (unsigned char)0xff; \
478 x86_membase_emit ((inst), 0, (basereg), (disp)); \
481 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
483 #define x86_dec_mem(inst,mem) \
485 *(inst)++ = (unsigned char)0xff; \
486 x86_mem_emit ((inst), 1, (mem)); \
489 #define x86_dec_membase(inst,basereg,disp) \
491 *(inst)++ = (unsigned char)0xff; \
492 x86_membase_emit ((inst), 1, (basereg), (disp)); \
495 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
497 #define x86_not_mem(inst,mem) \
499 *(inst)++ = (unsigned char)0xf7; \
500 x86_mem_emit ((inst), 2, (mem)); \
503 #define x86_not_membase(inst,basereg,disp) \
505 *(inst)++ = (unsigned char)0xf7; \
506 x86_membase_emit ((inst), 2, (basereg), (disp)); \
509 #define x86_not_reg(inst,reg) \
511 *(inst)++ = (unsigned char)0xf7; \
512 x86_reg_emit ((inst), 2, (reg)); \
515 #define x86_neg_mem(inst,mem) \
517 *(inst)++ = (unsigned char)0xf7; \
518 x86_mem_emit ((inst), 3, (mem)); \
521 #define x86_neg_membase(inst,basereg,disp) \
523 *(inst)++ = (unsigned char)0xf7; \
524 x86_membase_emit ((inst), 3, (basereg), (disp)); \
527 #define x86_neg_reg(inst,reg) \
529 *(inst)++ = (unsigned char)0xf7; \
530 x86_reg_emit ((inst), 3, (reg)); \
533 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
535 #define x86_alu_reg_imm(inst,opc,reg,imm) \
537 if ((reg) == X86_EAX) { \
538 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
539 x86_imm_emit32 ((inst), (imm)); \
542 if (x86_is_imm8((imm))) { \
543 *(inst)++ = (unsigned char)0x83; \
544 x86_reg_emit ((inst), (opc), (reg)); \
545 x86_imm_emit8 ((inst), (imm)); \
547 *(inst)++ = (unsigned char)0x81; \
548 x86_reg_emit ((inst), (opc), (reg)); \
549 x86_imm_emit32 ((inst), (imm)); \
553 #define x86_alu_mem_imm(inst,opc,mem,imm) \
555 if (x86_is_imm8((imm))) { \
556 *(inst)++ = (unsigned char)0x83; \
557 x86_mem_emit ((inst), (opc), (mem)); \
558 x86_imm_emit8 ((inst), (imm)); \
560 *(inst)++ = (unsigned char)0x81; \
561 x86_mem_emit ((inst), (opc), (mem)); \
562 x86_imm_emit32 ((inst), (imm)); \
566 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
568 if (x86_is_imm8((imm))) { \
569 *(inst)++ = (unsigned char)0x83; \
570 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
571 x86_imm_emit8 ((inst), (imm)); \
573 *(inst)++ = (unsigned char)0x81; \
574 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
575 x86_imm_emit32 ((inst), (imm)); \
579 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
581 *(inst)++ = (unsigned char)0x80; \
582 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
583 x86_imm_emit8 ((inst), (imm)); \
586 #define x86_alu_mem_reg(inst,opc,mem,reg) \
588 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
589 x86_mem_emit ((inst), (reg), (mem)); \
592 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
594 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
595 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
598 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
600 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
601 x86_reg_emit ((inst), (dreg), (reg)); \
605 * @x86_alu_reg8_reg8:
606 * Supports ALU operations between two 8-bit registers.
607 * dreg := dreg opc reg
608 * X86_Reg_No enum is used to specify the registers.
609 * Additionally is_*_h flags are used to specify what part
610 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
611 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
613 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
615 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
616 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
619 #define x86_alu_reg_mem(inst,opc,reg,mem) \
621 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
622 x86_mem_emit ((inst), (reg), (mem)); \
625 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
627 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
628 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
631 #define x86_test_reg_imm(inst,reg,imm) \
633 if ((reg) == X86_EAX) { \
634 *(inst)++ = (unsigned char)0xa9; \
636 *(inst)++ = (unsigned char)0xf7; \
637 x86_reg_emit ((inst), 0, (reg)); \
639 x86_imm_emit32 ((inst), (imm)); \
642 #define x86_test_mem_imm(inst,mem,imm) \
644 *(inst)++ = (unsigned char)0xf7; \
645 x86_mem_emit ((inst), 0, (mem)); \
646 x86_imm_emit32 ((inst), (imm)); \
649 #define x86_test_membase_imm(inst,basereg,disp,imm) \
651 *(inst)++ = (unsigned char)0xf7; \
652 x86_membase_emit ((inst), 0, (basereg), (disp)); \
653 x86_imm_emit32 ((inst), (imm)); \
656 #define x86_test_reg_reg(inst,dreg,reg) \
658 *(inst)++ = (unsigned char)0x85; \
659 x86_reg_emit ((inst), (reg), (dreg)); \
662 #define x86_test_mem_reg(inst,mem,reg) \
664 *(inst)++ = (unsigned char)0x85; \
665 x86_mem_emit ((inst), (reg), (mem)); \
668 #define x86_test_membase_reg(inst,basereg,disp,reg) \
670 *(inst)++ = (unsigned char)0x85; \
671 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
674 #define x86_shift_reg_imm(inst,opc,reg,imm) \
677 *(inst)++ = (unsigned char)0xd1; \
678 x86_reg_emit ((inst), (opc), (reg)); \
680 *(inst)++ = (unsigned char)0xc1; \
681 x86_reg_emit ((inst), (opc), (reg)); \
682 x86_imm_emit8 ((inst), (imm)); \
686 #define x86_shift_mem_imm(inst,opc,mem,imm) \
689 *(inst)++ = (unsigned char)0xd1; \
690 x86_mem_emit ((inst), (opc), (mem)); \
692 *(inst)++ = (unsigned char)0xc1; \
693 x86_mem_emit ((inst), (opc), (mem)); \
694 x86_imm_emit8 ((inst), (imm)); \
698 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
701 *(inst)++ = (unsigned char)0xd1; \
702 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
704 *(inst)++ = (unsigned char)0xc1; \
705 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
706 x86_imm_emit8 ((inst), (imm)); \
710 #define x86_shift_reg(inst,opc,reg) \
712 *(inst)++ = (unsigned char)0xd3; \
713 x86_reg_emit ((inst), (opc), (reg)); \
716 #define x86_shift_mem(inst,opc,mem) \
718 *(inst)++ = (unsigned char)0xd3; \
719 x86_mem_emit ((inst), (opc), (mem)); \
722 #define x86_shift_membase(inst,opc,basereg,disp) \
724 *(inst)++ = (unsigned char)0xd3; \
725 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
729 * Multi op shift missing.
732 #define x86_shrd_reg(inst,dreg,reg) \
734 *(inst)++ = (unsigned char)0x0f; \
735 *(inst)++ = (unsigned char)0xad; \
736 x86_reg_emit ((inst), (reg), (dreg)); \
739 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
741 *(inst)++ = (unsigned char)0x0f; \
742 *(inst)++ = (unsigned char)0xac; \
743 x86_reg_emit ((inst), (reg), (dreg)); \
744 x86_imm_emit8 ((inst), (shamt)); \
747 #define x86_shld_reg(inst,dreg,reg) \
749 *(inst)++ = (unsigned char)0x0f; \
750 *(inst)++ = (unsigned char)0xa5; \
751 x86_reg_emit ((inst), (reg), (dreg)); \
754 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
756 *(inst)++ = (unsigned char)0x0f; \
757 *(inst)++ = (unsigned char)0xa4; \
758 x86_reg_emit ((inst), (reg), (dreg)); \
759 x86_imm_emit8 ((inst), (shamt)); \
765 #define x86_mul_reg(inst,reg,is_signed) \
767 *(inst)++ = (unsigned char)0xf7; \
768 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
771 #define x86_mul_mem(inst,mem,is_signed) \
773 *(inst)++ = (unsigned char)0xf7; \
774 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
777 #define x86_mul_membase(inst,basereg,disp,is_signed) \
779 *(inst)++ = (unsigned char)0xf7; \
780 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
786 #define x86_imul_reg_reg(inst,dreg,reg) \
788 *(inst)++ = (unsigned char)0x0f; \
789 *(inst)++ = (unsigned char)0xaf; \
790 x86_reg_emit ((inst), (dreg), (reg)); \
793 #define x86_imul_reg_mem(inst,reg,mem) \
795 *(inst)++ = (unsigned char)0x0f; \
796 *(inst)++ = (unsigned char)0xaf; \
797 x86_mem_emit ((inst), (reg), (mem)); \
800 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
802 *(inst)++ = (unsigned char)0x0f; \
803 *(inst)++ = (unsigned char)0xaf; \
804 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
810 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
812 if (x86_is_imm8 ((imm))) { \
813 *(inst)++ = (unsigned char)0x6b; \
814 x86_reg_emit ((inst), (dreg), (reg)); \
815 x86_imm_emit8 ((inst), (imm)); \
817 *(inst)++ = (unsigned char)0x69; \
818 x86_reg_emit ((inst), (dreg), (reg)); \
819 x86_imm_emit32 ((inst), (imm)); \
823 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
825 if (x86_is_imm8 ((imm))) { \
826 *(inst)++ = (unsigned char)0x6b; \
827 x86_mem_emit ((inst), (reg), (mem)); \
828 x86_imm_emit8 ((inst), (imm)); \
830 *(inst)++ = (unsigned char)0x69; \
831 x86_reg_emit ((inst), (reg), (mem)); \
832 x86_imm_emit32 ((inst), (imm)); \
836 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
838 if (x86_is_imm8 ((imm))) { \
839 *(inst)++ = (unsigned char)0x6b; \
840 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
841 x86_imm_emit8 ((inst), (imm)); \
843 *(inst)++ = (unsigned char)0x69; \
844 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
845 x86_imm_emit32 ((inst), (imm)); \
850 * divide EDX:EAX by rm;
851 * eax = quotient, edx = remainder
854 #define x86_div_reg(inst,reg,is_signed) \
856 *(inst)++ = (unsigned char)0xf7; \
857 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
860 #define x86_div_mem(inst,mem,is_signed) \
862 *(inst)++ = (unsigned char)0xf7; \
863 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
866 #define x86_div_membase(inst,basereg,disp,is_signed) \
868 *(inst)++ = (unsigned char)0xf7; \
869 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
872 #define x86_mov_mem_reg(inst,mem,reg,size) \
875 case 1: *(inst)++ = (unsigned char)0x88; break; \
876 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
877 case 4: *(inst)++ = (unsigned char)0x89; break; \
878 default: assert (0); \
880 x86_mem_emit ((inst), (reg), (mem)); \
883 #define x86_mov_regp_reg(inst,regp,reg,size) \
886 case 1: *(inst)++ = (unsigned char)0x88; break; \
887 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
888 case 4: *(inst)++ = (unsigned char)0x89; break; \
889 default: assert (0); \
891 x86_regp_emit ((inst), (reg), (regp)); \
894 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
897 case 1: *(inst)++ = (unsigned char)0x88; break; \
898 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
899 case 4: *(inst)++ = (unsigned char)0x89; break; \
900 default: assert (0); \
902 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
905 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
908 case 1: *(inst)++ = (unsigned char)0x88; break; \
909 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
910 case 4: *(inst)++ = (unsigned char)0x89; break; \
911 default: assert (0); \
913 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
916 #define x86_mov_reg_reg(inst,dreg,reg,size) \
919 case 1: *(inst)++ = (unsigned char)0x8a; break; \
920 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
921 case 4: *(inst)++ = (unsigned char)0x8b; break; \
922 default: assert (0); \
924 x86_reg_emit ((inst), (dreg), (reg)); \
927 #define x86_mov_reg_mem(inst,reg,mem,size) \
930 case 1: *(inst)++ = (unsigned char)0x8a; break; \
931 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
932 case 4: *(inst)++ = (unsigned char)0x8b; break; \
933 default: assert (0); \
935 x86_mem_emit ((inst), (reg), (mem)); \
938 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
941 case 1: *(inst)++ = (unsigned char)0x8a; break; \
942 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
943 case 4: *(inst)++ = (unsigned char)0x8b; break; \
944 default: assert (0); \
946 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
949 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
952 case 1: *(inst)++ = (unsigned char)0x8a; break; \
953 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
954 case 4: *(inst)++ = (unsigned char)0x8b; break; \
955 default: assert (0); \
957 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
961 * Note: x86_clear_reg () chacnges the condition code!
963 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
965 #define x86_mov_reg_imm(inst,reg,imm) \
967 *(inst)++ = (unsigned char)0xb8 + (reg); \
968 x86_imm_emit32 ((inst), (imm)); \
971 #define x86_mov_mem_imm(inst,mem,imm,size) \
974 *(inst)++ = (unsigned char)0xc6; \
975 x86_mem_emit ((inst), 0, (mem)); \
976 x86_imm_emit8 ((inst), (imm)); \
977 } else if ((size) == 2) { \
978 *(inst)++ = (unsigned char)0x66; \
979 *(inst)++ = (unsigned char)0xc7; \
980 x86_mem_emit ((inst), 0, (mem)); \
981 x86_imm_emit16 ((inst), (imm)); \
983 *(inst)++ = (unsigned char)0xc7; \
984 x86_mem_emit ((inst), 0, (mem)); \
985 x86_imm_emit32 ((inst), (imm)); \
989 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
992 *(inst)++ = (unsigned char)0xc6; \
993 x86_membase_emit ((inst), 0, (basereg), (disp)); \
994 x86_imm_emit8 ((inst), (imm)); \
995 } else if ((size) == 2) { \
996 *(inst)++ = (unsigned char)0x66; \
997 *(inst)++ = (unsigned char)0xc7; \
998 x86_membase_emit ((inst), 0, (basereg), (disp)); \
999 x86_imm_emit16 ((inst), (imm)); \
1001 *(inst)++ = (unsigned char)0xc7; \
1002 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1003 x86_imm_emit32 ((inst), (imm)); \
1007 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1009 if ((size) == 1) { \
1010 *(inst)++ = (unsigned char)0xc6; \
1011 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1012 x86_imm_emit8 ((inst), (imm)); \
1013 } else if ((size) == 2) { \
1014 *(inst)++ = (unsigned char)0x66; \
1015 *(inst)++ = (unsigned char)0xc7; \
1016 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1017 x86_imm_emit16 ((inst), (imm)); \
1019 *(inst)++ = (unsigned char)0xc7; \
1020 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1021 x86_imm_emit32 ((inst), (imm)); \
1025 #define x86_lea_mem(inst,reg,mem) \
1027 *(inst)++ = (unsigned char)0x8d; \
1028 x86_mem_emit ((inst), (reg), (mem)); \
1031 #define x86_lea_membase(inst,reg,basereg,disp) \
1033 *(inst)++ = (unsigned char)0x8d; \
1034 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1037 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1039 *(inst)++ = (unsigned char)0x8d; \
1040 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1043 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1045 unsigned char op = 0xb6; \
1046 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1047 *(inst)++ = (unsigned char)0x0f; \
1048 if ((is_signed)) op += 0x08; \
1049 if ((is_half)) op += 0x01; \
1051 x86_reg_emit ((inst), (dreg), (reg)); \
1054 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1056 unsigned char op = 0xb6; \
1057 *(inst)++ = (unsigned char)0x0f; \
1058 if ((is_signed)) op += 0x08; \
1059 if ((is_half)) op += 0x01; \
1061 x86_mem_emit ((inst), (dreg), (mem)); \
1064 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1066 unsigned char op = 0xb6; \
1067 *(inst)++ = (unsigned char)0x0f; \
1068 if ((is_signed)) op += 0x08; \
1069 if ((is_half)) op += 0x01; \
1071 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1074 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1076 unsigned char op = 0xb6; \
1077 *(inst)++ = (unsigned char)0x0f; \
1078 if ((is_signed)) op += 0x08; \
1079 if ((is_half)) op += 0x01; \
1081 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1084 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1085 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1087 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1089 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1090 x86_mem_emit ((inst), (opc), (mem)); \
1093 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1095 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1096 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1099 #define x86_fp_op(inst,opc,index) \
1101 *(inst)++ = (unsigned char)0xd8; \
1102 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1105 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1107 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1108 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1109 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1113 * @x86_fp_int_op_membase
1114 * Supports FPU operations between ST(0) and integer operand in memory.
1115 * Operation encoded using X86_FP_Opcode enum.
1116 * Operand is addressed by [basereg + disp].
1117 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1119 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1121 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1122 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1125 #define x86_fstp(inst,index) \
1127 *(inst)++ = (unsigned char)0xdd; \
1128 *(inst)++ = (unsigned char)0xd8+(index); \
1131 #define x86_fcompp(inst) \
1133 *(inst)++ = (unsigned char)0xde; \
1134 *(inst)++ = (unsigned char)0xd9; \
1137 #define x86_fucompp(inst) \
1139 *(inst)++ = (unsigned char)0xda; \
1140 *(inst)++ = (unsigned char)0xe9; \
1143 #define x86_fnstsw(inst) \
1145 *(inst)++ = (unsigned char)0xdf; \
1146 *(inst)++ = (unsigned char)0xe0; \
1149 #define x86_fnstcw(inst,mem) \
1151 *(inst)++ = (unsigned char)0xd9; \
1152 x86_mem_emit ((inst), 7, (mem)); \
1155 #define x86_fnstcw_membase(inst,basereg,disp) \
1157 *(inst)++ = (unsigned char)0xd9; \
1158 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1161 #define x86_fldcw(inst,mem) \
1163 *(inst)++ = (unsigned char)0xd9; \
1164 x86_mem_emit ((inst), 5, (mem)); \
1167 #define x86_fldcw_membase(inst,basereg,disp) \
1169 *(inst)++ = (unsigned char)0xd9; \
1170 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1173 #define x86_fchs(inst) \
1175 *(inst)++ = (unsigned char)0xd9; \
1176 *(inst)++ = (unsigned char)0xe0; \
1179 #define x86_frem(inst) \
1181 *(inst)++ = (unsigned char)0xd9; \
1182 *(inst)++ = (unsigned char)0xf8; \
1185 #define x86_fxch(inst,index) \
1187 *(inst)++ = (unsigned char)0xd9; \
1188 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1191 #define x86_fcomi(inst,index) \
1193 *(inst)++ = (unsigned char)0xdb; \
1194 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1197 #define x86_fcomip(inst,index) \
1199 *(inst)++ = (unsigned char)0xdf; \
1200 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1203 #define x86_fucomi(inst,index) \
1205 *(inst)++ = (unsigned char)0xdb; \
1206 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1209 #define x86_fucomip(inst,index) \
1211 *(inst)++ = (unsigned char)0xdf; \
1212 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1215 #define x86_fld(inst,mem,is_double) \
1217 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1218 x86_mem_emit ((inst), 0, (mem)); \
1221 #define x86_fld_membase(inst,basereg,disp,is_double) \
1223 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1224 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1227 #define x86_fld80_mem(inst,mem) \
1229 *(inst)++ = (unsigned char)0xdb; \
1230 x86_mem_emit ((inst), 5, (mem)); \
1233 #define x86_fld80_membase(inst,basereg,disp) \
1235 *(inst)++ = (unsigned char)0xdb; \
1236 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1239 #define x86_fild(inst,mem,is_long) \
1242 *(inst)++ = (unsigned char)0xdf; \
1243 x86_mem_emit ((inst), 5, (mem)); \
1245 *(inst)++ = (unsigned char)0xdb; \
1246 x86_mem_emit ((inst), 0, (mem)); \
1250 #define x86_fild_membase(inst,basereg,disp,is_long) \
1253 *(inst)++ = (unsigned char)0xdf; \
1254 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1256 *(inst)++ = (unsigned char)0xdb; \
1257 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1261 #define x86_fld_reg(inst,index) \
1263 *(inst)++ = (unsigned char)0xd9; \
1264 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1267 #define x86_fldz(inst) \
1269 *(inst)++ = (unsigned char)0xd9; \
1270 *(inst)++ = (unsigned char)0xee; \
1273 #define x86_fld1(inst) \
1275 *(inst)++ = (unsigned char)0xd9; \
1276 *(inst)++ = (unsigned char)0xe8; \
1279 #define x86_fldpi(inst) \
1281 *(inst)++ = (unsigned char)0xd9; \
1282 *(inst)++ = (unsigned char)0xeb; \
1285 #define x86_fst(inst,mem,is_double,pop_stack) \
1287 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1288 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1291 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1293 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1294 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1297 #define x86_fst80_mem(inst,mem) \
1299 *(inst)++ = (unsigned char)0xdb; \
1300 x86_mem_emit ((inst), 7, (mem)); \
1304 #define x86_fst80_membase(inst,basereg,disp) \
1306 *(inst)++ = (unsigned char)0xdb; \
1307 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1311 #define x86_fist_pop(inst,mem,is_long) \
1314 *(inst)++ = (unsigned char)0xdf; \
1315 x86_mem_emit ((inst), 7, (mem)); \
1317 *(inst)++ = (unsigned char)0xdb; \
1318 x86_mem_emit ((inst), 3, (mem)); \
1322 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1325 *(inst)++ = (unsigned char)0xdf; \
1326 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1328 *(inst)++ = (unsigned char)0xdb; \
1329 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1333 #define x86_fstsw(inst) \
1335 *(inst)++ = (unsigned char)0x9b; \
1336 *(inst)++ = (unsigned char)0xdf; \
1337 *(inst)++ = (unsigned char)0xe0; \
1342 * Converts content of ST(0) to integer and stores it at memory location
1343 * addressed by [basereg + disp].
1344 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1346 #define x86_fist_membase(inst,basereg,disp,is_int) \
1349 *(inst)++ = (unsigned char)0xdb; \
1350 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1352 *(inst)++ = (unsigned char)0xdf; \
1353 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1358 #define x86_push_reg(inst,reg) \
1360 *(inst)++ = (unsigned char)0x50 + (reg); \
1363 #define x86_push_regp(inst,reg) \
1365 *(inst)++ = (unsigned char)0xff; \
1366 x86_regp_emit ((inst), 6, (reg)); \
1369 #define x86_push_mem(inst,mem) \
1371 *(inst)++ = (unsigned char)0xff; \
1372 x86_mem_emit ((inst), 6, (mem)); \
1375 #define x86_push_membase(inst,basereg,disp) \
1377 *(inst)++ = (unsigned char)0xff; \
1378 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1381 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1383 *(inst)++ = (unsigned char)0xff; \
1384 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1387 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1389 #define x86_push_imm(inst,imm) \
1391 int _imm = (int) (imm); \
1392 if (x86_is_imm8 (_imm)) { \
1393 *(inst)++ = (unsigned char)0x6A; \
1394 x86_imm_emit8 ((inst), (_imm)); \
1396 *(inst)++ = (unsigned char)0x68; \
1397 x86_imm_emit32 ((inst), (_imm)); \
1401 #define x86_pop_reg(inst,reg) \
1403 *(inst)++ = (unsigned char)0x58 + (reg); \
1406 #define x86_pop_mem(inst,mem) \
1408 *(inst)++ = (unsigned char)0x87; \
1409 x86_mem_emit ((inst), 0, (mem)); \
1412 #define x86_pop_membase(inst,basereg,disp) \
1414 *(inst)++ = (unsigned char)0x87; \
1415 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1418 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1419 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1420 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1421 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1423 #define x86_loop(inst,imm) \
1425 *(inst)++ = (unsigned char)0xe2; \
1426 x86_imm_emit8 ((inst), (imm)); \
1429 #define x86_loope(inst,imm) \
1431 *(inst)++ = (unsigned char)0xe1; \
1432 x86_imm_emit8 ((inst), (imm)); \
1435 #define x86_loopne(inst,imm) \
1437 *(inst)++ = (unsigned char)0xe0; \
1438 x86_imm_emit8 ((inst), (imm)); \
1441 #define x86_jump32(inst,imm) \
1443 *(inst)++ = (unsigned char)0xe9; \
1444 x86_imm_emit32 ((inst), (imm)); \
1447 #define x86_jump8(inst,imm) \
1449 *(inst)++ = (unsigned char)0xeb; \
1450 x86_imm_emit8 ((inst), (imm)); \
1453 #define x86_jump_reg(inst,reg) \
1455 *(inst)++ = (unsigned char)0xff; \
1456 x86_reg_emit ((inst), 4, (reg)); \
1459 #define x86_jump_mem(inst,mem) \
1461 *(inst)++ = (unsigned char)0xff; \
1462 x86_mem_emit ((inst), 4, (mem)); \
1465 #define x86_jump_membase(inst,basereg,disp) \
1467 *(inst)++ = (unsigned char)0xff; \
1468 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1472 * target is a pointer in our buffer.
1474 #define x86_jump_code(inst,target) \
1476 int t = (unsigned char*)(target) - (inst) - 2; \
1477 if (x86_is_imm8(t)) { \
1478 x86_jump8 ((inst), t); \
1481 x86_jump32 ((inst), t); \
1485 #define x86_jump_disp(inst,disp) \
1487 int t = (disp) - 2; \
1488 if (x86_is_imm8(t)) { \
1489 x86_jump8 ((inst), t); \
1492 x86_jump32 ((inst), t); \
1496 #define x86_branch8(inst,cond,imm,is_signed) \
1499 *(inst)++ = x86_cc_signed_map [(cond)]; \
1501 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1502 x86_imm_emit8 ((inst), (imm)); \
1505 #define x86_branch32(inst,cond,imm,is_signed) \
1507 *(inst)++ = (unsigned char)0x0f; \
1509 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1511 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1512 x86_imm_emit32 ((inst), (imm)); \
1515 #define x86_branch(inst,cond,target,is_signed) \
1517 int offset = (target) - (inst) - 2; \
1518 if (x86_is_imm8 ((offset))) \
1519 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1522 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1526 #define x86_branch_disp(inst,cond,disp,is_signed) \
1528 int offset = (disp) - 2; \
1529 if (x86_is_imm8 ((offset))) \
1530 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1533 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1537 #define x86_set_reg(inst,cond,reg,is_signed) \
1539 g_assert (X86_IS_BYTE_REG (reg)); \
1540 *(inst)++ = (unsigned char)0x0f; \
1542 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1544 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1545 x86_reg_emit ((inst), 0, (reg)); \
1548 #define x86_set_mem(inst,cond,mem,is_signed) \
1550 *(inst)++ = (unsigned char)0x0f; \
1552 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1554 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1555 x86_mem_emit ((inst), 0, (mem)); \
1558 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
1560 *(inst)++ = (unsigned char)0x0f; \
1562 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1564 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1565 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1568 #define x86_call_imm(inst,disp) \
1570 *(inst)++ = (unsigned char)0xe8; \
1571 x86_imm_emit32 ((inst), (int)(disp)); \
1574 #define x86_call_reg(inst,reg) \
1576 *(inst)++ = (unsigned char)0xff; \
1577 x86_reg_emit ((inst), 2, (reg)); \
1580 #define x86_call_mem(inst,mem) \
1582 *(inst)++ = (unsigned char)0xff; \
1583 x86_mem_emit ((inst), 2, (mem)); \
1586 #define x86_call_membase(inst,basereg,disp) \
1588 *(inst)++ = (unsigned char)0xff; \
1589 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1592 #define x86_call_code(inst,target) \
1594 int _x86_offset = (unsigned char*)(target) - (inst); \
1596 x86_call_imm ((inst), _x86_offset); \
1599 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
1601 #define x86_ret_imm(inst,imm) \
1606 *(inst)++ = (unsigned char)0xc2; \
1607 x86_imm_emit16 ((inst), (imm)); \
1611 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
1613 *(inst)++ = (unsigned char) 0x0f; \
1615 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1617 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1618 x86_reg_emit ((inst), (dreg), (reg)); \
1621 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
1623 *(inst)++ = (unsigned char) 0x0f; \
1625 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1627 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1628 x86_mem_emit ((inst), (reg), (mem)); \
1631 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
1633 *(inst)++ = (unsigned char) 0x0f; \
1635 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1637 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1638 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1641 #define x86_enter(inst,framesize) \
1643 *(inst)++ = (unsigned char)0xc8; \
1644 x86_imm_emit16 ((inst), (framesize)); \
1648 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
1649 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
1651 #define x86_fsin(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
1652 #define x86_fcos(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
1653 #define x86_fabs(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
1654 #define x86_ftst(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
1655 #define x86_fxam(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
1656 #define x86_fpatan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
1657 #define x86_fprem(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
1658 #define x86_fprem1(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
1659 #define x86_frndint(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
1660 #define x86_fsqrt(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
1661 #define x86_fptan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
1663 #define x86_padding(inst,size) \
1666 case 1: x86_nop ((inst)); break; \
1667 case 2: *(inst)++ = 0x8b; \
1668 *(inst)++ = 0xc0; break; \
1669 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
1670 *(inst)++ = 0x00; break; \
1671 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1672 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1674 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1675 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1676 x86_nop ((inst)); break; \
1677 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
1678 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1679 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1681 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
1682 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1683 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1684 *(inst)++ = 0x00; break; \
1685 default: assert (0); \
1689 #define x86_prolog(inst,frame_size,reg_mask) \
1691 unsigned i, m = 1; \
1692 x86_enter ((inst), (frame_size)); \
1693 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
1694 if ((reg_mask) & m) \
1695 x86_push_reg ((inst), i); \
1699 #define x86_epilog(inst,reg_mask) \
1701 unsigned i, m = 1 << X86_EDI; \
1702 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
1703 if ((reg_mask) & m) \
1704 x86_pop_reg ((inst), i); \
1706 x86_leave ((inst)); \
1712 X86_SSE_SQRT = 0x51,
1713 X86_SSE_RSQRT = 0x52,
1721 X86_SSE_ADDSUB = 0xD0,
1722 X86_SSE_HADD = 0x7C,
1723 X86_SSE_HSUB = 0x7D,
1725 X86_SSE_PAND = 0xDB,
1727 X86_SSE_PXOR = 0xEF,
1729 X86_SSE_PADDB = 0xFC,
1730 X86_SSE_PADDW = 0xFD,
1731 X86_SSE_PADDD = 0xFE,
1733 X86_SSE_PSUBB = 0xF8,
1734 X86_SSE_PSUBW = 0xF9,
1735 X86_SSE_PSUBD = 0xFA,
1737 X86_SSE_PUNPCKLBW = 0x60,
1738 X86_SSE_PUNPCKLWD = 0x61,
1739 X86_SSE_PUNPCKLDQ = 0x62,
1740 X86_SSE_PUNPCKLQDQ = 0x6C,
1742 X86_SSE_PUNPCKHBW = 0x68,
1743 X86_SSE_PUNPCKHWD = 0x69,
1744 X86_SSE_PUNPCKHDQ = 0x6A,
1745 X86_SSE_PUNPCKHQDQ = 0x6D,
1747 X86_SSE_PADDUSB = 0xDC,
1748 X86_SSE_PADDUSW = 0xDD,
1749 X86_SSE_PSUBUSB = 0xD8,
1750 X86_SSE_PSUBUSW = 0xD9,
1752 X86_SSE_PMULLW = 0xD5,
1754 X86_SSE_PSHIFTW = 0x71,
1759 X86_SSE_PSRLW_REG = 0xD1,
1760 X86_SSE_PSRAW_REG = 0xE1,
1761 X86_SSE_PSLLW_REG = 0xF1,
1766 /* minimal SSE* support */
1767 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
1769 *(inst)++ = (unsigned char)0xf2; \
1770 *(inst)++ = (unsigned char)0x0f; \
1771 *(inst)++ = (unsigned char)0x10; \
1772 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1775 #define x86_cvttsd2si(inst,dreg,reg) \
1777 *(inst)++ = (unsigned char)0xf2; \
1778 *(inst)++ = (unsigned char)0x0f; \
1779 *(inst)++ = (unsigned char)0x2c; \
1780 x86_reg_emit ((inst), (dreg), (reg)); \
1783 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
1785 *(inst)++ = (unsigned char)0x0F; \
1786 *(inst)++ = (unsigned char)(opc); \
1787 x86_reg_emit ((inst), (dreg), (reg)); \
1790 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
1792 *(inst)++ = (unsigned char)0x66; \
1793 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
1796 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
1798 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
1801 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
1803 *(inst)++ = (unsigned char)0xF2; \
1804 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
1807 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
1809 *(inst)++ = (unsigned char)0xF3; \
1810 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
1813 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
1815 *(inst)++ = (unsigned char)0x0f; \
1816 *(inst)++ = (unsigned char)0x10; \
1817 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
1820 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
1822 *(inst)++ = (unsigned char)0x0f; \
1823 *(inst)++ = (unsigned char)0x11; \
1824 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1827 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
1829 *(inst)++ = (unsigned char)0x0f; \
1830 *(inst)++ = (unsigned char)0x28; \
1831 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
1834 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
1836 *(inst)++ = (unsigned char)0x0f; \
1837 *(inst)++ = (unsigned char)0x29; \
1838 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1841 #define x86_movaps_reg_reg(inst,dreg,sreg) \
1843 *(inst)++ = (unsigned char)0x0f; \
1844 *(inst)++ = (unsigned char)0x28; \
1845 x86_reg_emit ((inst), (dreg), (sreg)); \
1849 #define x86_movd_reg_xreg(inst,dreg,sreg) \
1851 *(inst)++ = (unsigned char)0x66; \
1852 *(inst)++ = (unsigned char)0x0f; \
1853 *(inst)++ = (unsigned char)0x7e; \
1854 x86_reg_emit ((inst), (sreg), (dreg)); \
1857 #define x86_movd_xreg_reg(inst,dreg,sreg) \
1859 *(inst)++ = (unsigned char)0x66; \
1860 *(inst)++ = (unsigned char)0x0f; \
1861 *(inst)++ = (unsigned char)0x6e; \
1862 x86_reg_emit ((inst), (dreg), (sreg)); \
1865 #define x86_pshufd_reg_reg(inst,dreg,sreg,mask) \
1867 *(inst)++ = (unsigned char)0x66; \
1868 *(inst)++ = (unsigned char)0x0f; \
1869 *(inst)++ = (unsigned char)0x70; \
1870 x86_reg_emit ((inst), (dreg), (sreg)); \
1871 *(inst)++ = (unsigned char)mask; \
1874 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
1876 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
1877 x86_imm_emit8 ((inst), (imm)); \
1880 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
1882 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \