2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 #ifdef __native_client_codegen__
20 #define kNaClAlignment 32
21 #define kNaClAlignmentMask (kNaClAlignment - 1)
22 extern guint8 nacl_align_byte;
23 #endif /* __native_client_codegen__ */
26 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
27 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do { mono_nacl_align_inst(inst_ptr_ptr, inst_len); } while (0)
28 #define x86_call_sequence_pre(inst) guint8* _code_start = (inst);
29 #define x86_call_sequence_post(inst) \
30 (mono_nacl_align_call(&_code_start, &(inst)), _code_start);
31 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
32 #define x86_call_sequence_post_val(inst) \
33 (mono_nacl_align_call(&_code_start, &(inst)), _code_start);
35 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do {} while (0)
36 #define x86_call_sequence_pre(inst)
37 #define x86_call_sequence_post(inst)
38 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
39 #define x86_call_sequence_post_val(inst) _code_start
40 #endif /* __native_client_codegen__ */
44 // x86 register numbers
71 // opcodes for alu instructions
85 // opcodes for shift instructions
100 // opcodes for floating-point instructions
114 // integer conditions codes
117 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
118 X86_CC_NE = 1, X86_CC_NZ = 1,
119 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
120 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
121 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
122 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
123 X86_CC_LZ = 6, X86_CC_S = 6,
124 X86_CC_GEZ = 7, X86_CC_NS = 7,
125 X86_CC_P = 8, X86_CC_PE = 8,
126 X86_CC_NP = 9, X86_CC_PO = 9,
138 X86_FP_CC_MASK = 0x4500
141 /* FP control word */
143 X86_FPCW_INVOPEX_MASK = 0x1,
144 X86_FPCW_DENOPEX_MASK = 0x2,
145 X86_FPCW_ZERODIV_MASK = 0x4,
146 X86_FPCW_OVFEX_MASK = 0x8,
147 X86_FPCW_UNDFEX_MASK = 0x10,
148 X86_FPCW_PRECEX_MASK = 0x20,
149 X86_FPCW_PRECC_MASK = 0x300,
150 X86_FPCW_ROUNDC_MASK = 0xc00,
152 /* values for precision control */
153 X86_FPCW_PREC_SINGLE = 0,
154 X86_FPCW_PREC_DOUBLE = 0x200,
155 X86_FPCW_PREC_EXTENDED = 0x300,
157 /* values for rounding control */
158 X86_FPCW_ROUND_NEAREST = 0,
159 X86_FPCW_ROUND_DOWN = 0x400,
160 X86_FPCW_ROUND_UP = 0x800,
161 X86_FPCW_ROUND_TOZERO = 0xc00
168 X86_LOCK_PREFIX = 0xF0,
169 X86_REPNZ_PREFIX = 0xF2,
170 X86_REPZ_PREFIX = 0xF3,
171 X86_REP_PREFIX = 0xF3,
172 X86_CS_PREFIX = 0x2E,
173 X86_SS_PREFIX = 0x36,
174 X86_DS_PREFIX = 0x3E,
175 X86_ES_PREFIX = 0x26,
176 X86_FS_PREFIX = 0x64,
177 X86_GS_PREFIX = 0x65,
178 X86_UNLIKELY_PREFIX = 0x2E,
179 X86_LIKELY_PREFIX = 0x3E,
180 X86_OPERAND_PREFIX = 0x66,
181 X86_ADDRESS_PREFIX = 0x67
184 static const unsigned char
185 x86_cc_unsigned_map [X86_NCC] = {
200 static const unsigned char
201 x86_cc_signed_map [X86_NCC] = {
221 #define X86_NOBASEREG (-1)
224 // bitvector mask for callee-saved registers
226 #define X86_ESI_MASK (1<<X86_ESI)
227 #define X86_EDI_MASK (1<<X86_EDI)
228 #define X86_EBX_MASK (1<<X86_EBX)
229 #define X86_EBP_MASK (1<<X86_EBP)
231 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
232 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
233 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
235 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
236 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
238 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
243 // +--------------------------------+
244 // | in_arg[0] = var[0] |
245 // | in_arg[1] = var[1] |
247 // | in_arg[n_arg-1] = var[n_arg-1] |
248 // +--------------------------------+
250 // +--------------------------------+
251 // | saved EBP | <-- frame pointer (EBP)
252 // +--------------------------------+
254 // +--------------------------------+
256 // | var[n_arg+1] | local variables area
259 // +--------------------------------+
262 // | spill area | area for spilling mimic stack
264 // +--------------------------------|
266 // | ebp [ESP_Frame only] |
267 // | esi | 0..3 callee-saved regs
268 // | edi | <-- stack pointer (ESP)
269 // +--------------------------------+
271 // | stk1 | operand stack area/
272 // | . . . | out args
274 // +--------------------------------|
281 * useful building blocks
283 #define x86_modrm_mod(modrm) ((modrm) >> 6)
284 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
285 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
287 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
288 #define x86_imm_emit32(inst,imm) \
290 x86_imm_buf imb; imb.val = (int) (imm); \
291 *(inst)++ = imb.b [0]; \
292 *(inst)++ = imb.b [1]; \
293 *(inst)++ = imb.b [2]; \
294 *(inst)++ = imb.b [3]; \
296 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
297 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
298 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
299 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
301 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
302 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
303 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
304 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
306 #define kMaxMembaseEmitPadding 6
308 #define x86_membase_emit(inst,r,basereg,disp) do {\
309 if ((basereg) == X86_ESP) { \
311 x86_address_byte ((inst), 0, (r), X86_ESP); \
312 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
313 } else if (x86_is_imm8((disp))) { \
314 x86_address_byte ((inst), 1, (r), X86_ESP); \
315 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
316 x86_imm_emit8 ((inst), (disp)); \
318 x86_address_byte ((inst), 2, (r), X86_ESP); \
319 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
320 x86_imm_emit32 ((inst), (disp)); \
324 if ((disp) == 0 && (basereg) != X86_EBP) { \
325 x86_address_byte ((inst), 0, (r), (basereg)); \
328 if (x86_is_imm8((disp))) { \
329 x86_address_byte ((inst), 1, (r), (basereg)); \
330 x86_imm_emit8 ((inst), (disp)); \
332 x86_address_byte ((inst), 2, (r), (basereg)); \
333 x86_imm_emit32 ((inst), (disp)); \
337 #define kMaxMemindexEmitPadding 6
339 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
341 if ((basereg) == X86_NOBASEREG) { \
342 x86_address_byte ((inst), 0, (r), 4); \
343 x86_address_byte ((inst), (shift), (indexreg), 5); \
344 x86_imm_emit32 ((inst), (disp)); \
345 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
346 x86_address_byte ((inst), 0, (r), 4); \
347 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
348 } else if (x86_is_imm8((disp))) { \
349 x86_address_byte ((inst), 1, (r), 4); \
350 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
351 x86_imm_emit8 ((inst), (disp)); \
353 x86_address_byte ((inst), 2, (r), 4); \
354 x86_address_byte ((inst), (shift), (indexreg), 5); \
355 x86_imm_emit32 ((inst), (disp)); \
360 * target is the position in the code where to jump to:
362 * .. output loop code...
363 * x86_mov_reg_imm (code, X86_EAX, 0);
365 * x86_loop (code, -1);
369 * x86_patch (loop, target);
371 * ins should point at the start of the instruction that encodes a target.
372 * the instruction is inspected for validity and the correct displacement
375 #define x86_do_patch(ins,target) \
377 unsigned char* pos = (ins) + 1; \
378 int disp, size = 0; \
379 switch (*(unsigned char*)(ins)) { \
380 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
381 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
382 ++size; ++pos; break; /* prefix for 32-bit disp */ \
383 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
384 case 0xeb: /* jump8 */ \
385 /* conditional jump opcodes */ \
386 case 0x70: case 0x71: case 0x72: case 0x73: \
387 case 0x74: case 0x75: case 0x76: case 0x77: \
388 case 0x78: case 0x79: case 0x7a: case 0x7b: \
389 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
391 default: assert (0); \
393 disp = (target) - pos; \
394 if (size) x86_imm_emit32 (pos, disp - 4); \
395 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
399 #if defined( __native_client_codegen__ ) && defined(TARGET_X86)
401 #define x86_skip_nops(inst) \
406 if (inst[0] == 0x90) { \
410 if (inst[0] == 0x8b && inst[1] == 0xc0) { \
414 if (inst[0] == 0x8d && inst[1] == 0x6d \
415 && inst[2] == 0x00) { \
419 if (inst[0] == 0x8d && inst[1] == 0x64 \
420 && inst[2] == 0x24 && inst[3] == 0x00) { \
424 /* skip inst+=5 case because it's the 4-byte + 1-byte case */ \
425 if (inst[0] == 0x8d && inst[1] == 0xad \
426 && inst[2] == 0x00 && inst[3] == 0x00 \
427 && inst[4] == 0x00 && inst[5] == 0x00) { \
431 if (inst[0] == 0x8d && inst[1] == 0xa4 \
432 && inst[2] == 0x24 && inst[3] == 0x00 \
433 && inst[4] == 0x00 && inst[5] == 0x00 \
434 && inst[6] == 0x00 ) { \
438 } while ( in_nop ); \
441 #define x86_patch(ins,target) \
443 unsigned char* inst = (ins); \
444 x86_skip_nops((inst)); \
445 x86_do_patch((inst), (target)); \
449 #define x86_patch(ins,target) do { x86_do_patch((ins), (target)); } while (0)
450 #endif /* __native_client_codegen__ */
452 #ifdef __native_client_codegen__
453 /* The breakpoint instruction is illegal in Native Client, although the HALT */
454 /* instruction is allowed. The breakpoint is used several places in mini-x86.c */
455 /* and exceptions-x86.c. */
456 #define x86_breakpoint(inst) \
461 #define x86_breakpoint(inst) \
467 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
468 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
469 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
470 #define x86_stosd(inst) x86_stosl((inst))
471 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
472 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
473 #define x86_movsd(inst) x86_movsl((inst))
475 /* kNaClAlignment - 1 is the max value we can pass into x86_codegen_pre. */
476 /* This keeps us from having to call x86_codegen_pre with specific */
477 /* knowledge of the size of the instruction that follows it, and */
478 /* localizes the alignment requirement to this spot. */
479 #define x86_prefix(inst,p) \
481 x86_codegen_pre(&(inst), kNaClAlignment - 1); \
482 *(inst)++ =(unsigned char) (p); \
485 #define x86_rdtsc(inst) \
491 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
493 x86_codegen_pre(&(inst), 3); \
494 *(inst)++ = (unsigned char)0x0f; \
495 *(inst)++ = (unsigned char)0xb1; \
496 x86_reg_emit ((inst), (reg), (dreg)); \
499 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
501 x86_codegen_pre(&(inst), 7); \
502 *(inst)++ = (unsigned char)0x0f; \
503 *(inst)++ = (unsigned char)0xb1; \
504 x86_mem_emit ((inst), (reg), (mem)); \
507 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
509 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
510 *(inst)++ = (unsigned char)0x0f; \
511 *(inst)++ = (unsigned char)0xb1; \
512 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
515 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
517 x86_codegen_pre(&(inst), 2); \
519 *(inst)++ = (unsigned char)0x86; \
521 *(inst)++ = (unsigned char)0x87; \
522 x86_reg_emit ((inst), (reg), (dreg)); \
525 #define x86_xchg_mem_reg(inst,mem,reg,size) \
527 x86_codegen_pre(&(inst), 6); \
529 *(inst)++ = (unsigned char)0x86; \
531 *(inst)++ = (unsigned char)0x87; \
532 x86_mem_emit ((inst), (reg), (mem)); \
535 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
537 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
539 *(inst)++ = (unsigned char)0x86; \
541 *(inst)++ = (unsigned char)0x87; \
542 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
545 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
547 x86_codegen_pre(&(inst), 4); \
548 *(inst)++ = (unsigned char)0x0F; \
550 *(inst)++ = (unsigned char)0xC0; \
552 *(inst)++ = (unsigned char)0xC1; \
553 x86_reg_emit ((inst), (reg), (dreg)); \
556 #define x86_xadd_mem_reg(inst,mem,reg,size) \
558 x86_codegen_pre(&(inst), 7); \
559 *(inst)++ = (unsigned char)0x0F; \
561 *(inst)++ = (unsigned char)0xC0; \
563 *(inst)++ = (unsigned char)0xC1; \
564 x86_mem_emit ((inst), (reg), (mem)); \
567 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
569 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
570 *(inst)++ = (unsigned char)0x0F; \
572 *(inst)++ = (unsigned char)0xC0; \
574 *(inst)++ = (unsigned char)0xC1; \
575 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
578 #define x86_inc_mem(inst,mem) \
580 x86_codegen_pre(&(inst), 6); \
581 *(inst)++ = (unsigned char)0xff; \
582 x86_mem_emit ((inst), 0, (mem)); \
585 #define x86_inc_membase(inst,basereg,disp) \
587 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
588 *(inst)++ = (unsigned char)0xff; \
589 x86_membase_emit ((inst), 0, (basereg), (disp)); \
592 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
594 #define x86_dec_mem(inst,mem) \
596 x86_codegen_pre(&(inst), 6); \
597 *(inst)++ = (unsigned char)0xff; \
598 x86_mem_emit ((inst), 1, (mem)); \
601 #define x86_dec_membase(inst,basereg,disp) \
603 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
604 *(inst)++ = (unsigned char)0xff; \
605 x86_membase_emit ((inst), 1, (basereg), (disp)); \
608 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
610 #define x86_not_mem(inst,mem) \
612 x86_codegen_pre(&(inst), 6); \
613 *(inst)++ = (unsigned char)0xf7; \
614 x86_mem_emit ((inst), 2, (mem)); \
617 #define x86_not_membase(inst,basereg,disp) \
619 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
620 *(inst)++ = (unsigned char)0xf7; \
621 x86_membase_emit ((inst), 2, (basereg), (disp)); \
624 #define x86_not_reg(inst,reg) \
626 x86_codegen_pre(&(inst), 2); \
627 *(inst)++ = (unsigned char)0xf7; \
628 x86_reg_emit ((inst), 2, (reg)); \
631 #define x86_neg_mem(inst,mem) \
633 x86_codegen_pre(&(inst), 2); \
634 *(inst)++ = (unsigned char)0xf7; \
635 x86_mem_emit ((inst), 3, (mem)); \
638 #define x86_neg_membase(inst,basereg,disp) \
640 x86_codegen_pre(&(inst), 6); \
641 *(inst)++ = (unsigned char)0xf7; \
642 x86_membase_emit ((inst), 3, (basereg), (disp)); \
645 #define x86_neg_reg(inst,reg) \
647 x86_codegen_pre(&(inst), 2); \
648 *(inst)++ = (unsigned char)0xf7; \
649 x86_reg_emit ((inst), 3, (reg)); \
652 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
654 #define x86_alu_reg_imm(inst,opc,reg,imm) \
656 if ((reg) == X86_EAX) { \
657 x86_codegen_pre(&(inst), 5); \
658 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
659 x86_imm_emit32 ((inst), (imm)); \
662 if (x86_is_imm8((imm))) { \
663 x86_codegen_pre(&(inst), 3); \
664 *(inst)++ = (unsigned char)0x83; \
665 x86_reg_emit ((inst), (opc), (reg)); \
666 x86_imm_emit8 ((inst), (imm)); \
668 x86_codegen_pre(&(inst), 6); \
669 *(inst)++ = (unsigned char)0x81; \
670 x86_reg_emit ((inst), (opc), (reg)); \
671 x86_imm_emit32 ((inst), (imm)); \
675 #define x86_alu_mem_imm(inst,opc,mem,imm) \
677 if (x86_is_imm8((imm))) { \
678 x86_codegen_pre(&(inst), 7); \
679 *(inst)++ = (unsigned char)0x83; \
680 x86_mem_emit ((inst), (opc), (mem)); \
681 x86_imm_emit8 ((inst), (imm)); \
683 x86_codegen_pre(&(inst), 10); \
684 *(inst)++ = (unsigned char)0x81; \
685 x86_mem_emit ((inst), (opc), (mem)); \
686 x86_imm_emit32 ((inst), (imm)); \
690 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
692 if (x86_is_imm8((imm))) { \
693 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
694 *(inst)++ = (unsigned char)0x83; \
695 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
696 x86_imm_emit8 ((inst), (imm)); \
698 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
699 *(inst)++ = (unsigned char)0x81; \
700 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
701 x86_imm_emit32 ((inst), (imm)); \
705 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
707 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
708 *(inst)++ = (unsigned char)0x80; \
709 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
710 x86_imm_emit8 ((inst), (imm)); \
713 #define x86_alu_mem_reg(inst,opc,mem,reg) \
715 x86_codegen_pre(&(inst), 6); \
716 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
717 x86_mem_emit ((inst), (reg), (mem)); \
720 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
722 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
723 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
724 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
727 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
729 x86_codegen_pre(&(inst), 2); \
730 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
731 x86_reg_emit ((inst), (dreg), (reg)); \
735 * @x86_alu_reg8_reg8:
736 * Supports ALU operations between two 8-bit registers.
737 * dreg := dreg opc reg
738 * X86_Reg_No enum is used to specify the registers.
739 * Additionally is_*_h flags are used to specify what part
740 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
741 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
743 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
745 x86_codegen_pre(&(inst), 2); \
746 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
747 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
750 #define x86_alu_reg_mem(inst,opc,reg,mem) \
752 x86_codegen_pre(&(inst), 6); \
753 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
754 x86_mem_emit ((inst), (reg), (mem)); \
757 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
759 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
760 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
761 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
764 #define x86_test_reg_imm(inst,reg,imm) \
766 x86_codegen_pre(&(inst), 6); \
767 if ((reg) == X86_EAX) { \
768 *(inst)++ = (unsigned char)0xa9; \
770 *(inst)++ = (unsigned char)0xf7; \
771 x86_reg_emit ((inst), 0, (reg)); \
773 x86_imm_emit32 ((inst), (imm)); \
776 #define x86_test_mem_imm(inst,mem,imm) \
778 x86_codegen_pre(&(inst), 10); \
779 *(inst)++ = (unsigned char)0xf7; \
780 x86_mem_emit ((inst), 0, (mem)); \
781 x86_imm_emit32 ((inst), (imm)); \
784 #define x86_test_membase_imm(inst,basereg,disp,imm) \
786 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
787 *(inst)++ = (unsigned char)0xf7; \
788 x86_membase_emit ((inst), 0, (basereg), (disp)); \
789 x86_imm_emit32 ((inst), (imm)); \
792 #define x86_test_reg_reg(inst,dreg,reg) \
794 x86_codegen_pre(&(inst), 2); \
795 *(inst)++ = (unsigned char)0x85; \
796 x86_reg_emit ((inst), (reg), (dreg)); \
799 #define x86_test_mem_reg(inst,mem,reg) \
801 x86_codegen_pre(&(inst), 6); \
802 *(inst)++ = (unsigned char)0x85; \
803 x86_mem_emit ((inst), (reg), (mem)); \
806 #define x86_test_membase_reg(inst,basereg,disp,reg) \
808 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
809 *(inst)++ = (unsigned char)0x85; \
810 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
813 #define x86_shift_reg_imm(inst,opc,reg,imm) \
816 x86_codegen_pre(&(inst), 2); \
817 *(inst)++ = (unsigned char)0xd1; \
818 x86_reg_emit ((inst), (opc), (reg)); \
820 x86_codegen_pre(&(inst), 3); \
821 *(inst)++ = (unsigned char)0xc1; \
822 x86_reg_emit ((inst), (opc), (reg)); \
823 x86_imm_emit8 ((inst), (imm)); \
827 #define x86_shift_mem_imm(inst,opc,mem,imm) \
830 x86_codegen_pre(&(inst), 6); \
831 *(inst)++ = (unsigned char)0xd1; \
832 x86_mem_emit ((inst), (opc), (mem)); \
834 x86_codegen_pre(&(inst), 7); \
835 *(inst)++ = (unsigned char)0xc1; \
836 x86_mem_emit ((inst), (opc), (mem)); \
837 x86_imm_emit8 ((inst), (imm)); \
841 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
844 x86_codegen_pre(&(inst), 6); \
845 *(inst)++ = (unsigned char)0xd1; \
846 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
848 x86_codegen_pre(&(inst), 7); \
849 *(inst)++ = (unsigned char)0xc1; \
850 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
851 x86_imm_emit8 ((inst), (imm)); \
855 #define x86_shift_reg(inst,opc,reg) \
857 x86_codegen_pre(&(inst), 2); \
858 *(inst)++ = (unsigned char)0xd3; \
859 x86_reg_emit ((inst), (opc), (reg)); \
862 #define x86_shift_mem(inst,opc,mem) \
864 x86_codegen_pre(&(inst), 6); \
865 *(inst)++ = (unsigned char)0xd3; \
866 x86_mem_emit ((inst), (opc), (mem)); \
869 #define x86_shift_membase(inst,opc,basereg,disp) \
871 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
872 *(inst)++ = (unsigned char)0xd3; \
873 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
877 * Multi op shift missing.
880 #define x86_shrd_reg(inst,dreg,reg) \
882 x86_codegen_pre(&(inst), 3); \
883 *(inst)++ = (unsigned char)0x0f; \
884 *(inst)++ = (unsigned char)0xad; \
885 x86_reg_emit ((inst), (reg), (dreg)); \
888 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
890 x86_codegen_pre(&(inst), 4); \
891 *(inst)++ = (unsigned char)0x0f; \
892 *(inst)++ = (unsigned char)0xac; \
893 x86_reg_emit ((inst), (reg), (dreg)); \
894 x86_imm_emit8 ((inst), (shamt)); \
897 #define x86_shld_reg(inst,dreg,reg) \
899 x86_codegen_pre(&(inst), 3); \
900 *(inst)++ = (unsigned char)0x0f; \
901 *(inst)++ = (unsigned char)0xa5; \
902 x86_reg_emit ((inst), (reg), (dreg)); \
905 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
907 x86_codegen_pre(&(inst), 4); \
908 *(inst)++ = (unsigned char)0x0f; \
909 *(inst)++ = (unsigned char)0xa4; \
910 x86_reg_emit ((inst), (reg), (dreg)); \
911 x86_imm_emit8 ((inst), (shamt)); \
917 #define x86_mul_reg(inst,reg,is_signed) \
919 x86_codegen_pre(&(inst), 2); \
920 *(inst)++ = (unsigned char)0xf7; \
921 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
924 #define x86_mul_mem(inst,mem,is_signed) \
926 x86_codegen_pre(&(inst), 6); \
927 *(inst)++ = (unsigned char)0xf7; \
928 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
931 #define x86_mul_membase(inst,basereg,disp,is_signed) \
933 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
934 *(inst)++ = (unsigned char)0xf7; \
935 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
941 #define x86_imul_reg_reg(inst,dreg,reg) \
943 x86_codegen_pre(&(inst), 3); \
944 *(inst)++ = (unsigned char)0x0f; \
945 *(inst)++ = (unsigned char)0xaf; \
946 x86_reg_emit ((inst), (dreg), (reg)); \
949 #define x86_imul_reg_mem(inst,reg,mem) \
951 x86_codegen_pre(&(inst), 7); \
952 *(inst)++ = (unsigned char)0x0f; \
953 *(inst)++ = (unsigned char)0xaf; \
954 x86_mem_emit ((inst), (reg), (mem)); \
957 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
959 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
960 *(inst)++ = (unsigned char)0x0f; \
961 *(inst)++ = (unsigned char)0xaf; \
962 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
968 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
970 if (x86_is_imm8 ((imm))) { \
971 x86_codegen_pre(&(inst), 3); \
972 *(inst)++ = (unsigned char)0x6b; \
973 x86_reg_emit ((inst), (dreg), (reg)); \
974 x86_imm_emit8 ((inst), (imm)); \
976 x86_codegen_pre(&(inst), 6); \
977 *(inst)++ = (unsigned char)0x69; \
978 x86_reg_emit ((inst), (dreg), (reg)); \
979 x86_imm_emit32 ((inst), (imm)); \
983 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
985 if (x86_is_imm8 ((imm))) { \
986 x86_codegen_pre(&(inst), 7); \
987 *(inst)++ = (unsigned char)0x6b; \
988 x86_mem_emit ((inst), (reg), (mem)); \
989 x86_imm_emit8 ((inst), (imm)); \
991 x86_codegen_pre(&(inst), 6); \
992 *(inst)++ = (unsigned char)0x69; \
993 x86_reg_emit ((inst), (reg), (mem)); \
994 x86_imm_emit32 ((inst), (imm)); \
998 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
1000 if (x86_is_imm8 ((imm))) { \
1001 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1002 *(inst)++ = (unsigned char)0x6b; \
1003 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1004 x86_imm_emit8 ((inst), (imm)); \
1006 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1007 *(inst)++ = (unsigned char)0x69; \
1008 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1009 x86_imm_emit32 ((inst), (imm)); \
1014 * divide EDX:EAX by rm;
1015 * eax = quotient, edx = remainder
1018 #define x86_div_reg(inst,reg,is_signed) \
1020 x86_codegen_pre(&(inst), 2); \
1021 *(inst)++ = (unsigned char)0xf7; \
1022 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
1025 #define x86_div_mem(inst,mem,is_signed) \
1027 x86_codegen_pre(&(inst), 6); \
1028 *(inst)++ = (unsigned char)0xf7; \
1029 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
1032 #define x86_div_membase(inst,basereg,disp,is_signed) \
1034 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1035 *(inst)++ = (unsigned char)0xf7; \
1036 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
1039 #define x86_mov_mem_reg(inst,mem,reg,size) \
1041 x86_codegen_pre(&(inst), 7); \
1043 case 1: *(inst)++ = (unsigned char)0x88; break; \
1044 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1045 case 4: *(inst)++ = (unsigned char)0x89; break; \
1046 default: assert (0); \
1048 x86_mem_emit ((inst), (reg), (mem)); \
1051 #define x86_mov_regp_reg(inst,regp,reg,size) \
1053 x86_codegen_pre(&(inst), 3); \
1055 case 1: *(inst)++ = (unsigned char)0x88; break; \
1056 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1057 case 4: *(inst)++ = (unsigned char)0x89; break; \
1058 default: assert (0); \
1060 x86_regp_emit ((inst), (reg), (regp)); \
1063 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
1065 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1067 case 1: *(inst)++ = (unsigned char)0x88; break; \
1068 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1069 case 4: *(inst)++ = (unsigned char)0x89; break; \
1070 default: assert (0); \
1072 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1075 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
1077 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1079 case 1: *(inst)++ = (unsigned char)0x88; break; \
1080 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1081 case 4: *(inst)++ = (unsigned char)0x89; break; \
1082 default: assert (0); \
1084 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1087 #define x86_mov_reg_reg(inst,dreg,reg,size) \
1089 x86_codegen_pre(&(inst), 3); \
1091 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1092 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1093 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1094 default: assert (0); \
1096 x86_reg_emit ((inst), (dreg), (reg)); \
1099 #define x86_mov_reg_mem(inst,reg,mem,size) \
1101 x86_codegen_pre(&(inst), 7); \
1103 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1104 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1105 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1106 default: assert (0); \
1108 x86_mem_emit ((inst), (reg), (mem)); \
1111 #define kMovRegMembasePadding (2 + kMaxMembaseEmitPadding)
1113 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
1115 x86_codegen_pre(&(inst), kMovRegMembasePadding); \
1117 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1118 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1119 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1120 default: assert (0); \
1122 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1125 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
1127 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1129 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1130 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
1131 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1132 default: assert (0); \
1134 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1138 * Note: x86_clear_reg () chacnges the condition code!
1140 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
1142 #define x86_mov_reg_imm(inst,reg,imm) \
1144 x86_codegen_pre(&(inst), 5); \
1145 *(inst)++ = (unsigned char)0xb8 + (reg); \
1146 x86_imm_emit32 ((inst), (imm)); \
1149 #define x86_mov_mem_imm(inst,mem,imm,size) \
1151 if ((size) == 1) { \
1152 x86_codegen_pre(&(inst), 7); \
1153 *(inst)++ = (unsigned char)0xc6; \
1154 x86_mem_emit ((inst), 0, (mem)); \
1155 x86_imm_emit8 ((inst), (imm)); \
1156 } else if ((size) == 2) { \
1157 x86_codegen_pre(&(inst), 9); \
1158 *(inst)++ = (unsigned char)0x66; \
1159 *(inst)++ = (unsigned char)0xc7; \
1160 x86_mem_emit ((inst), 0, (mem)); \
1161 x86_imm_emit16 ((inst), (imm)); \
1163 x86_codegen_pre(&(inst), 10); \
1164 *(inst)++ = (unsigned char)0xc7; \
1165 x86_mem_emit ((inst), 0, (mem)); \
1166 x86_imm_emit32 ((inst), (imm)); \
1170 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
1172 if ((size) == 1) { \
1173 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1174 *(inst)++ = (unsigned char)0xc6; \
1175 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1176 x86_imm_emit8 ((inst), (imm)); \
1177 } else if ((size) == 2) { \
1178 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
1179 *(inst)++ = (unsigned char)0x66; \
1180 *(inst)++ = (unsigned char)0xc7; \
1181 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1182 x86_imm_emit16 ((inst), (imm)); \
1184 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1185 *(inst)++ = (unsigned char)0xc7; \
1186 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1187 x86_imm_emit32 ((inst), (imm)); \
1191 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1193 if ((size) == 1) { \
1194 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1195 *(inst)++ = (unsigned char)0xc6; \
1196 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1197 x86_imm_emit8 ((inst), (imm)); \
1198 } else if ((size) == 2) { \
1199 x86_codegen_pre(&(inst), 4 + kMaxMemindexEmitPadding); \
1200 *(inst)++ = (unsigned char)0x66; \
1201 *(inst)++ = (unsigned char)0xc7; \
1202 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1203 x86_imm_emit16 ((inst), (imm)); \
1205 x86_codegen_pre(&(inst), 5 + kMaxMemindexEmitPadding); \
1206 *(inst)++ = (unsigned char)0xc7; \
1207 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1208 x86_imm_emit32 ((inst), (imm)); \
1212 #define x86_lea_mem(inst,reg,mem) \
1214 x86_codegen_pre(&(inst), 5); \
1215 *(inst)++ = (unsigned char)0x8d; \
1216 x86_mem_emit ((inst), (reg), (mem)); \
1219 #define x86_lea_membase(inst,reg,basereg,disp) \
1221 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1222 *(inst)++ = (unsigned char)0x8d; \
1223 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1226 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1228 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1229 *(inst)++ = (unsigned char)0x8d; \
1230 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1233 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1235 unsigned char op = 0xb6; \
1236 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1237 x86_codegen_pre(&(inst), 3); \
1238 *(inst)++ = (unsigned char)0x0f; \
1239 if ((is_signed)) op += 0x08; \
1240 if ((is_half)) op += 0x01; \
1242 x86_reg_emit ((inst), (dreg), (reg)); \
1245 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1247 unsigned char op = 0xb6; \
1248 x86_codegen_pre(&(inst), 7); \
1249 *(inst)++ = (unsigned char)0x0f; \
1250 if ((is_signed)) op += 0x08; \
1251 if ((is_half)) op += 0x01; \
1253 x86_mem_emit ((inst), (dreg), (mem)); \
1256 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1258 unsigned char op = 0xb6; \
1259 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1260 *(inst)++ = (unsigned char)0x0f; \
1261 if ((is_signed)) op += 0x08; \
1262 if ((is_half)) op += 0x01; \
1264 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1267 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1269 unsigned char op = 0xb6; \
1270 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1271 *(inst)++ = (unsigned char)0x0f; \
1272 if ((is_signed)) op += 0x08; \
1273 if ((is_half)) op += 0x01; \
1275 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1278 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1279 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1281 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1283 x86_codegen_pre(&(inst), 6); \
1284 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1285 x86_mem_emit ((inst), (opc), (mem)); \
1288 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1290 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1291 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1292 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1295 #define x86_fp_op(inst,opc,index) \
1297 x86_codegen_pre(&(inst), 2); \
1298 *(inst)++ = (unsigned char)0xd8; \
1299 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1302 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1304 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1305 x86_codegen_pre(&(inst), 2); \
1306 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1307 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1311 * @x86_fp_int_op_membase
1312 * Supports FPU operations between ST(0) and integer operand in memory.
1313 * Operation encoded using X86_FP_Opcode enum.
1314 * Operand is addressed by [basereg + disp].
1315 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1317 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1319 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1320 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1321 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1324 #define x86_fstp(inst,index) \
1326 x86_codegen_pre(&(inst), 2); \
1327 *(inst)++ = (unsigned char)0xdd; \
1328 *(inst)++ = (unsigned char)0xd8+(index); \
1331 #define x86_fcompp(inst) \
1333 x86_codegen_pre(&(inst), 2); \
1334 *(inst)++ = (unsigned char)0xde; \
1335 *(inst)++ = (unsigned char)0xd9; \
1338 #define x86_fucompp(inst) \
1340 x86_codegen_pre(&(inst), 2); \
1341 *(inst)++ = (unsigned char)0xda; \
1342 *(inst)++ = (unsigned char)0xe9; \
1345 #define x86_fnstsw(inst) \
1347 x86_codegen_pre(&(inst), 2); \
1348 *(inst)++ = (unsigned char)0xdf; \
1349 *(inst)++ = (unsigned char)0xe0; \
1352 #define x86_fnstcw(inst,mem) \
1354 x86_codegen_pre(&(inst), 6); \
1355 *(inst)++ = (unsigned char)0xd9; \
1356 x86_mem_emit ((inst), 7, (mem)); \
1359 #define x86_fnstcw_membase(inst,basereg,disp) \
1361 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1362 *(inst)++ = (unsigned char)0xd9; \
1363 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1366 #define x86_fldcw(inst,mem) \
1368 x86_codegen_pre(&(inst), 6); \
1369 *(inst)++ = (unsigned char)0xd9; \
1370 x86_mem_emit ((inst), 5, (mem)); \
1373 #define x86_fldcw_membase(inst,basereg,disp) \
1375 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1376 *(inst)++ = (unsigned char)0xd9; \
1377 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1380 #define x86_fchs(inst) \
1382 x86_codegen_pre(&(inst), 2); \
1383 *(inst)++ = (unsigned char)0xd9; \
1384 *(inst)++ = (unsigned char)0xe0; \
1387 #define x86_frem(inst) \
1389 x86_codegen_pre(&(inst), 2); \
1390 *(inst)++ = (unsigned char)0xd9; \
1391 *(inst)++ = (unsigned char)0xf8; \
1394 #define x86_fxch(inst,index) \
1396 x86_codegen_pre(&(inst), 2); \
1397 *(inst)++ = (unsigned char)0xd9; \
1398 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1401 #define x86_fcomi(inst,index) \
1403 x86_codegen_pre(&(inst), 2); \
1404 *(inst)++ = (unsigned char)0xdb; \
1405 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1408 #define x86_fcomip(inst,index) \
1410 x86_codegen_pre(&(inst), 2); \
1411 *(inst)++ = (unsigned char)0xdf; \
1412 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1415 #define x86_fucomi(inst,index) \
1417 x86_codegen_pre(&(inst), 2); \
1418 *(inst)++ = (unsigned char)0xdb; \
1419 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1422 #define x86_fucomip(inst,index) \
1424 x86_codegen_pre(&(inst), 2); \
1425 *(inst)++ = (unsigned char)0xdf; \
1426 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1429 #define x86_fld(inst,mem,is_double) \
1431 x86_codegen_pre(&(inst), 6); \
1432 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1433 x86_mem_emit ((inst), 0, (mem)); \
1436 #define x86_fld_membase(inst,basereg,disp,is_double) \
1438 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1439 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1440 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1443 #define x86_fld80_mem(inst,mem) \
1445 x86_codegen_pre(&(inst), 6); \
1446 *(inst)++ = (unsigned char)0xdb; \
1447 x86_mem_emit ((inst), 5, (mem)); \
1450 #define x86_fld80_membase(inst,basereg,disp) \
1452 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1453 *(inst)++ = (unsigned char)0xdb; \
1454 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1457 #define x86_fild(inst,mem,is_long) \
1459 x86_codegen_pre(&(inst), 6); \
1461 *(inst)++ = (unsigned char)0xdf; \
1462 x86_mem_emit ((inst), 5, (mem)); \
1464 *(inst)++ = (unsigned char)0xdb; \
1465 x86_mem_emit ((inst), 0, (mem)); \
1469 #define x86_fild_membase(inst,basereg,disp,is_long) \
1471 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1473 *(inst)++ = (unsigned char)0xdf; \
1474 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1476 *(inst)++ = (unsigned char)0xdb; \
1477 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1481 #define x86_fld_reg(inst,index) \
1483 x86_codegen_pre(&(inst), 2); \
1484 *(inst)++ = (unsigned char)0xd9; \
1485 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1488 #define x86_fldz(inst) \
1490 x86_codegen_pre(&(inst), 2); \
1491 *(inst)++ = (unsigned char)0xd9; \
1492 *(inst)++ = (unsigned char)0xee; \
1495 #define x86_fld1(inst) \
1497 x86_codegen_pre(&(inst), 2); \
1498 *(inst)++ = (unsigned char)0xd9; \
1499 *(inst)++ = (unsigned char)0xe8; \
1502 #define x86_fldpi(inst) \
1504 x86_codegen_pre(&(inst), 2); \
1505 *(inst)++ = (unsigned char)0xd9; \
1506 *(inst)++ = (unsigned char)0xeb; \
1509 #define x86_fst(inst,mem,is_double,pop_stack) \
1511 x86_codegen_pre(&(inst), 6); \
1512 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1513 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1516 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1518 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1519 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1520 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1523 #define x86_fst80_mem(inst,mem) \
1525 x86_codegen_pre(&(inst), 6); \
1526 *(inst)++ = (unsigned char)0xdb; \
1527 x86_mem_emit ((inst), 7, (mem)); \
1531 #define x86_fst80_membase(inst,basereg,disp) \
1533 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1534 *(inst)++ = (unsigned char)0xdb; \
1535 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1539 #define x86_fist_pop(inst,mem,is_long) \
1541 x86_codegen_pre(&(inst), 6); \
1543 *(inst)++ = (unsigned char)0xdf; \
1544 x86_mem_emit ((inst), 7, (mem)); \
1546 *(inst)++ = (unsigned char)0xdb; \
1547 x86_mem_emit ((inst), 3, (mem)); \
1551 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1553 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1555 *(inst)++ = (unsigned char)0xdf; \
1556 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1558 *(inst)++ = (unsigned char)0xdb; \
1559 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1563 #define x86_fstsw(inst) \
1565 x86_codegen_pre(&(inst), 3); \
1566 *(inst)++ = (unsigned char)0x9b; \
1567 *(inst)++ = (unsigned char)0xdf; \
1568 *(inst)++ = (unsigned char)0xe0; \
1573 * Converts content of ST(0) to integer and stores it at memory location
1574 * addressed by [basereg + disp].
1575 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1577 #define x86_fist_membase(inst,basereg,disp,is_int) \
1579 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1581 *(inst)++ = (unsigned char)0xdb; \
1582 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1584 *(inst)++ = (unsigned char)0xdf; \
1585 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1590 #define x86_push_reg(inst,reg) \
1592 *(inst)++ = (unsigned char)0x50 + (reg); \
1595 #define x86_push_regp(inst,reg) \
1597 x86_codegen_pre(&(inst), 2); \
1598 *(inst)++ = (unsigned char)0xff; \
1599 x86_regp_emit ((inst), 6, (reg)); \
1602 #define x86_push_mem(inst,mem) \
1604 x86_codegen_pre(&(inst), 6); \
1605 *(inst)++ = (unsigned char)0xff; \
1606 x86_mem_emit ((inst), 6, (mem)); \
1609 #define x86_push_membase(inst,basereg,disp) \
1611 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1612 *(inst)++ = (unsigned char)0xff; \
1613 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1616 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1618 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1619 *(inst)++ = (unsigned char)0xff; \
1620 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1623 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1625 #define x86_push_imm(inst,imm) \
1627 int _imm = (int) (imm); \
1628 if (x86_is_imm8 (_imm)) { \
1629 x86_codegen_pre(&(inst), 2); \
1630 *(inst)++ = (unsigned char)0x6A; \
1631 x86_imm_emit8 ((inst), (_imm)); \
1633 x86_codegen_pre(&(inst), 5); \
1634 *(inst)++ = (unsigned char)0x68; \
1635 x86_imm_emit32 ((inst), (_imm)); \
1639 #define x86_pop_reg(inst,reg) \
1641 *(inst)++ = (unsigned char)0x58 + (reg); \
1644 #define x86_pop_mem(inst,mem) \
1646 x86_codegen_pre(&(inst), 6); \
1647 *(inst)++ = (unsigned char)0x87; \
1648 x86_mem_emit ((inst), 0, (mem)); \
1651 #define x86_pop_membase(inst,basereg,disp) \
1653 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1654 *(inst)++ = (unsigned char)0x87; \
1655 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1658 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1659 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1660 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1661 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1663 #define x86_loop(inst,imm) \
1665 x86_codegen_pre(&(inst), 2); \
1666 *(inst)++ = (unsigned char)0xe2; \
1667 x86_imm_emit8 ((inst), (imm)); \
1670 #define x86_loope(inst,imm) \
1672 x86_codegen_pre(&(inst), 2); \
1673 *(inst)++ = (unsigned char)0xe1; \
1674 x86_imm_emit8 ((inst), (imm)); \
1677 #define x86_loopne(inst,imm) \
1679 x86_codegen_pre(&(inst), 2); \
1680 *(inst)++ = (unsigned char)0xe0; \
1681 x86_imm_emit8 ((inst), (imm)); \
1684 #define x86_jump32(inst,imm) \
1686 x86_codegen_pre(&(inst), 5); \
1687 *(inst)++ = (unsigned char)0xe9; \
1688 x86_imm_emit32 ((inst), (imm)); \
1691 #define x86_jump8(inst,imm) \
1693 x86_codegen_pre(&(inst), 2); \
1694 *(inst)++ = (unsigned char)0xeb; \
1695 x86_imm_emit8 ((inst), (imm)); \
1699 #ifdef __native_client_codegen__
1700 #define x86_jump_reg(inst,reg) do { \
1701 x86_codegen_pre(&(inst), 5); \
1702 *(inst)++ = (unsigned char)0x83; /* and */ \
1703 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
1704 *(inst)++ = (unsigned char)nacl_align_byte; \
1705 *(inst)++ = (unsigned char)0xff; \
1706 x86_reg_emit ((inst), 4, (reg)); \
1709 /* Let's hope ECX is available for these... */
1710 #define x86_jump_mem(inst,mem) do { \
1711 x86_mov_reg_mem(inst, (X86_ECX), (mem), 4); \
1712 x86_jump_reg(inst, (X86_ECX)); \
1715 #define x86_jump_membase(inst,basereg,disp) do { \
1716 x86_mov_reg_membase(inst, (X86_ECX), basereg, disp, 4); \
1717 x86_jump_reg(inst, (X86_ECX)); \
1720 /* like x86_jump_membase, but force a 32-bit displacement */
1721 #define x86_jump_membase32(inst,basereg,disp) do { \
1722 x86_codegen_pre(&(inst), 6); \
1723 *(inst)++ = (unsigned char)0x8b; \
1724 x86_address_byte ((inst), 2, X86_ECX, (basereg)); \
1725 x86_imm_emit32 ((inst), (disp)); \
1726 x86_jump_reg(inst, (X86_ECX)); \
1728 #else /* __native_client_codegen__ */
1729 #define x86_jump_reg(inst,reg) \
1731 *(inst)++ = (unsigned char)0xff; \
1732 x86_reg_emit ((inst), 4, (reg)); \
1735 #define x86_jump_mem(inst,mem) \
1737 *(inst)++ = (unsigned char)0xff; \
1738 x86_mem_emit ((inst), 4, (mem)); \
1741 #define x86_jump_membase(inst,basereg,disp) \
1743 *(inst)++ = (unsigned char)0xff; \
1744 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1746 #endif /* __native_client_codegen__ */
1748 * target is a pointer in our buffer.
1750 #define x86_jump_code(inst,target) \
1753 x86_codegen_pre(&(inst), 2); \
1754 t = (unsigned char*)(target) - (inst) - 2; \
1755 if (x86_is_imm8(t)) { \
1756 x86_jump8 ((inst), t); \
1758 x86_codegen_pre(&(inst), 5); \
1759 t = (unsigned char*)(target) - (inst) - 5; \
1760 x86_jump32 ((inst), t); \
1764 #define x86_jump_disp(inst,disp) \
1766 int t = (disp) - 2; \
1767 if (x86_is_imm8(t)) { \
1768 x86_jump8 ((inst), t); \
1771 x86_jump32 ((inst), t); \
1775 #define x86_branch8(inst,cond,imm,is_signed) \
1777 x86_codegen_pre(&(inst), 2); \
1779 *(inst)++ = x86_cc_signed_map [(cond)]; \
1781 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1782 x86_imm_emit8 ((inst), (imm)); \
1785 #define x86_branch32(inst,cond,imm,is_signed) \
1787 x86_codegen_pre(&(inst), 6); \
1788 *(inst)++ = (unsigned char)0x0f; \
1790 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1792 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1793 x86_imm_emit32 ((inst), (imm)); \
1796 #define x86_branch(inst,cond,target,is_signed) \
1799 x86_codegen_pre(&(inst), 2); \
1800 offset = (target) - (inst) - 2; \
1801 if (x86_is_imm8 ((offset))) \
1802 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1804 x86_codegen_pre(&(inst), 6); \
1805 offset = (target) - (inst) - 6; \
1806 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1810 #define x86_branch_disp(inst,cond,disp,is_signed) \
1812 int offset = (disp) - 2; \
1813 if (x86_is_imm8 ((offset))) \
1814 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1817 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1821 #define x86_set_reg(inst,cond,reg,is_signed) \
1823 g_assert (X86_IS_BYTE_REG (reg)); \
1824 x86_codegen_pre(&(inst), 3); \
1825 *(inst)++ = (unsigned char)0x0f; \
1827 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1829 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1830 x86_reg_emit ((inst), 0, (reg)); \
1833 #define x86_set_mem(inst,cond,mem,is_signed) \
1835 x86_codegen_pre(&(inst), 7); \
1836 *(inst)++ = (unsigned char)0x0f; \
1838 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1840 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1841 x86_mem_emit ((inst), 0, (mem)); \
1844 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
1846 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1847 *(inst)++ = (unsigned char)0x0f; \
1849 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1851 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1852 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1855 #define x86_call_imm_body(inst,disp) \
1857 *(inst)++ = (unsigned char)0xe8; \
1858 x86_imm_emit32 ((inst), (int)(disp)); \
1861 #define x86_call_imm(inst,disp) \
1863 x86_call_sequence_pre((inst)); \
1864 x86_call_imm_body((inst), (disp)); \
1865 x86_call_sequence_post((inst)); \
1868 #ifdef __native_client_codegen__
1869 #define x86_call_reg_internal(inst,reg) \
1871 x86_codegen_pre(&(inst), 5); \
1872 *(inst)++ = (unsigned char)0x83; /* and */ \
1873 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
1874 *(inst)++ = (unsigned char)nacl_align_byte; \
1875 *(inst)++ = (unsigned char)0xff; /* call */ \
1876 x86_reg_emit ((inst), 2, (reg)); /* reg */ \
1879 #define x86_call_reg(inst, reg) do { \
1880 x86_call_sequence_pre((inst)); \
1881 x86_call_reg_internal(inst, reg); \
1882 x86_call_sequence_post((inst)); \
1886 /* It appears that x86_call_mem() is never used, so I'm leaving it out. */
1887 #define x86_call_membase(inst,basereg,disp) do { \
1888 x86_call_sequence_pre((inst)); \
1889 /* x86_mov_reg_membase() inlined so its fixed size */ \
1890 *(inst)++ = (unsigned char)0x8b; \
1891 x86_address_byte ((inst), 2, (X86_ECX), (basereg)); \
1892 x86_imm_emit32 ((inst), (disp)); \
1893 x86_call_reg_internal(inst, X86_ECX); \
1894 x86_call_sequence_post((inst)); \
1896 #else /* __native_client_codegen__ */
1897 #define x86_call_reg(inst,reg) \
1899 *(inst)++ = (unsigned char)0xff; \
1900 x86_reg_emit ((inst), 2, (reg)); \
1903 #define x86_call_mem(inst,mem) \
1905 *(inst)++ = (unsigned char)0xff; \
1906 x86_mem_emit ((inst), 2, (mem)); \
1909 #define x86_call_membase(inst,basereg,disp) \
1911 *(inst)++ = (unsigned char)0xff; \
1912 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1914 #endif /* __native_client_codegen__ */
1917 #ifdef __native_client_codegen__
1919 #define x86_call_code(inst,target) \
1922 guint8* _aligned_start; \
1923 x86_call_sequence_pre_val ((inst)); \
1924 _x86_offset = (unsigned char*)(target) - (inst); \
1926 x86_call_imm_body ((inst), _x86_offset); \
1927 _aligned_start = x86_call_sequence_post_val ((inst)); \
1928 _x86_offset = (unsigned char*)(target) - (_aligned_start); \
1930 x86_call_imm_body ((_aligned_start), _x86_offset); \
1933 #define SIZE_OF_RET 6
1934 #define x86_ret(inst) do { \
1935 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
1936 x86_codegen_pre(&(inst), 5); \
1937 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
1938 *(inst)++ = (unsigned char)0xe1; \
1939 *(inst)++ = (unsigned char)nacl_align_byte; \
1940 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
1941 *(inst)++ = (unsigned char)0xe1; \
1944 /* pop return address */
1945 /* pop imm bytes from stack */
1947 #define x86_ret_imm(inst,imm) do { \
1948 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
1949 x86_alu_reg_imm ((inst), X86_ADD, X86_ESP, imm); \
1950 x86_codegen_pre(&(inst), 5); \
1951 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
1952 *(inst)++ = (unsigned char)0xe1; \
1953 *(inst)++ = (unsigned char)nacl_align_byte; \
1954 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
1955 *(inst)++ = (unsigned char)0xe1; \
1957 #else /* __native_client_codegen__ */
1959 #define x86_call_code(inst,target) \
1962 _x86_offset = (unsigned char*)(target) - (inst); \
1964 x86_call_imm_body ((inst), _x86_offset); \
1967 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
1969 #define x86_ret_imm(inst,imm) \
1974 x86_codegen_pre(&(inst), 3); \
1975 *(inst)++ = (unsigned char)0xc2; \
1976 x86_imm_emit16 ((inst), (imm)); \
1979 #endif /* __native_client_codegen__ */
1981 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
1983 x86_codegen_pre(&(inst), 3); \
1984 *(inst)++ = (unsigned char) 0x0f; \
1986 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1988 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1989 x86_reg_emit ((inst), (dreg), (reg)); \
1992 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
1994 x86_codegen_pre(&(inst), 7); \
1995 *(inst)++ = (unsigned char) 0x0f; \
1997 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1999 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2000 x86_mem_emit ((inst), (reg), (mem)); \
2003 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
2005 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2006 *(inst)++ = (unsigned char) 0x0f; \
2008 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2010 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2011 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2014 #define x86_enter(inst,framesize) \
2016 x86_codegen_pre(&(inst), 4); \
2017 *(inst)++ = (unsigned char)0xc8; \
2018 x86_imm_emit16 ((inst), (framesize)); \
2022 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
2023 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
2025 #define x86_fsin(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
2026 #define x86_fcos(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
2027 #define x86_fabs(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
2028 #define x86_ftst(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
2029 #define x86_fxam(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
2030 #define x86_fpatan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
2031 #define x86_fprem(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
2032 #define x86_fprem1(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
2033 #define x86_frndint(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
2034 #define x86_fsqrt(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
2035 #define x86_fptan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
2037 #define x86_padding(inst,size) \
2040 case 1: x86_nop ((inst)); break; \
2041 case 2: *(inst)++ = 0x8b; \
2042 *(inst)++ = 0xc0; break; \
2043 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
2044 *(inst)++ = 0x00; break; \
2045 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2046 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2048 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2049 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2050 x86_nop ((inst)); break; \
2051 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
2052 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2053 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2055 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
2056 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2057 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2058 *(inst)++ = 0x00; break; \
2059 default: assert (0); \
2063 #ifdef __native_client_codegen__
2065 #define kNaClLengthOfCallReg 5
2066 #define kNaClLengthOfCallImm 5
2067 #define kNaClLengthOfCallMembase (kNaClLengthOfCallReg + 6)
2069 #endif /* __native_client_codegen__ */
2071 #define x86_prolog(inst,frame_size,reg_mask) \
2073 unsigned i, m = 1; \
2074 x86_enter ((inst), (frame_size)); \
2075 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
2076 if ((reg_mask) & m) \
2077 x86_push_reg ((inst), i); \
2081 #define x86_epilog(inst,reg_mask) \
2083 unsigned i, m = 1 << X86_EDI; \
2084 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
2085 if ((reg_mask) & m) \
2086 x86_pop_reg ((inst), i); \
2088 x86_leave ((inst)); \
2094 X86_SSE_SQRT = 0x51,
2095 X86_SSE_RSQRT = 0x52,
2103 X86_SSE_COMP = 0xC2,
2105 X86_SSE_ANDN = 0x55,
2108 X86_SSE_UNPCKL = 0x14,
2109 X86_SSE_UNPCKH = 0x15,
2111 X86_SSE_ADDSUB = 0xD0,
2112 X86_SSE_HADD = 0x7C,
2113 X86_SSE_HSUB = 0x7D,
2114 X86_SSE_MOVSHDUP = 0x16,
2115 X86_SSE_MOVSLDUP = 0x12,
2116 X86_SSE_MOVDDUP = 0x12,
2118 X86_SSE_PAND = 0xDB,
2120 X86_SSE_PXOR = 0xEF,
2122 X86_SSE_PADDB = 0xFC,
2123 X86_SSE_PADDW = 0xFD,
2124 X86_SSE_PADDD = 0xFE,
2125 X86_SSE_PADDQ = 0xD4,
2127 X86_SSE_PSUBB = 0xF8,
2128 X86_SSE_PSUBW = 0xF9,
2129 X86_SSE_PSUBD = 0xFA,
2130 X86_SSE_PSUBQ = 0xFB,
2132 X86_SSE_PMAXSB = 0x3C, /*sse41*/
2133 X86_SSE_PMAXSW = 0xEE,
2134 X86_SSE_PMAXSD = 0x3D, /*sse41*/
2136 X86_SSE_PMAXUB = 0xDE,
2137 X86_SSE_PMAXUW = 0x3E, /*sse41*/
2138 X86_SSE_PMAXUD = 0x3F, /*sse41*/
2140 X86_SSE_PMINSB = 0x38, /*sse41*/
2141 X86_SSE_PMINSW = 0xEA,
2142 X86_SSE_PMINSD = 0x39,/*sse41*/
2144 X86_SSE_PMINUB = 0xDA,
2145 X86_SSE_PMINUW = 0x3A, /*sse41*/
2146 X86_SSE_PMINUD = 0x3B, /*sse41*/
2148 X86_SSE_PAVGB = 0xE0,
2149 X86_SSE_PAVGW = 0xE3,
2151 X86_SSE_PCMPEQB = 0x74,
2152 X86_SSE_PCMPEQW = 0x75,
2153 X86_SSE_PCMPEQD = 0x76,
2154 X86_SSE_PCMPEQQ = 0x29, /*sse41*/
2156 X86_SSE_PCMPGTB = 0x64,
2157 X86_SSE_PCMPGTW = 0x65,
2158 X86_SSE_PCMPGTD = 0x66,
2159 X86_SSE_PCMPGTQ = 0x37, /*sse42*/
2161 X86_SSE_PSADBW = 0xf6,
2163 X86_SSE_PSHUFD = 0x70,
2165 X86_SSE_PUNPCKLBW = 0x60,
2166 X86_SSE_PUNPCKLWD = 0x61,
2167 X86_SSE_PUNPCKLDQ = 0x62,
2168 X86_SSE_PUNPCKLQDQ = 0x6C,
2170 X86_SSE_PUNPCKHBW = 0x68,
2171 X86_SSE_PUNPCKHWD = 0x69,
2172 X86_SSE_PUNPCKHDQ = 0x6A,
2173 X86_SSE_PUNPCKHQDQ = 0x6D,
2175 X86_SSE_PACKSSWB = 0x63,
2176 X86_SSE_PACKSSDW = 0x6B,
2178 X86_SSE_PACKUSWB = 0x67,
2179 X86_SSE_PACKUSDW = 0x2B,/*sse41*/
2181 X86_SSE_PADDUSB = 0xDC,
2182 X86_SSE_PADDUSW = 0xDD,
2183 X86_SSE_PSUBUSB = 0xD8,
2184 X86_SSE_PSUBUSW = 0xD9,
2186 X86_SSE_PADDSB = 0xEC,
2187 X86_SSE_PADDSW = 0xED,
2188 X86_SSE_PSUBSB = 0xE8,
2189 X86_SSE_PSUBSW = 0xE9,
2191 X86_SSE_PMULLW = 0xD5,
2192 X86_SSE_PMULLD = 0x40,/*sse41*/
2193 X86_SSE_PMULHUW = 0xE4,
2194 X86_SSE_PMULHW = 0xE5,
2195 X86_SSE_PMULUDQ = 0xF4,
2197 X86_SSE_PMOVMSKB = 0xD7,
2199 X86_SSE_PSHIFTW = 0x71,
2200 X86_SSE_PSHIFTD = 0x72,
2201 X86_SSE_PSHIFTQ = 0x73,
2206 X86_SSE_PSRLW_REG = 0xD1,
2207 X86_SSE_PSRAW_REG = 0xE1,
2208 X86_SSE_PSLLW_REG = 0xF1,
2210 X86_SSE_PSRLD_REG = 0xD2,
2211 X86_SSE_PSRAD_REG = 0xE2,
2212 X86_SSE_PSLLD_REG = 0xF2,
2214 X86_SSE_PSRLQ_REG = 0xD3,
2215 X86_SSE_PSLLQ_REG = 0xF3,
2217 X86_SSE_PREFETCH = 0x18,
2218 X86_SSE_MOVNTPS = 0x2B,
2219 X86_SSE_MOVHPD_REG_MEMBASE = 0x16,
2220 X86_SSE_MOVHPD_MEMBASE_REG = 0x17,
2222 X86_SSE_MOVSD_REG_MEMBASE = 0x10,
2223 X86_SSE_MOVSD_MEMBASE_REG = 0x11,
2225 X86_SSE_PINSRB = 0x20,/*sse41*/
2226 X86_SSE_PINSRW = 0xC4,
2227 X86_SSE_PINSRD = 0x22,/*sse41*/
2229 X86_SSE_PEXTRB = 0x14,/*sse41*/
2230 X86_SSE_PEXTRW = 0xC5,
2231 X86_SSE_PEXTRD = 0x16,/*sse41*/
2235 /* minimal SSE* support */
2236 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
2238 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2239 *(inst)++ = (unsigned char)0xf2; \
2240 *(inst)++ = (unsigned char)0x0f; \
2241 *(inst)++ = (unsigned char)0x10; \
2242 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
2245 #define x86_cvttsd2si(inst,dreg,reg) \
2247 x86_codegen_pre(&(inst), 4); \
2248 *(inst)++ = (unsigned char)0xf2; \
2249 *(inst)++ = (unsigned char)0x0f; \
2250 *(inst)++ = (unsigned char)0x2c; \
2251 x86_reg_emit ((inst), (dreg), (reg)); \
2254 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
2256 x86_codegen_pre(&(inst), 3); \
2257 *(inst)++ = (unsigned char)0x0F; \
2258 *(inst)++ = (unsigned char)(opc); \
2259 x86_reg_emit ((inst), (dreg), (reg)); \
2262 #define x86_sse_alu_reg_membase(inst,opc,sreg,basereg,disp) \
2264 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2265 *(inst)++ = (unsigned char)0x0f; \
2266 *(inst)++ = (unsigned char)(opc); \
2267 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2270 #define x86_sse_alu_membase_reg(inst,opc,basereg,disp,reg) \
2272 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2273 *(inst)++ = (unsigned char)0x0F; \
2274 *(inst)++ = (unsigned char)(opc); \
2275 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2279 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
2281 x86_codegen_pre(&(inst), 4); \
2282 *(inst)++ = (unsigned char)0x66; \
2283 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2286 #define x86_sse_alu_pd_membase_reg(inst,opc,basereg,disp,reg) \
2288 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2289 *(inst)++ = (unsigned char)0x66; \
2290 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2293 #define x86_sse_alu_pd_reg_membase(inst,opc,dreg,basereg,disp) \
2295 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2296 *(inst)++ = (unsigned char)0x66; \
2297 x86_sse_alu_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2300 #define x86_sse_alu_pd_reg_reg_imm(inst,opc,dreg,reg,imm) \
2302 x86_codegen_pre(&(inst), 5); \
2303 x86_sse_alu_pd_reg_reg ((inst), (opc), (dreg), (reg)); \
2304 *(inst)++ = (unsigned char)(imm); \
2307 #define x86_sse_alu_pd_reg_membase_imm(inst,opc,dreg,basereg,disp,imm) \
2309 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
2310 x86_sse_alu_pd_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2311 *(inst)++ = (unsigned char)(imm); \
2315 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
2317 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2320 #define x86_sse_alu_ps_reg_reg_imm(inst,opc,dreg,reg, imm) \
2322 x86_codegen_pre(&(inst), 4); \
2323 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2324 *(inst)++ = (unsigned char)imm; \
2328 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
2330 x86_codegen_pre(&(inst), 4); \
2331 *(inst)++ = (unsigned char)0xF2; \
2332 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2335 #define x86_sse_alu_sd_membase_reg(inst,opc,basereg,disp,reg) \
2337 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2338 *(inst)++ = (unsigned char)0xF2; \
2339 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2343 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
2345 x86_codegen_pre(&(inst), 4); \
2346 *(inst)++ = (unsigned char)0xF3; \
2347 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2350 #define x86_sse_alu_ss_membase_reg(inst,opc,basereg,disp,reg) \
2352 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2353 *(inst)++ = (unsigned char)0xF3; \
2354 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2359 #define x86_sse_alu_sse41_reg_reg(inst,opc,dreg,reg) \
2361 x86_codegen_pre(&(inst), 5); \
2362 *(inst)++ = (unsigned char)0x66; \
2363 *(inst)++ = (unsigned char)0x0F; \
2364 *(inst)++ = (unsigned char)0x38; \
2365 *(inst)++ = (unsigned char)(opc); \
2366 x86_reg_emit ((inst), (dreg), (reg)); \
2369 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
2371 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2372 *(inst)++ = (unsigned char)0x0f; \
2373 *(inst)++ = (unsigned char)0x10; \
2374 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2377 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
2379 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2380 *(inst)++ = (unsigned char)0x0f; \
2381 *(inst)++ = (unsigned char)0x11; \
2382 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2385 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
2387 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2388 *(inst)++ = (unsigned char)0x0f; \
2389 *(inst)++ = (unsigned char)0x28; \
2390 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2393 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
2395 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2396 *(inst)++ = (unsigned char)0x0f; \
2397 *(inst)++ = (unsigned char)0x29; \
2398 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2401 #define x86_movaps_reg_reg(inst,dreg,sreg) \
2403 x86_codegen_pre(&(inst), 3); \
2404 *(inst)++ = (unsigned char)0x0f; \
2405 *(inst)++ = (unsigned char)0x28; \
2406 x86_reg_emit ((inst), (dreg), (sreg)); \
2410 #define x86_movd_reg_xreg(inst,dreg,sreg) \
2412 x86_codegen_pre(&(inst), 4); \
2413 *(inst)++ = (unsigned char)0x66; \
2414 *(inst)++ = (unsigned char)0x0f; \
2415 *(inst)++ = (unsigned char)0x7e; \
2416 x86_reg_emit ((inst), (sreg), (dreg)); \
2419 #define x86_movd_xreg_reg(inst,dreg,sreg) \
2421 x86_codegen_pre(&(inst), 4); \
2422 *(inst)++ = (unsigned char)0x66; \
2423 *(inst)++ = (unsigned char)0x0f; \
2424 *(inst)++ = (unsigned char)0x6e; \
2425 x86_reg_emit ((inst), (dreg), (sreg)); \
2428 #define x86_movd_xreg_membase(inst,sreg,basereg,disp) \
2430 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2431 *(inst)++ = (unsigned char)0x66; \
2432 *(inst)++ = (unsigned char)0x0f; \
2433 *(inst)++ = (unsigned char)0x6e; \
2434 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2437 #define x86_pshufw_reg_reg(inst,dreg,sreg,mask,high_words) \
2439 x86_codegen_pre(&(inst), 5); \
2440 *(inst)++ = (unsigned char)(high_words) ? 0xF3 : 0xF2; \
2441 *(inst)++ = (unsigned char)0x0f; \
2442 *(inst)++ = (unsigned char)0x70; \
2443 x86_reg_emit ((inst), (dreg), (sreg)); \
2444 *(inst)++ = (unsigned char)mask; \
2447 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
2449 x86_codegen_pre(&(inst), 5); \
2450 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
2451 x86_imm_emit8 ((inst), (imm)); \
2454 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
2456 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \