2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 #ifdef __native_client_codegen__
20 extern gint8 nacl_align_byte;
21 #endif /* __native_client_codegen__ */
24 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
25 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do { mono_nacl_align_inst(inst_ptr_ptr, inst_len); } while (0)
26 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
27 #define x86_call_sequence_post_val(inst) \
28 (mono_nacl_align_call(&_code_start, &(inst)), _code_start);
29 #define x86_call_sequence_pre(inst) x86_call_sequence_pre_val((inst))
30 #define x86_call_sequence_post(inst) x86_call_sequence_post_val((inst))
32 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do {} while (0)
33 /* Two variants are needed to avoid warnings */
34 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
35 #define x86_call_sequence_post_val(inst) _code_start
36 #define x86_call_sequence_pre(inst)
37 #define x86_call_sequence_post(inst)
38 #endif /* __native_client_codegen__ */
42 // x86 register numbers
69 // opcodes for alu instructions
83 // opcodes for shift instructions
98 // opcodes for floating-point instructions
112 // integer conditions codes
115 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
116 X86_CC_NE = 1, X86_CC_NZ = 1,
117 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
118 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
119 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
120 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
121 X86_CC_LZ = 6, X86_CC_S = 6,
122 X86_CC_GEZ = 7, X86_CC_NS = 7,
123 X86_CC_P = 8, X86_CC_PE = 8,
124 X86_CC_NP = 9, X86_CC_PO = 9,
136 X86_FP_CC_MASK = 0x4500
139 /* FP control word */
141 X86_FPCW_INVOPEX_MASK = 0x1,
142 X86_FPCW_DENOPEX_MASK = 0x2,
143 X86_FPCW_ZERODIV_MASK = 0x4,
144 X86_FPCW_OVFEX_MASK = 0x8,
145 X86_FPCW_UNDFEX_MASK = 0x10,
146 X86_FPCW_PRECEX_MASK = 0x20,
147 X86_FPCW_PRECC_MASK = 0x300,
148 X86_FPCW_ROUNDC_MASK = 0xc00,
150 /* values for precision control */
151 X86_FPCW_PREC_SINGLE = 0,
152 X86_FPCW_PREC_DOUBLE = 0x200,
153 X86_FPCW_PREC_EXTENDED = 0x300,
155 /* values for rounding control */
156 X86_FPCW_ROUND_NEAREST = 0,
157 X86_FPCW_ROUND_DOWN = 0x400,
158 X86_FPCW_ROUND_UP = 0x800,
159 X86_FPCW_ROUND_TOZERO = 0xc00
166 X86_LOCK_PREFIX = 0xF0,
167 X86_REPNZ_PREFIX = 0xF2,
168 X86_REPZ_PREFIX = 0xF3,
169 X86_REP_PREFIX = 0xF3,
170 X86_CS_PREFIX = 0x2E,
171 X86_SS_PREFIX = 0x36,
172 X86_DS_PREFIX = 0x3E,
173 X86_ES_PREFIX = 0x26,
174 X86_FS_PREFIX = 0x64,
175 X86_GS_PREFIX = 0x65,
176 X86_UNLIKELY_PREFIX = 0x2E,
177 X86_LIKELY_PREFIX = 0x3E,
178 X86_OPERAND_PREFIX = 0x66,
179 X86_ADDRESS_PREFIX = 0x67
182 static const unsigned char
183 x86_cc_unsigned_map [X86_NCC] = {
198 static const unsigned char
199 x86_cc_signed_map [X86_NCC] = {
219 #define X86_NOBASEREG (-1)
222 // bitvector mask for callee-saved registers
224 #define X86_ESI_MASK (1<<X86_ESI)
225 #define X86_EDI_MASK (1<<X86_EDI)
226 #define X86_EBX_MASK (1<<X86_EBX)
227 #define X86_EBP_MASK (1<<X86_EBP)
229 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
230 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
231 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
233 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
234 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
236 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
241 // +--------------------------------+
242 // | in_arg[0] = var[0] |
243 // | in_arg[1] = var[1] |
245 // | in_arg[n_arg-1] = var[n_arg-1] |
246 // +--------------------------------+
248 // +--------------------------------+
249 // | saved EBP | <-- frame pointer (EBP)
250 // +--------------------------------+
252 // +--------------------------------+
254 // | var[n_arg+1] | local variables area
257 // +--------------------------------+
260 // | spill area | area for spilling mimic stack
262 // +--------------------------------|
264 // | ebp [ESP_Frame only] |
265 // | esi | 0..3 callee-saved regs
266 // | edi | <-- stack pointer (ESP)
267 // +--------------------------------+
269 // | stk1 | operand stack area/
270 // | . . . | out args
272 // +--------------------------------|
279 * useful building blocks
281 #define x86_modrm_mod(modrm) ((modrm) >> 6)
282 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
283 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
285 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
286 #define x86_imm_emit32(inst,imm) \
288 x86_imm_buf imb; imb.val = (int) (imm); \
289 *(inst)++ = imb.b [0]; \
290 *(inst)++ = imb.b [1]; \
291 *(inst)++ = imb.b [2]; \
292 *(inst)++ = imb.b [3]; \
294 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
295 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
296 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
297 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
299 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
300 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
301 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
302 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
304 #define kMaxMembaseEmitPadding 6
306 #define x86_membase_emit_body(inst,r,basereg,disp) do {\
307 if ((basereg) == X86_ESP) { \
309 x86_address_byte ((inst), 0, (r), X86_ESP); \
310 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
311 } else if (x86_is_imm8((disp))) { \
312 x86_address_byte ((inst), 1, (r), X86_ESP); \
313 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
314 x86_imm_emit8 ((inst), (disp)); \
316 x86_address_byte ((inst), 2, (r), X86_ESP); \
317 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
318 x86_imm_emit32 ((inst), (disp)); \
322 if ((disp) == 0 && (basereg) != X86_EBP) { \
323 x86_address_byte ((inst), 0, (r), (basereg)); \
326 if (x86_is_imm8((disp))) { \
327 x86_address_byte ((inst), 1, (r), (basereg)); \
328 x86_imm_emit8 ((inst), (disp)); \
330 x86_address_byte ((inst), 2, (r), (basereg)); \
331 x86_imm_emit32 ((inst), (disp)); \
335 #if defined(__native_client_codegen__) && defined(TARGET_AMD64)
336 #define x86_membase_emit(inst,r,basereg,disp) \
338 amd64_nacl_membase_handler(&(inst), (basereg), (disp), (r)) ; \
340 #else /* __default_codegen__ || 32-bit NaCl codegen */
341 #define x86_membase_emit(inst,r,basereg,disp) \
343 x86_membase_emit_body((inst),(r),(basereg),(disp)); \
347 #define kMaxMemindexEmitPadding 6
349 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
351 if ((basereg) == X86_NOBASEREG) { \
352 x86_address_byte ((inst), 0, (r), 4); \
353 x86_address_byte ((inst), (shift), (indexreg), 5); \
354 x86_imm_emit32 ((inst), (disp)); \
355 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
356 x86_address_byte ((inst), 0, (r), 4); \
357 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
358 } else if (x86_is_imm8((disp))) { \
359 x86_address_byte ((inst), 1, (r), 4); \
360 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
361 x86_imm_emit8 ((inst), (disp)); \
363 x86_address_byte ((inst), 2, (r), 4); \
364 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
365 x86_imm_emit32 ((inst), (disp)); \
370 * target is the position in the code where to jump to:
372 * .. output loop code...
373 * x86_mov_reg_imm (code, X86_EAX, 0);
375 * x86_loop (code, -1);
379 * x86_patch (loop, target);
381 * ins should point at the start of the instruction that encodes a target.
382 * the instruction is inspected for validity and the correct displacement
385 #define x86_do_patch(ins,target) \
387 unsigned char* pos = (ins) + 1; \
388 int disp, size = 0; \
389 switch (*(unsigned char*)(ins)) { \
390 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
391 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
392 ++size; ++pos; break; /* prefix for 32-bit disp */ \
393 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
394 case 0xeb: /* jump8 */ \
395 /* conditional jump opcodes */ \
396 case 0x70: case 0x71: case 0x72: case 0x73: \
397 case 0x74: case 0x75: case 0x76: case 0x77: \
398 case 0x78: case 0x79: case 0x7a: case 0x7b: \
399 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
401 default: assert (0); \
403 disp = (target) - pos; \
404 if (size) x86_imm_emit32 (pos, disp - 4); \
405 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
409 #if defined( __native_client_codegen__ ) && defined(TARGET_X86)
411 #define x86_skip_nops(inst) \
416 if (inst[0] == 0x90) { \
420 if (inst[0] == 0x8b && inst[1] == 0xc0) { \
424 if (inst[0] == 0x8d && inst[1] == 0x6d \
425 && inst[2] == 0x00) { \
429 if (inst[0] == 0x8d && inst[1] == 0x64 \
430 && inst[2] == 0x24 && inst[3] == 0x00) { \
434 /* skip inst+=5 case because it's the 4-byte + 1-byte case */ \
435 if (inst[0] == 0x8d && inst[1] == 0xad \
436 && inst[2] == 0x00 && inst[3] == 0x00 \
437 && inst[4] == 0x00 && inst[5] == 0x00) { \
441 if (inst[0] == 0x8d && inst[1] == 0xa4 \
442 && inst[2] == 0x24 && inst[3] == 0x00 \
443 && inst[4] == 0x00 && inst[5] == 0x00 \
444 && inst[6] == 0x00 ) { \
448 } while ( in_nop ); \
451 #if defined(__native_client__)
452 #define x86_patch(ins,target) \
454 unsigned char* inst = (ins); \
455 guint8* new_target = nacl_modify_patch_target((target)); \
456 x86_skip_nops((inst)); \
457 x86_do_patch((inst), new_target); \
459 #else /* __native_client__ */
460 #define x86_patch(ins,target) \
462 unsigned char* inst = (ins); \
463 guint8* new_target = (target); \
464 x86_skip_nops((inst)); \
465 x86_do_patch((inst), new_target); \
467 #endif /* __native_client__ */
470 #define x86_patch(ins,target) do { x86_do_patch((ins), (target)); } while (0)
471 #endif /* __native_client_codegen__ */
473 #ifdef __native_client_codegen__
474 /* The breakpoint instruction is illegal in Native Client, although the HALT */
475 /* instruction is allowed. The breakpoint is used several places in mini-x86.c */
476 /* and exceptions-x86.c. */
477 #define x86_breakpoint(inst) \
482 #define x86_breakpoint(inst) \
488 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
489 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
490 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
491 #define x86_stosd(inst) x86_stosl((inst))
492 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
493 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
494 #define x86_movsd(inst) x86_movsl((inst))
496 #if defined(__default_codegen__)
497 #define x86_prefix(inst,p) \
499 *(inst)++ =(unsigned char) (p); \
501 #elif defined(__native_client_codegen__)
502 #if defined(TARGET_X86)
503 /* kNaClAlignment - 1 is the max value we can pass into x86_codegen_pre. */
504 /* This keeps us from having to call x86_codegen_pre with specific */
505 /* knowledge of the size of the instruction that follows it, and */
506 /* localizes the alignment requirement to this spot. */
507 #define x86_prefix(inst,p) \
509 x86_codegen_pre(&(inst), kNaClAlignment - 1); \
510 *(inst)++ =(unsigned char) (p); \
512 #elif defined(TARGET_AMD64)
513 /* We need to tag any prefixes so we can perform proper membase sandboxing */
514 /* See: mini-amd64.c:amd64_nacl_membase_handler for verbose details */
515 #define x86_prefix(inst,p) \
517 amd64_nacl_tag_legacy_prefix((inst)); \
518 *(inst)++ =(unsigned char) (p); \
521 #endif /* TARGET_AMD64 */
523 #endif /* __native_client_codegen__ */
525 #define x86_rdtsc(inst) \
527 x86_codegen_pre(&(inst), 2); \
532 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
534 x86_codegen_pre(&(inst), 3); \
535 *(inst)++ = (unsigned char)0x0f; \
536 *(inst)++ = (unsigned char)0xb1; \
537 x86_reg_emit ((inst), (reg), (dreg)); \
540 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
542 x86_codegen_pre(&(inst), 7); \
543 *(inst)++ = (unsigned char)0x0f; \
544 *(inst)++ = (unsigned char)0xb1; \
545 x86_mem_emit ((inst), (reg), (mem)); \
548 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
550 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
551 *(inst)++ = (unsigned char)0x0f; \
552 *(inst)++ = (unsigned char)0xb1; \
553 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
556 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
558 x86_codegen_pre(&(inst), 2); \
560 *(inst)++ = (unsigned char)0x86; \
562 *(inst)++ = (unsigned char)0x87; \
563 x86_reg_emit ((inst), (reg), (dreg)); \
566 #define x86_xchg_mem_reg(inst,mem,reg,size) \
568 x86_codegen_pre(&(inst), 6); \
570 *(inst)++ = (unsigned char)0x86; \
572 *(inst)++ = (unsigned char)0x87; \
573 x86_mem_emit ((inst), (reg), (mem)); \
576 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
578 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
580 *(inst)++ = (unsigned char)0x86; \
582 *(inst)++ = (unsigned char)0x87; \
583 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
586 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
588 x86_codegen_pre(&(inst), 3); \
589 *(inst)++ = (unsigned char)0x0F; \
591 *(inst)++ = (unsigned char)0xC0; \
593 *(inst)++ = (unsigned char)0xC1; \
594 x86_reg_emit ((inst), (reg), (dreg)); \
597 #define x86_xadd_mem_reg(inst,mem,reg,size) \
599 x86_codegen_pre(&(inst), 7); \
600 *(inst)++ = (unsigned char)0x0F; \
602 *(inst)++ = (unsigned char)0xC0; \
604 *(inst)++ = (unsigned char)0xC1; \
605 x86_mem_emit ((inst), (reg), (mem)); \
608 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
610 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
611 *(inst)++ = (unsigned char)0x0F; \
613 *(inst)++ = (unsigned char)0xC0; \
615 *(inst)++ = (unsigned char)0xC1; \
616 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
619 #define x86_inc_mem(inst,mem) \
621 x86_codegen_pre(&(inst), 6); \
622 *(inst)++ = (unsigned char)0xff; \
623 x86_mem_emit ((inst), 0, (mem)); \
626 #define x86_inc_membase(inst,basereg,disp) \
628 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
629 *(inst)++ = (unsigned char)0xff; \
630 x86_membase_emit ((inst), 0, (basereg), (disp)); \
633 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
635 #define x86_dec_mem(inst,mem) \
637 x86_codegen_pre(&(inst), 6); \
638 *(inst)++ = (unsigned char)0xff; \
639 x86_mem_emit ((inst), 1, (mem)); \
642 #define x86_dec_membase(inst,basereg,disp) \
644 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
645 *(inst)++ = (unsigned char)0xff; \
646 x86_membase_emit ((inst), 1, (basereg), (disp)); \
649 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
651 #define x86_not_mem(inst,mem) \
653 x86_codegen_pre(&(inst), 6); \
654 *(inst)++ = (unsigned char)0xf7; \
655 x86_mem_emit ((inst), 2, (mem)); \
658 #define x86_not_membase(inst,basereg,disp) \
660 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
661 *(inst)++ = (unsigned char)0xf7; \
662 x86_membase_emit ((inst), 2, (basereg), (disp)); \
665 #define x86_not_reg(inst,reg) \
667 x86_codegen_pre(&(inst), 2); \
668 *(inst)++ = (unsigned char)0xf7; \
669 x86_reg_emit ((inst), 2, (reg)); \
672 #define x86_neg_mem(inst,mem) \
674 x86_codegen_pre(&(inst), 6); \
675 *(inst)++ = (unsigned char)0xf7; \
676 x86_mem_emit ((inst), 3, (mem)); \
679 #define x86_neg_membase(inst,basereg,disp) \
681 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
682 *(inst)++ = (unsigned char)0xf7; \
683 x86_membase_emit ((inst), 3, (basereg), (disp)); \
686 #define x86_neg_reg(inst,reg) \
688 x86_codegen_pre(&(inst), 2); \
689 *(inst)++ = (unsigned char)0xf7; \
690 x86_reg_emit ((inst), 3, (reg)); \
693 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
695 #define x86_alu_reg_imm(inst,opc,reg,imm) \
697 if ((reg) == X86_EAX) { \
698 x86_codegen_pre(&(inst), 5); \
699 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
700 x86_imm_emit32 ((inst), (imm)); \
703 if (x86_is_imm8((imm))) { \
704 x86_codegen_pre(&(inst), 3); \
705 *(inst)++ = (unsigned char)0x83; \
706 x86_reg_emit ((inst), (opc), (reg)); \
707 x86_imm_emit8 ((inst), (imm)); \
709 x86_codegen_pre(&(inst), 6); \
710 *(inst)++ = (unsigned char)0x81; \
711 x86_reg_emit ((inst), (opc), (reg)); \
712 x86_imm_emit32 ((inst), (imm)); \
716 #define x86_alu_mem_imm(inst,opc,mem,imm) \
718 if (x86_is_imm8((imm))) { \
719 x86_codegen_pre(&(inst), 7); \
720 *(inst)++ = (unsigned char)0x83; \
721 x86_mem_emit ((inst), (opc), (mem)); \
722 x86_imm_emit8 ((inst), (imm)); \
724 x86_codegen_pre(&(inst), 10); \
725 *(inst)++ = (unsigned char)0x81; \
726 x86_mem_emit ((inst), (opc), (mem)); \
727 x86_imm_emit32 ((inst), (imm)); \
731 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
733 if (x86_is_imm8((imm))) { \
734 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
735 *(inst)++ = (unsigned char)0x83; \
736 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
737 x86_imm_emit8 ((inst), (imm)); \
739 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
740 *(inst)++ = (unsigned char)0x81; \
741 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
742 x86_imm_emit32 ((inst), (imm)); \
746 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
748 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
749 *(inst)++ = (unsigned char)0x80; \
750 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
751 x86_imm_emit8 ((inst), (imm)); \
754 #define x86_alu_mem_reg(inst,opc,mem,reg) \
756 x86_codegen_pre(&(inst), 6); \
757 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
758 x86_mem_emit ((inst), (reg), (mem)); \
761 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
763 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
764 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
765 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
768 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
770 x86_codegen_pre(&(inst), 2); \
771 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
772 x86_reg_emit ((inst), (dreg), (reg)); \
776 * @x86_alu_reg8_reg8:
777 * Supports ALU operations between two 8-bit registers.
778 * dreg := dreg opc reg
779 * X86_Reg_No enum is used to specify the registers.
780 * Additionally is_*_h flags are used to specify what part
781 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
782 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
784 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
786 x86_codegen_pre(&(inst), 2); \
787 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
788 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
791 #define x86_alu_reg_mem(inst,opc,reg,mem) \
793 x86_codegen_pre(&(inst), 6); \
794 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
795 x86_mem_emit ((inst), (reg), (mem)); \
798 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
800 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
801 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
802 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
805 #define x86_test_reg_imm(inst,reg,imm) \
807 x86_codegen_pre(&(inst), 6); \
808 if ((reg) == X86_EAX) { \
809 *(inst)++ = (unsigned char)0xa9; \
811 *(inst)++ = (unsigned char)0xf7; \
812 x86_reg_emit ((inst), 0, (reg)); \
814 x86_imm_emit32 ((inst), (imm)); \
817 #define x86_test_mem_imm8(inst,mem,imm) \
819 x86_codegen_pre(&(inst), 7); \
820 *(inst)++ = (unsigned char)0xf6; \
821 x86_mem_emit ((inst), 0, (mem)); \
822 x86_imm_emit8 ((inst), (imm)); \
825 #define x86_test_mem_imm(inst,mem,imm) \
827 x86_codegen_pre(&(inst), 10); \
828 *(inst)++ = (unsigned char)0xf7; \
829 x86_mem_emit ((inst), 0, (mem)); \
830 x86_imm_emit32 ((inst), (imm)); \
833 #define x86_test_membase_imm(inst,basereg,disp,imm) \
835 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
836 *(inst)++ = (unsigned char)0xf7; \
837 x86_membase_emit ((inst), 0, (basereg), (disp)); \
838 x86_imm_emit32 ((inst), (imm)); \
841 #define x86_test_reg_reg(inst,dreg,reg) \
843 x86_codegen_pre(&(inst), 2); \
844 *(inst)++ = (unsigned char)0x85; \
845 x86_reg_emit ((inst), (reg), (dreg)); \
848 #define x86_test_mem_reg(inst,mem,reg) \
850 x86_codegen_pre(&(inst), 6); \
851 *(inst)++ = (unsigned char)0x85; \
852 x86_mem_emit ((inst), (reg), (mem)); \
855 #define x86_test_membase_reg(inst,basereg,disp,reg) \
857 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
858 *(inst)++ = (unsigned char)0x85; \
859 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
862 #define x86_shift_reg_imm(inst,opc,reg,imm) \
865 x86_codegen_pre(&(inst), 2); \
866 *(inst)++ = (unsigned char)0xd1; \
867 x86_reg_emit ((inst), (opc), (reg)); \
869 x86_codegen_pre(&(inst), 3); \
870 *(inst)++ = (unsigned char)0xc1; \
871 x86_reg_emit ((inst), (opc), (reg)); \
872 x86_imm_emit8 ((inst), (imm)); \
876 #define x86_shift_mem_imm(inst,opc,mem,imm) \
879 x86_codegen_pre(&(inst), 6); \
880 *(inst)++ = (unsigned char)0xd1; \
881 x86_mem_emit ((inst), (opc), (mem)); \
883 x86_codegen_pre(&(inst), 7); \
884 *(inst)++ = (unsigned char)0xc1; \
885 x86_mem_emit ((inst), (opc), (mem)); \
886 x86_imm_emit8 ((inst), (imm)); \
890 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
893 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
894 *(inst)++ = (unsigned char)0xd1; \
895 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
897 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
898 *(inst)++ = (unsigned char)0xc1; \
899 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
900 x86_imm_emit8 ((inst), (imm)); \
904 #define x86_shift_reg(inst,opc,reg) \
906 x86_codegen_pre(&(inst), 2); \
907 *(inst)++ = (unsigned char)0xd3; \
908 x86_reg_emit ((inst), (opc), (reg)); \
911 #define x86_shift_mem(inst,opc,mem) \
913 x86_codegen_pre(&(inst), 6); \
914 *(inst)++ = (unsigned char)0xd3; \
915 x86_mem_emit ((inst), (opc), (mem)); \
918 #define x86_shift_membase(inst,opc,basereg,disp) \
920 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
921 *(inst)++ = (unsigned char)0xd3; \
922 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
926 * Multi op shift missing.
929 #define x86_shrd_reg(inst,dreg,reg) \
931 x86_codegen_pre(&(inst), 3); \
932 *(inst)++ = (unsigned char)0x0f; \
933 *(inst)++ = (unsigned char)0xad; \
934 x86_reg_emit ((inst), (reg), (dreg)); \
937 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
939 x86_codegen_pre(&(inst), 4); \
940 *(inst)++ = (unsigned char)0x0f; \
941 *(inst)++ = (unsigned char)0xac; \
942 x86_reg_emit ((inst), (reg), (dreg)); \
943 x86_imm_emit8 ((inst), (shamt)); \
946 #define x86_shld_reg(inst,dreg,reg) \
948 x86_codegen_pre(&(inst), 3); \
949 *(inst)++ = (unsigned char)0x0f; \
950 *(inst)++ = (unsigned char)0xa5; \
951 x86_reg_emit ((inst), (reg), (dreg)); \
954 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
956 x86_codegen_pre(&(inst), 4); \
957 *(inst)++ = (unsigned char)0x0f; \
958 *(inst)++ = (unsigned char)0xa4; \
959 x86_reg_emit ((inst), (reg), (dreg)); \
960 x86_imm_emit8 ((inst), (shamt)); \
966 #define x86_mul_reg(inst,reg,is_signed) \
968 x86_codegen_pre(&(inst), 2); \
969 *(inst)++ = (unsigned char)0xf7; \
970 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
973 #define x86_mul_mem(inst,mem,is_signed) \
975 x86_codegen_pre(&(inst), 6); \
976 *(inst)++ = (unsigned char)0xf7; \
977 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
980 #define x86_mul_membase(inst,basereg,disp,is_signed) \
982 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
983 *(inst)++ = (unsigned char)0xf7; \
984 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
990 #define x86_imul_reg_reg(inst,dreg,reg) \
992 x86_codegen_pre(&(inst), 3); \
993 *(inst)++ = (unsigned char)0x0f; \
994 *(inst)++ = (unsigned char)0xaf; \
995 x86_reg_emit ((inst), (dreg), (reg)); \
998 #define x86_imul_reg_mem(inst,reg,mem) \
1000 x86_codegen_pre(&(inst), 7); \
1001 *(inst)++ = (unsigned char)0x0f; \
1002 *(inst)++ = (unsigned char)0xaf; \
1003 x86_mem_emit ((inst), (reg), (mem)); \
1006 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
1008 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1009 *(inst)++ = (unsigned char)0x0f; \
1010 *(inst)++ = (unsigned char)0xaf; \
1011 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1017 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
1019 if (x86_is_imm8 ((imm))) { \
1020 x86_codegen_pre(&(inst), 3); \
1021 *(inst)++ = (unsigned char)0x6b; \
1022 x86_reg_emit ((inst), (dreg), (reg)); \
1023 x86_imm_emit8 ((inst), (imm)); \
1025 x86_codegen_pre(&(inst), 6); \
1026 *(inst)++ = (unsigned char)0x69; \
1027 x86_reg_emit ((inst), (dreg), (reg)); \
1028 x86_imm_emit32 ((inst), (imm)); \
1032 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
1034 if (x86_is_imm8 ((imm))) { \
1035 x86_codegen_pre(&(inst), 7); \
1036 *(inst)++ = (unsigned char)0x6b; \
1037 x86_mem_emit ((inst), (reg), (mem)); \
1038 x86_imm_emit8 ((inst), (imm)); \
1040 x86_codegen_pre(&(inst), 6); \
1041 *(inst)++ = (unsigned char)0x69; \
1042 x86_mem_emit ((inst), (reg), (mem)); \
1043 x86_imm_emit32 ((inst), (imm)); \
1047 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
1049 if (x86_is_imm8 ((imm))) { \
1050 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1051 *(inst)++ = (unsigned char)0x6b; \
1052 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1053 x86_imm_emit8 ((inst), (imm)); \
1055 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1056 *(inst)++ = (unsigned char)0x69; \
1057 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1058 x86_imm_emit32 ((inst), (imm)); \
1063 * divide EDX:EAX by rm;
1064 * eax = quotient, edx = remainder
1067 #define x86_div_reg(inst,reg,is_signed) \
1069 x86_codegen_pre(&(inst), 2); \
1070 *(inst)++ = (unsigned char)0xf7; \
1071 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
1074 #define x86_div_mem(inst,mem,is_signed) \
1076 x86_codegen_pre(&(inst), 6); \
1077 *(inst)++ = (unsigned char)0xf7; \
1078 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
1081 #define x86_div_membase(inst,basereg,disp,is_signed) \
1083 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1084 *(inst)++ = (unsigned char)0xf7; \
1085 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
1088 #define x86_mov_mem_reg(inst,mem,reg,size) \
1090 x86_codegen_pre(&(inst), 7); \
1092 case 1: *(inst)++ = (unsigned char)0x88; break; \
1093 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1094 case 4: *(inst)++ = (unsigned char)0x89; break; \
1095 default: assert (0); \
1097 x86_mem_emit ((inst), (reg), (mem)); \
1100 #define x86_mov_regp_reg(inst,regp,reg,size) \
1102 x86_codegen_pre(&(inst), 3); \
1104 case 1: *(inst)++ = (unsigned char)0x88; break; \
1105 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1106 case 4: *(inst)++ = (unsigned char)0x89; break; \
1107 default: assert (0); \
1109 x86_regp_emit ((inst), (reg), (regp)); \
1112 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
1114 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1116 case 1: *(inst)++ = (unsigned char)0x88; break; \
1117 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1118 case 4: *(inst)++ = (unsigned char)0x89; break; \
1119 default: assert (0); \
1121 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1124 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
1126 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1128 case 1: *(inst)++ = (unsigned char)0x88; break; \
1129 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1130 case 4: *(inst)++ = (unsigned char)0x89; break; \
1131 default: assert (0); \
1133 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1136 #define x86_mov_reg_reg(inst,dreg,reg,size) \
1138 x86_codegen_pre(&(inst), 3); \
1140 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1141 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1142 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1143 default: assert (0); \
1145 x86_reg_emit ((inst), (dreg), (reg)); \
1148 #define x86_mov_reg_mem(inst,reg,mem,size) \
1150 x86_codegen_pre(&(inst), 7); \
1152 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1153 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1154 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1155 default: assert (0); \
1157 x86_mem_emit ((inst), (reg), (mem)); \
1160 #define kMovRegMembasePadding (2 + kMaxMembaseEmitPadding)
1162 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
1164 x86_codegen_pre(&(inst), kMovRegMembasePadding); \
1166 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1167 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1168 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1169 default: assert (0); \
1171 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1174 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
1176 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1178 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1179 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1180 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1181 default: assert (0); \
1183 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1187 * Note: x86_clear_reg () chacnges the condition code!
1189 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
1191 #define x86_mov_reg_imm(inst,reg,imm) \
1193 x86_codegen_pre(&(inst), 5); \
1194 *(inst)++ = (unsigned char)0xb8 + (reg); \
1195 x86_imm_emit32 ((inst), (imm)); \
1198 #define x86_mov_mem_imm(inst,mem,imm,size) \
1200 if ((size) == 1) { \
1201 x86_codegen_pre(&(inst), 7); \
1202 *(inst)++ = (unsigned char)0xc6; \
1203 x86_mem_emit ((inst), 0, (mem)); \
1204 x86_imm_emit8 ((inst), (imm)); \
1205 } else if ((size) == 2) { \
1206 x86_codegen_pre(&(inst), 9); \
1207 x86_prefix((inst), X86_OPERAND_PREFIX); \
1208 *(inst)++ = (unsigned char)0xc7; \
1209 x86_mem_emit ((inst), 0, (mem)); \
1210 x86_imm_emit16 ((inst), (imm)); \
1212 x86_codegen_pre(&(inst), 10); \
1213 *(inst)++ = (unsigned char)0xc7; \
1214 x86_mem_emit ((inst), 0, (mem)); \
1215 x86_imm_emit32 ((inst), (imm)); \
1219 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
1221 if ((size) == 1) { \
1222 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1223 *(inst)++ = (unsigned char)0xc6; \
1224 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1225 x86_imm_emit8 ((inst), (imm)); \
1226 } else if ((size) == 2) { \
1227 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
1228 x86_prefix((inst), X86_OPERAND_PREFIX); \
1229 *(inst)++ = (unsigned char)0xc7; \
1230 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1231 x86_imm_emit16 ((inst), (imm)); \
1233 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1234 *(inst)++ = (unsigned char)0xc7; \
1235 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1236 x86_imm_emit32 ((inst), (imm)); \
1240 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1242 if ((size) == 1) { \
1243 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1244 *(inst)++ = (unsigned char)0xc6; \
1245 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1246 x86_imm_emit8 ((inst), (imm)); \
1247 } else if ((size) == 2) { \
1248 x86_codegen_pre(&(inst), 4 + kMaxMemindexEmitPadding); \
1249 x86_prefix((inst), X86_OPERAND_PREFIX); \
1250 *(inst)++ = (unsigned char)0xc7; \
1251 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1252 x86_imm_emit16 ((inst), (imm)); \
1254 x86_codegen_pre(&(inst), 5 + kMaxMemindexEmitPadding); \
1255 *(inst)++ = (unsigned char)0xc7; \
1256 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1257 x86_imm_emit32 ((inst), (imm)); \
1261 #define x86_lea_mem(inst,reg,mem) \
1263 x86_codegen_pre(&(inst), 5); \
1264 *(inst)++ = (unsigned char)0x8d; \
1265 x86_mem_emit ((inst), (reg), (mem)); \
1268 #define x86_lea_membase(inst,reg,basereg,disp) \
1270 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1271 *(inst)++ = (unsigned char)0x8d; \
1272 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1275 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1277 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1278 *(inst)++ = (unsigned char)0x8d; \
1279 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1282 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1284 unsigned char op = 0xb6; \
1285 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1286 x86_codegen_pre(&(inst), 3); \
1287 *(inst)++ = (unsigned char)0x0f; \
1288 if ((is_signed)) op += 0x08; \
1289 if ((is_half)) op += 0x01; \
1291 x86_reg_emit ((inst), (dreg), (reg)); \
1294 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1296 unsigned char op = 0xb6; \
1297 x86_codegen_pre(&(inst), 7); \
1298 *(inst)++ = (unsigned char)0x0f; \
1299 if ((is_signed)) op += 0x08; \
1300 if ((is_half)) op += 0x01; \
1302 x86_mem_emit ((inst), (dreg), (mem)); \
1305 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1307 unsigned char op = 0xb6; \
1308 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1309 *(inst)++ = (unsigned char)0x0f; \
1310 if ((is_signed)) op += 0x08; \
1311 if ((is_half)) op += 0x01; \
1313 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1316 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1318 unsigned char op = 0xb6; \
1319 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1320 *(inst)++ = (unsigned char)0x0f; \
1321 if ((is_signed)) op += 0x08; \
1322 if ((is_half)) op += 0x01; \
1324 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1327 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1328 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1330 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1332 x86_codegen_pre(&(inst), 6); \
1333 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1334 x86_mem_emit ((inst), (opc), (mem)); \
1337 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1339 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1340 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1341 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1344 #define x86_fp_op(inst,opc,index) \
1346 x86_codegen_pre(&(inst), 2); \
1347 *(inst)++ = (unsigned char)0xd8; \
1348 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1351 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1353 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1354 x86_codegen_pre(&(inst), 2); \
1355 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1356 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1360 * @x86_fp_int_op_membase
1361 * Supports FPU operations between ST(0) and integer operand in memory.
1362 * Operation encoded using X86_FP_Opcode enum.
1363 * Operand is addressed by [basereg + disp].
1364 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1366 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1368 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1369 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1370 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1373 #define x86_fstp(inst,index) \
1375 x86_codegen_pre(&(inst), 2); \
1376 *(inst)++ = (unsigned char)0xdd; \
1377 *(inst)++ = (unsigned char)0xd8+(index); \
1380 #define x86_fcompp(inst) \
1382 x86_codegen_pre(&(inst), 2); \
1383 *(inst)++ = (unsigned char)0xde; \
1384 *(inst)++ = (unsigned char)0xd9; \
1387 #define x86_fucompp(inst) \
1389 x86_codegen_pre(&(inst), 2); \
1390 *(inst)++ = (unsigned char)0xda; \
1391 *(inst)++ = (unsigned char)0xe9; \
1394 #define x86_fnstsw(inst) \
1396 x86_codegen_pre(&(inst), 2); \
1397 *(inst)++ = (unsigned char)0xdf; \
1398 *(inst)++ = (unsigned char)0xe0; \
1401 #define x86_fnstcw(inst,mem) \
1403 x86_codegen_pre(&(inst), 6); \
1404 *(inst)++ = (unsigned char)0xd9; \
1405 x86_mem_emit ((inst), 7, (mem)); \
1408 #define x86_fnstcw_membase(inst,basereg,disp) \
1410 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1411 *(inst)++ = (unsigned char)0xd9; \
1412 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1415 #define x86_fldcw(inst,mem) \
1417 x86_codegen_pre(&(inst), 6); \
1418 *(inst)++ = (unsigned char)0xd9; \
1419 x86_mem_emit ((inst), 5, (mem)); \
1422 #define x86_fldcw_membase(inst,basereg,disp) \
1424 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1425 *(inst)++ = (unsigned char)0xd9; \
1426 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1429 #define x86_fchs(inst) \
1431 x86_codegen_pre(&(inst), 2); \
1432 *(inst)++ = (unsigned char)0xd9; \
1433 *(inst)++ = (unsigned char)0xe0; \
1436 #define x86_frem(inst) \
1438 x86_codegen_pre(&(inst), 2); \
1439 *(inst)++ = (unsigned char)0xd9; \
1440 *(inst)++ = (unsigned char)0xf8; \
1443 #define x86_fxch(inst,index) \
1445 x86_codegen_pre(&(inst), 2); \
1446 *(inst)++ = (unsigned char)0xd9; \
1447 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1450 #define x86_fcomi(inst,index) \
1452 x86_codegen_pre(&(inst), 2); \
1453 *(inst)++ = (unsigned char)0xdb; \
1454 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1457 #define x86_fcomip(inst,index) \
1459 x86_codegen_pre(&(inst), 2); \
1460 *(inst)++ = (unsigned char)0xdf; \
1461 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1464 #define x86_fucomi(inst,index) \
1466 x86_codegen_pre(&(inst), 2); \
1467 *(inst)++ = (unsigned char)0xdb; \
1468 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1471 #define x86_fucomip(inst,index) \
1473 x86_codegen_pre(&(inst), 2); \
1474 *(inst)++ = (unsigned char)0xdf; \
1475 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1478 #define x86_fld(inst,mem,is_double) \
1480 x86_codegen_pre(&(inst), 6); \
1481 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1482 x86_mem_emit ((inst), 0, (mem)); \
1485 #define x86_fld_membase(inst,basereg,disp,is_double) \
1487 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1488 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1489 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1492 #define x86_fld80_mem(inst,mem) \
1494 x86_codegen_pre(&(inst), 6); \
1495 *(inst)++ = (unsigned char)0xdb; \
1496 x86_mem_emit ((inst), 5, (mem)); \
1499 #define x86_fld80_membase(inst,basereg,disp) \
1501 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1502 *(inst)++ = (unsigned char)0xdb; \
1503 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1506 #define x86_fild(inst,mem,is_long) \
1508 x86_codegen_pre(&(inst), 6); \
1510 *(inst)++ = (unsigned char)0xdf; \
1511 x86_mem_emit ((inst), 5, (mem)); \
1513 *(inst)++ = (unsigned char)0xdb; \
1514 x86_mem_emit ((inst), 0, (mem)); \
1518 #define x86_fild_membase(inst,basereg,disp,is_long) \
1520 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1522 *(inst)++ = (unsigned char)0xdf; \
1523 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1525 *(inst)++ = (unsigned char)0xdb; \
1526 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1530 #define x86_fld_reg(inst,index) \
1532 x86_codegen_pre(&(inst), 2); \
1533 *(inst)++ = (unsigned char)0xd9; \
1534 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1537 #define x86_fldz(inst) \
1539 x86_codegen_pre(&(inst), 2); \
1540 *(inst)++ = (unsigned char)0xd9; \
1541 *(inst)++ = (unsigned char)0xee; \
1544 #define x86_fld1(inst) \
1546 x86_codegen_pre(&(inst), 2); \
1547 *(inst)++ = (unsigned char)0xd9; \
1548 *(inst)++ = (unsigned char)0xe8; \
1551 #define x86_fldpi(inst) \
1553 x86_codegen_pre(&(inst), 2); \
1554 *(inst)++ = (unsigned char)0xd9; \
1555 *(inst)++ = (unsigned char)0xeb; \
1558 #define x86_fst(inst,mem,is_double,pop_stack) \
1560 x86_codegen_pre(&(inst), 6); \
1561 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1562 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1565 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1567 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1568 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1569 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1572 #define x86_fst80_mem(inst,mem) \
1574 x86_codegen_pre(&(inst), 6); \
1575 *(inst)++ = (unsigned char)0xdb; \
1576 x86_mem_emit ((inst), 7, (mem)); \
1580 #define x86_fst80_membase(inst,basereg,disp) \
1582 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1583 *(inst)++ = (unsigned char)0xdb; \
1584 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1588 #define x86_fist_pop(inst,mem,is_long) \
1590 x86_codegen_pre(&(inst), 6); \
1592 *(inst)++ = (unsigned char)0xdf; \
1593 x86_mem_emit ((inst), 7, (mem)); \
1595 *(inst)++ = (unsigned char)0xdb; \
1596 x86_mem_emit ((inst), 3, (mem)); \
1600 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1602 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1604 *(inst)++ = (unsigned char)0xdf; \
1605 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1607 *(inst)++ = (unsigned char)0xdb; \
1608 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1612 #define x86_fstsw(inst) \
1614 x86_codegen_pre(&(inst), 3); \
1615 *(inst)++ = (unsigned char)0x9b; \
1616 *(inst)++ = (unsigned char)0xdf; \
1617 *(inst)++ = (unsigned char)0xe0; \
1622 * Converts content of ST(0) to integer and stores it at memory location
1623 * addressed by [basereg + disp].
1624 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1626 #define x86_fist_membase(inst,basereg,disp,is_int) \
1628 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1630 *(inst)++ = (unsigned char)0xdb; \
1631 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1633 *(inst)++ = (unsigned char)0xdf; \
1634 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1639 #define x86_push_reg(inst,reg) \
1641 *(inst)++ = (unsigned char)0x50 + (reg); \
1644 #define x86_push_regp(inst,reg) \
1646 x86_codegen_pre(&(inst), 2); \
1647 *(inst)++ = (unsigned char)0xff; \
1648 x86_regp_emit ((inst), 6, (reg)); \
1651 #define x86_push_mem(inst,mem) \
1653 x86_codegen_pre(&(inst), 6); \
1654 *(inst)++ = (unsigned char)0xff; \
1655 x86_mem_emit ((inst), 6, (mem)); \
1658 #define x86_push_membase(inst,basereg,disp) \
1660 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1661 *(inst)++ = (unsigned char)0xff; \
1662 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1665 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1667 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1668 *(inst)++ = (unsigned char)0xff; \
1669 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1672 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1674 #define x86_push_imm(inst,imm) \
1676 int _imm = (int) (imm); \
1677 if (x86_is_imm8 (_imm)) { \
1678 x86_codegen_pre(&(inst), 2); \
1679 *(inst)++ = (unsigned char)0x6A; \
1680 x86_imm_emit8 ((inst), (_imm)); \
1682 x86_codegen_pre(&(inst), 5); \
1683 *(inst)++ = (unsigned char)0x68; \
1684 x86_imm_emit32 ((inst), (_imm)); \
1688 #define x86_pop_reg(inst,reg) \
1690 *(inst)++ = (unsigned char)0x58 + (reg); \
1693 #define x86_pop_mem(inst,mem) \
1695 x86_codegen_pre(&(inst), 6); \
1696 *(inst)++ = (unsigned char)0x87; \
1697 x86_mem_emit ((inst), 0, (mem)); \
1700 #define x86_pop_membase(inst,basereg,disp) \
1702 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1703 *(inst)++ = (unsigned char)0x87; \
1704 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1707 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1708 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1709 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1710 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1712 #define x86_loop(inst,imm) \
1714 x86_codegen_pre(&(inst), 2); \
1715 *(inst)++ = (unsigned char)0xe2; \
1716 x86_imm_emit8 ((inst), (imm)); \
1719 #define x86_loope(inst,imm) \
1721 x86_codegen_pre(&(inst), 2); \
1722 *(inst)++ = (unsigned char)0xe1; \
1723 x86_imm_emit8 ((inst), (imm)); \
1726 #define x86_loopne(inst,imm) \
1728 x86_codegen_pre(&(inst), 2); \
1729 *(inst)++ = (unsigned char)0xe0; \
1730 x86_imm_emit8 ((inst), (imm)); \
1733 #if defined(TARGET_X86)
1734 #define x86_jump32(inst,imm) \
1736 x86_codegen_pre(&(inst), 5); \
1737 *(inst)++ = (unsigned char)0xe9; \
1738 x86_imm_emit32 ((inst), (imm)); \
1741 #define x86_jump8(inst,imm) \
1743 x86_codegen_pre(&(inst), 2); \
1744 *(inst)++ = (unsigned char)0xeb; \
1745 x86_imm_emit8 ((inst), (imm)); \
1747 #elif defined(TARGET_AMD64)
1748 /* These macros are used directly from mini-amd64.c and other */
1749 /* amd64 specific files, so they need to be instrumented directly. */
1750 #define x86_jump32(inst,imm) \
1752 amd64_codegen_pre(inst); \
1753 *(inst)++ = (unsigned char)0xe9; \
1754 x86_imm_emit32 ((inst), (imm)); \
1755 amd64_codegen_post(inst); \
1758 #define x86_jump8(inst,imm) \
1760 amd64_codegen_pre(inst); \
1761 *(inst)++ = (unsigned char)0xeb; \
1762 x86_imm_emit8 ((inst), (imm)); \
1763 amd64_codegen_post(inst); \
1767 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
1768 #define x86_jump_reg(inst,reg) do { \
1769 x86_codegen_pre(&(inst), 5); \
1770 *(inst)++ = (unsigned char)0x83; /* and */ \
1771 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
1772 *(inst)++ = (unsigned char)nacl_align_byte; \
1773 *(inst)++ = (unsigned char)0xff; \
1774 x86_reg_emit ((inst), 4, (reg)); \
1777 /* Let's hope ECX is available for these... */
1778 #define x86_jump_mem(inst,mem) do { \
1779 x86_mov_reg_mem(inst, (X86_ECX), (mem), 4); \
1780 x86_jump_reg(inst, (X86_ECX)); \
1783 #define x86_jump_membase(inst,basereg,disp) do { \
1784 x86_mov_reg_membase(inst, (X86_ECX), basereg, disp, 4); \
1785 x86_jump_reg(inst, (X86_ECX)); \
1788 /* like x86_jump_membase, but force a 32-bit displacement */
1789 #define x86_jump_membase32(inst,basereg,disp) do { \
1790 x86_codegen_pre(&(inst), 6); \
1791 *(inst)++ = (unsigned char)0x8b; \
1792 x86_address_byte ((inst), 2, X86_ECX, (basereg)); \
1793 x86_imm_emit32 ((inst), (disp)); \
1794 x86_jump_reg(inst, (X86_ECX)); \
1796 #else /* __native_client_codegen__ */
1797 #define x86_jump_reg(inst,reg) \
1799 *(inst)++ = (unsigned char)0xff; \
1800 x86_reg_emit ((inst), 4, (reg)); \
1803 #define x86_jump_mem(inst,mem) \
1805 *(inst)++ = (unsigned char)0xff; \
1806 x86_mem_emit ((inst), 4, (mem)); \
1809 #define x86_jump_membase(inst,basereg,disp) \
1811 *(inst)++ = (unsigned char)0xff; \
1812 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1814 #endif /* __native_client_codegen__ */
1816 * target is a pointer in our buffer.
1818 #define x86_jump_code_body(inst,target) \
1821 x86_codegen_pre(&(inst), 2); \
1822 t = (unsigned char*)(target) - (inst) - 2; \
1823 if (x86_is_imm8(t)) { \
1824 x86_jump8 ((inst), t); \
1826 x86_codegen_pre(&(inst), 5); \
1827 t = (unsigned char*)(target) - (inst) - 5; \
1828 x86_jump32 ((inst), t); \
1832 #if defined(__default_codegen__)
1833 #define x86_jump_code(inst,target) \
1835 x86_jump_code_body((inst),(target)); \
1837 #elif defined(__native_client_codegen__) && defined(TARGET_X86)
1838 #define x86_jump_code(inst,target) \
1840 guint8* jump_start = (inst); \
1841 x86_jump_code_body((inst),(target)); \
1842 x86_patch(jump_start, (target)); \
1844 #elif defined(__native_client_codegen__) && defined(TARGET_AMD64)
1845 #define x86_jump_code(inst,target) \
1847 /* jump_code_body is used twice because there are offsets */ \
1848 /* calculated based on the IP, which can change after the */ \
1849 /* call to amd64_codegen_post */ \
1850 amd64_codegen_pre(inst); \
1851 x86_jump_code_body((inst),(target)); \
1852 inst = amd64_codegen_post(inst); \
1853 x86_jump_code_body((inst),(target)); \
1855 #endif /* __native_client_codegen__ */
1857 #define x86_jump_disp(inst,disp) \
1859 int t = (disp) - 2; \
1860 if (x86_is_imm8(t)) { \
1861 x86_jump8 ((inst), t); \
1864 x86_jump32 ((inst), t); \
1868 #if defined(TARGET_X86)
1869 #define x86_branch8(inst,cond,imm,is_signed) \
1871 x86_codegen_pre(&(inst), 2); \
1873 *(inst)++ = x86_cc_signed_map [(cond)]; \
1875 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1876 x86_imm_emit8 ((inst), (imm)); \
1879 #define x86_branch32(inst,cond,imm,is_signed) \
1881 x86_codegen_pre(&(inst), 6); \
1882 *(inst)++ = (unsigned char)0x0f; \
1884 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1886 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1887 x86_imm_emit32 ((inst), (imm)); \
1889 #elif defined(TARGET_AMD64)
1890 /* These macros are used directly from mini-amd64.c and other */
1891 /* amd64 specific files, so they need to be instrumented directly. */
1892 #define x86_branch8(inst,cond,imm,is_signed) \
1894 amd64_codegen_pre(inst); \
1896 *(inst)++ = x86_cc_signed_map [(cond)]; \
1898 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1899 x86_imm_emit8 ((inst), (imm)); \
1900 amd64_codegen_post(inst); \
1902 #define x86_branch32(inst,cond,imm,is_signed) \
1904 amd64_codegen_pre(inst); \
1905 *(inst)++ = (unsigned char)0x0f; \
1907 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1909 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1910 x86_imm_emit32 ((inst), (imm)); \
1911 amd64_codegen_post(inst); \
1915 #if defined(TARGET_X86)
1916 #define x86_branch(inst,cond,target,is_signed) \
1919 guint8* branch_start; \
1920 x86_codegen_pre(&(inst), 2); \
1921 offset = (target) - (inst) - 2; \
1922 branch_start = (inst); \
1923 if (x86_is_imm8 ((offset))) \
1924 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1926 x86_codegen_pre(&(inst), 6); \
1927 offset = (target) - (inst) - 6; \
1928 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1930 x86_patch(branch_start, (target)); \
1932 #elif defined(TARGET_AMD64)
1933 /* This macro is used directly from mini-amd64.c and other */
1934 /* amd64 specific files, so it needs to be instrumented directly. */
1936 #define x86_branch_body(inst,cond,target,is_signed) \
1938 int offset = (target) - (inst) - 2; \
1939 if (x86_is_imm8 ((offset))) \
1940 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1942 offset = (target) - (inst) - 6; \
1943 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1947 #if defined(__default_codegen__)
1948 #define x86_branch(inst,cond,target,is_signed) \
1950 x86_branch_body((inst),(cond),(target),(is_signed)); \
1952 #elif defined(__native_client_codegen__)
1953 #define x86_branch(inst,cond,target,is_signed) \
1955 /* branch_body is used twice because there are offsets */ \
1956 /* calculated based on the IP, which can change after */ \
1957 /* the call to amd64_codegen_post */ \
1958 amd64_codegen_pre(inst); \
1959 x86_branch_body((inst),(cond),(target),(is_signed)); \
1960 inst = amd64_codegen_post(inst); \
1961 x86_branch_body((inst),(cond),(target),(is_signed)); \
1963 #endif /* __native_client_codegen__ */
1965 #endif /* TARGET_AMD64 */
1967 #define x86_branch_disp(inst,cond,disp,is_signed) \
1969 int offset = (disp) - 2; \
1970 if (x86_is_imm8 ((offset))) \
1971 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1974 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1978 #define x86_set_reg(inst,cond,reg,is_signed) \
1980 g_assert (X86_IS_BYTE_REG (reg)); \
1981 x86_codegen_pre(&(inst), 3); \
1982 *(inst)++ = (unsigned char)0x0f; \
1984 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1986 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1987 x86_reg_emit ((inst), 0, (reg)); \
1990 #define x86_set_mem(inst,cond,mem,is_signed) \
1992 x86_codegen_pre(&(inst), 7); \
1993 *(inst)++ = (unsigned char)0x0f; \
1995 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1997 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1998 x86_mem_emit ((inst), 0, (mem)); \
2001 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
2003 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2004 *(inst)++ = (unsigned char)0x0f; \
2006 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
2008 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
2009 x86_membase_emit ((inst), 0, (basereg), (disp)); \
2012 #define x86_call_imm_body(inst,disp) \
2014 *(inst)++ = (unsigned char)0xe8; \
2015 x86_imm_emit32 ((inst), (int)(disp)); \
2018 #define x86_call_imm(inst,disp) \
2020 x86_call_sequence_pre((inst)); \
2021 x86_call_imm_body((inst), (disp)); \
2022 x86_call_sequence_post((inst)); \
2026 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2027 #define x86_call_reg_internal(inst,reg) \
2029 *(inst)++ = (unsigned char)0x83; /* and */ \
2030 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
2031 *(inst)++ = (unsigned char)nacl_align_byte; \
2032 *(inst)++ = (unsigned char)0xff; /* call */ \
2033 x86_reg_emit ((inst), 2, (reg)); /* reg */ \
2036 #define x86_call_reg(inst, reg) do { \
2037 x86_call_sequence_pre((inst)); \
2038 x86_call_reg_internal(inst, reg); \
2039 x86_call_sequence_post((inst)); \
2043 /* It appears that x86_call_mem() is never used, so I'm leaving it out. */
2044 #define x86_call_membase(inst,basereg,disp) do { \
2045 x86_call_sequence_pre((inst)); \
2046 /* x86_mov_reg_membase() inlined so its fixed size */ \
2047 *(inst)++ = (unsigned char)0x8b; \
2048 x86_address_byte ((inst), 2, (X86_ECX), (basereg)); \
2049 x86_imm_emit32 ((inst), (disp)); \
2050 x86_call_reg_internal(inst, X86_ECX); \
2051 x86_call_sequence_post((inst)); \
2053 #else /* __native_client_codegen__ */
2054 #define x86_call_reg(inst,reg) \
2056 *(inst)++ = (unsigned char)0xff; \
2057 x86_reg_emit ((inst), 2, (reg)); \
2060 #define x86_call_mem(inst,mem) \
2062 *(inst)++ = (unsigned char)0xff; \
2063 x86_mem_emit ((inst), 2, (mem)); \
2066 #define x86_call_membase(inst,basereg,disp) \
2068 *(inst)++ = (unsigned char)0xff; \
2069 x86_membase_emit ((inst), 2, (basereg), (disp)); \
2071 #endif /* __native_client_codegen__ */
2074 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2076 #define x86_call_code(inst,target) \
2079 guint8* call_start; \
2080 guint8* _aligned_start; \
2081 x86_call_sequence_pre_val((inst)); \
2082 _x86_offset = (unsigned char*)(target) - (inst); \
2084 x86_call_imm_body ((inst), _x86_offset); \
2085 _aligned_start = x86_call_sequence_post_val((inst)); \
2086 call_start = _aligned_start; \
2087 _x86_offset = (unsigned char*)(target) - (_aligned_start); \
2089 x86_call_imm_body ((_aligned_start), _x86_offset); \
2090 x86_patch(call_start, (target)); \
2093 #define SIZE_OF_RET 6
2094 #define x86_ret(inst) do { \
2095 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2096 x86_codegen_pre(&(inst), 5); \
2097 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2098 *(inst)++ = (unsigned char)0xe1; \
2099 *(inst)++ = (unsigned char)nacl_align_byte; \
2100 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2101 *(inst)++ = (unsigned char)0xe1; \
2104 /* pop return address */
2105 /* pop imm bytes from stack */
2107 #define x86_ret_imm(inst,imm) do { \
2108 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2109 x86_alu_reg_imm ((inst), X86_ADD, X86_ESP, imm); \
2110 x86_codegen_pre(&(inst), 5); \
2111 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2112 *(inst)++ = (unsigned char)0xe1; \
2113 *(inst)++ = (unsigned char)nacl_align_byte; \
2114 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2115 *(inst)++ = (unsigned char)0xe1; \
2117 #else /* __native_client_codegen__ */
2119 #define x86_call_code(inst,target) \
2122 _x86_offset = (unsigned char*)(target) - (inst); \
2124 x86_call_imm_body ((inst), _x86_offset); \
2127 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
2129 #define x86_ret_imm(inst,imm) \
2134 x86_codegen_pre(&(inst), 3); \
2135 *(inst)++ = (unsigned char)0xc2; \
2136 x86_imm_emit16 ((inst), (imm)); \
2139 #endif /* __native_client_codegen__ */
2141 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
2143 x86_codegen_pre(&(inst), 3); \
2144 *(inst)++ = (unsigned char) 0x0f; \
2146 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2148 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2149 x86_reg_emit ((inst), (dreg), (reg)); \
2152 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
2154 x86_codegen_pre(&(inst), 7); \
2155 *(inst)++ = (unsigned char) 0x0f; \
2157 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2159 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2160 x86_mem_emit ((inst), (reg), (mem)); \
2163 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
2165 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2166 *(inst)++ = (unsigned char) 0x0f; \
2168 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2170 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2171 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2174 #define x86_enter(inst,framesize) \
2176 x86_codegen_pre(&(inst), 4); \
2177 *(inst)++ = (unsigned char)0xc8; \
2178 x86_imm_emit16 ((inst), (framesize)); \
2182 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
2183 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
2185 #define x86_fsin(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
2186 #define x86_fcos(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
2187 #define x86_fabs(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
2188 #define x86_ftst(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
2189 #define x86_fxam(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
2190 #define x86_fpatan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
2191 #define x86_fprem(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
2192 #define x86_fprem1(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
2193 #define x86_frndint(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
2194 #define x86_fsqrt(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
2195 #define x86_fptan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
2197 #define x86_padding(inst,size) \
2200 case 1: x86_nop ((inst)); break; \
2201 case 2: *(inst)++ = 0x8b; \
2202 *(inst)++ = 0xc0; break; \
2203 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
2204 *(inst)++ = 0x00; break; \
2205 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2206 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2208 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2209 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2210 x86_nop ((inst)); break; \
2211 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
2212 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2213 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2215 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
2216 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2217 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2218 *(inst)++ = 0x00; break; \
2219 default: assert (0); \
2223 #ifdef __native_client_codegen__
2225 #define kx86NaClLengthOfCallReg 5
2226 #define kx86NaClLengthOfCallImm 5
2227 #define kx86NaClLengthOfCallMembase (kx86NaClLengthOfCallReg + 6)
2229 #endif /* __native_client_codegen__ */
2231 #define x86_prolog(inst,frame_size,reg_mask) \
2233 unsigned i, m = 1; \
2234 x86_enter ((inst), (frame_size)); \
2235 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
2236 if ((reg_mask) & m) \
2237 x86_push_reg ((inst), i); \
2241 #define x86_epilog(inst,reg_mask) \
2243 unsigned i, m = 1 << X86_EDI; \
2244 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
2245 if ((reg_mask) & m) \
2246 x86_pop_reg ((inst), i); \
2248 x86_leave ((inst)); \
2254 X86_SSE_SQRT = 0x51,
2255 X86_SSE_RSQRT = 0x52,
2263 X86_SSE_COMP = 0xC2,
2265 X86_SSE_ANDN = 0x55,
2268 X86_SSE_UNPCKL = 0x14,
2269 X86_SSE_UNPCKH = 0x15,
2271 X86_SSE_ADDSUB = 0xD0,
2272 X86_SSE_HADD = 0x7C,
2273 X86_SSE_HSUB = 0x7D,
2274 X86_SSE_MOVSHDUP = 0x16,
2275 X86_SSE_MOVSLDUP = 0x12,
2276 X86_SSE_MOVDDUP = 0x12,
2278 X86_SSE_PAND = 0xDB,
2280 X86_SSE_PXOR = 0xEF,
2282 X86_SSE_PADDB = 0xFC,
2283 X86_SSE_PADDW = 0xFD,
2284 X86_SSE_PADDD = 0xFE,
2285 X86_SSE_PADDQ = 0xD4,
2287 X86_SSE_PSUBB = 0xF8,
2288 X86_SSE_PSUBW = 0xF9,
2289 X86_SSE_PSUBD = 0xFA,
2290 X86_SSE_PSUBQ = 0xFB,
2292 X86_SSE_PMAXSB = 0x3C, /*sse41*/
2293 X86_SSE_PMAXSW = 0xEE,
2294 X86_SSE_PMAXSD = 0x3D, /*sse41*/
2296 X86_SSE_PMAXUB = 0xDE,
2297 X86_SSE_PMAXUW = 0x3E, /*sse41*/
2298 X86_SSE_PMAXUD = 0x3F, /*sse41*/
2300 X86_SSE_PMINSB = 0x38, /*sse41*/
2301 X86_SSE_PMINSW = 0xEA,
2302 X86_SSE_PMINSD = 0x39,/*sse41*/
2304 X86_SSE_PMINUB = 0xDA,
2305 X86_SSE_PMINUW = 0x3A, /*sse41*/
2306 X86_SSE_PMINUD = 0x3B, /*sse41*/
2308 X86_SSE_PAVGB = 0xE0,
2309 X86_SSE_PAVGW = 0xE3,
2311 X86_SSE_PCMPEQB = 0x74,
2312 X86_SSE_PCMPEQW = 0x75,
2313 X86_SSE_PCMPEQD = 0x76,
2314 X86_SSE_PCMPEQQ = 0x29, /*sse41*/
2316 X86_SSE_PCMPGTB = 0x64,
2317 X86_SSE_PCMPGTW = 0x65,
2318 X86_SSE_PCMPGTD = 0x66,
2319 X86_SSE_PCMPGTQ = 0x37, /*sse42*/
2321 X86_SSE_PSADBW = 0xf6,
2323 X86_SSE_PSHUFD = 0x70,
2325 X86_SSE_PUNPCKLBW = 0x60,
2326 X86_SSE_PUNPCKLWD = 0x61,
2327 X86_SSE_PUNPCKLDQ = 0x62,
2328 X86_SSE_PUNPCKLQDQ = 0x6C,
2330 X86_SSE_PUNPCKHBW = 0x68,
2331 X86_SSE_PUNPCKHWD = 0x69,
2332 X86_SSE_PUNPCKHDQ = 0x6A,
2333 X86_SSE_PUNPCKHQDQ = 0x6D,
2335 X86_SSE_PACKSSWB = 0x63,
2336 X86_SSE_PACKSSDW = 0x6B,
2338 X86_SSE_PACKUSWB = 0x67,
2339 X86_SSE_PACKUSDW = 0x2B,/*sse41*/
2341 X86_SSE_PADDUSB = 0xDC,
2342 X86_SSE_PADDUSW = 0xDD,
2343 X86_SSE_PSUBUSB = 0xD8,
2344 X86_SSE_PSUBUSW = 0xD9,
2346 X86_SSE_PADDSB = 0xEC,
2347 X86_SSE_PADDSW = 0xED,
2348 X86_SSE_PSUBSB = 0xE8,
2349 X86_SSE_PSUBSW = 0xE9,
2351 X86_SSE_PMULLW = 0xD5,
2352 X86_SSE_PMULLD = 0x40,/*sse41*/
2353 X86_SSE_PMULHUW = 0xE4,
2354 X86_SSE_PMULHW = 0xE5,
2355 X86_SSE_PMULUDQ = 0xF4,
2357 X86_SSE_PMOVMSKB = 0xD7,
2359 X86_SSE_PSHIFTW = 0x71,
2360 X86_SSE_PSHIFTD = 0x72,
2361 X86_SSE_PSHIFTQ = 0x73,
2366 X86_SSE_PSRLW_REG = 0xD1,
2367 X86_SSE_PSRAW_REG = 0xE1,
2368 X86_SSE_PSLLW_REG = 0xF1,
2370 X86_SSE_PSRLD_REG = 0xD2,
2371 X86_SSE_PSRAD_REG = 0xE2,
2372 X86_SSE_PSLLD_REG = 0xF2,
2374 X86_SSE_PSRLQ_REG = 0xD3,
2375 X86_SSE_PSLLQ_REG = 0xF3,
2377 X86_SSE_PREFETCH = 0x18,
2378 X86_SSE_MOVNTPS = 0x2B,
2379 X86_SSE_MOVHPD_REG_MEMBASE = 0x16,
2380 X86_SSE_MOVHPD_MEMBASE_REG = 0x17,
2382 X86_SSE_MOVSD_REG_MEMBASE = 0x10,
2383 X86_SSE_MOVSD_MEMBASE_REG = 0x11,
2385 X86_SSE_PINSRB = 0x20,/*sse41*/
2386 X86_SSE_PINSRW = 0xC4,
2387 X86_SSE_PINSRD = 0x22,/*sse41*/
2389 X86_SSE_PEXTRB = 0x14,/*sse41*/
2390 X86_SSE_PEXTRW = 0xC5,
2391 X86_SSE_PEXTRD = 0x16,/*sse41*/
2393 X86_SSE_SHUFP = 0xC6,
2395 X86_SSE_CVTDQ2PD = 0xE6,
2396 X86_SSE_CVTDQ2PS = 0x5B,
2397 X86_SSE_CVTPD2DQ = 0xE6,
2398 X86_SSE_CVTPD2PS = 0x5A,
2399 X86_SSE_CVTPS2DQ = 0x5B,
2400 X86_SSE_CVTPS2PD = 0x5A,
2401 X86_SSE_CVTTPD2DQ = 0xE6,
2402 X86_SSE_CVTTPS2DQ = 0x5B,
2406 /* minimal SSE* support */
2407 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
2409 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2410 *(inst)++ = (unsigned char)0xf2; \
2411 *(inst)++ = (unsigned char)0x0f; \
2412 *(inst)++ = (unsigned char)0x10; \
2413 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
2416 #define x86_cvttsd2si(inst,dreg,reg) \
2418 x86_codegen_pre(&(inst), 4); \
2419 *(inst)++ = (unsigned char)0xf2; \
2420 *(inst)++ = (unsigned char)0x0f; \
2421 *(inst)++ = (unsigned char)0x2c; \
2422 x86_reg_emit ((inst), (dreg), (reg)); \
2425 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
2427 x86_codegen_pre(&(inst), 3); \
2428 *(inst)++ = (unsigned char)0x0F; \
2429 *(inst)++ = (unsigned char)(opc); \
2430 x86_reg_emit ((inst), (dreg), (reg)); \
2433 #define x86_sse_alu_reg_membase(inst,opc,sreg,basereg,disp) \
2435 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2436 *(inst)++ = (unsigned char)0x0f; \
2437 *(inst)++ = (unsigned char)(opc); \
2438 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2441 #define x86_sse_alu_membase_reg(inst,opc,basereg,disp,reg) \
2443 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2444 *(inst)++ = (unsigned char)0x0F; \
2445 *(inst)++ = (unsigned char)(opc); \
2446 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2449 #define x86_sse_alu_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2451 x86_codegen_pre(&(inst), 4); \
2452 *(inst)++ = (unsigned char)0x0F; \
2453 *(inst)++ = (unsigned char)(opc); \
2454 x86_reg_emit ((inst), (dreg), (reg)); \
2455 *(inst)++ = (unsigned char)(imm8); \
2458 #define x86_sse_alu_pd_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2460 x86_codegen_pre(&(inst), 5); \
2461 *(inst)++ = (unsigned char)0x66; \
2462 x86_sse_alu_reg_reg_imm8 ((inst), (opc), (dreg), (reg), (imm8)); \
2465 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
2467 x86_codegen_pre(&(inst), 4); \
2468 *(inst)++ = (unsigned char)0x66; \
2469 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2472 #define x86_sse_alu_pd_membase_reg(inst,opc,basereg,disp,reg) \
2474 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2475 *(inst)++ = (unsigned char)0x66; \
2476 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2479 #define x86_sse_alu_pd_reg_membase(inst,opc,dreg,basereg,disp) \
2481 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2482 *(inst)++ = (unsigned char)0x66; \
2483 x86_sse_alu_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2486 #define x86_sse_alu_pd_reg_reg_imm(inst,opc,dreg,reg,imm) \
2488 x86_codegen_pre(&(inst), 5); \
2489 x86_sse_alu_pd_reg_reg ((inst), (opc), (dreg), (reg)); \
2490 *(inst)++ = (unsigned char)(imm); \
2493 #define x86_sse_alu_pd_reg_membase_imm(inst,opc,dreg,basereg,disp,imm) \
2495 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
2496 x86_sse_alu_pd_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2497 *(inst)++ = (unsigned char)(imm); \
2501 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
2503 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2506 #define x86_sse_alu_ps_reg_reg_imm(inst,opc,dreg,reg, imm) \
2508 x86_codegen_pre(&(inst), 4); \
2509 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2510 *(inst)++ = (unsigned char)imm; \
2514 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
2516 x86_codegen_pre(&(inst), 4); \
2517 *(inst)++ = (unsigned char)0xF2; \
2518 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2521 #define x86_sse_alu_sd_membase_reg(inst,opc,basereg,disp,reg) \
2523 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2524 *(inst)++ = (unsigned char)0xF2; \
2525 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2529 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
2531 x86_codegen_pre(&(inst), 4); \
2532 *(inst)++ = (unsigned char)0xF3; \
2533 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2536 #define x86_sse_alu_ss_membase_reg(inst,opc,basereg,disp,reg) \
2538 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2539 *(inst)++ = (unsigned char)0xF3; \
2540 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2545 #define x86_sse_alu_sse41_reg_reg(inst,opc,dreg,reg) \
2547 x86_codegen_pre(&(inst), 5); \
2548 *(inst)++ = (unsigned char)0x66; \
2549 *(inst)++ = (unsigned char)0x0F; \
2550 *(inst)++ = (unsigned char)0x38; \
2551 *(inst)++ = (unsigned char)(opc); \
2552 x86_reg_emit ((inst), (dreg), (reg)); \
2555 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
2557 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2558 *(inst)++ = (unsigned char)0x0f; \
2559 *(inst)++ = (unsigned char)0x10; \
2560 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2563 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
2565 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2566 *(inst)++ = (unsigned char)0x0f; \
2567 *(inst)++ = (unsigned char)0x11; \
2568 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2571 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
2573 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2574 *(inst)++ = (unsigned char)0x0f; \
2575 *(inst)++ = (unsigned char)0x28; \
2576 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2579 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
2581 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2582 *(inst)++ = (unsigned char)0x0f; \
2583 *(inst)++ = (unsigned char)0x29; \
2584 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2587 #define x86_movaps_reg_reg(inst,dreg,sreg) \
2589 x86_codegen_pre(&(inst), 3); \
2590 *(inst)++ = (unsigned char)0x0f; \
2591 *(inst)++ = (unsigned char)0x28; \
2592 x86_reg_emit ((inst), (dreg), (sreg)); \
2596 #define x86_movd_reg_xreg(inst,dreg,sreg) \
2598 x86_codegen_pre(&(inst), 4); \
2599 *(inst)++ = (unsigned char)0x66; \
2600 *(inst)++ = (unsigned char)0x0f; \
2601 *(inst)++ = (unsigned char)0x7e; \
2602 x86_reg_emit ((inst), (sreg), (dreg)); \
2605 #define x86_movd_xreg_reg(inst,dreg,sreg) \
2607 x86_codegen_pre(&(inst), 4); \
2608 *(inst)++ = (unsigned char)0x66; \
2609 *(inst)++ = (unsigned char)0x0f; \
2610 *(inst)++ = (unsigned char)0x6e; \
2611 x86_reg_emit ((inst), (dreg), (sreg)); \
2614 #define x86_movd_xreg_membase(inst,sreg,basereg,disp) \
2616 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2617 *(inst)++ = (unsigned char)0x66; \
2618 *(inst)++ = (unsigned char)0x0f; \
2619 *(inst)++ = (unsigned char)0x6e; \
2620 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2623 #define x86_pshufw_reg_reg(inst,dreg,sreg,mask,high_words) \
2625 x86_codegen_pre(&(inst), 5); \
2626 *(inst)++ = (unsigned char)(high_words) ? 0xF3 : 0xF2; \
2627 *(inst)++ = (unsigned char)0x0f; \
2628 *(inst)++ = (unsigned char)0x70; \
2629 x86_reg_emit ((inst), (dreg), (sreg)); \
2630 *(inst)++ = (unsigned char)mask; \
2633 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
2635 x86_codegen_pre(&(inst), 5); \
2636 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
2637 x86_imm_emit8 ((inst), (imm)); \
2640 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
2642 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \