2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 // x86 register numbers
33 // opcodes for alu instructions
47 // opcodes for shift instructions
62 // opcodes for floating-point instructions
76 // integer conditions codes
79 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
80 X86_CC_NE = 1, X86_CC_NZ = 1,
81 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
82 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
83 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
84 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
85 X86_CC_LZ = 6, X86_CC_S = 6,
86 X86_CC_GEZ = 7, X86_CC_NS = 7,
87 X86_CC_P = 8, X86_CC_PE = 8,
88 X86_CC_NP = 9, X86_CC_PO = 9,
100 X86_FP_CC_MASK = 0x4500
103 /* FP control word */
105 X86_FPCW_INVOPEX_MASK = 0x1,
106 X86_FPCW_DENOPEX_MASK = 0x2,
107 X86_FPCW_ZERODIV_MASK = 0x4,
108 X86_FPCW_OVFEX_MASK = 0x8,
109 X86_FPCW_UNDFEX_MASK = 0x10,
110 X86_FPCW_PRECEX_MASK = 0x20,
111 X86_FPCW_PRECC_MASK = 0x300,
112 X86_FPCW_ROUNDC_MASK = 0xc00,
114 /* values for precision control */
115 X86_FPCW_PREC_SINGLE = 0,
116 X86_FPCW_PREC_DOUBLE = 0x200,
117 X86_FPCW_PREC_EXTENDED = 0x300,
119 /* values for rounding control */
120 X86_FPCW_ROUND_NEAREST = 0,
121 X86_FPCW_ROUND_DOWN = 0x400,
122 X86_FPCW_ROUND_UP = 0x800,
123 X86_FPCW_ROUND_TOZERO = 0xc00
130 X86_LOCK_PREFIX = 0xF0,
131 X86_REPNZ_PREFIX = 0xF2,
132 X86_REPZ_PREFIX = 0xF3,
133 X86_REP_PREFIX = 0xF3,
134 X86_CS_PREFIX = 0x2E,
135 X86_SS_PREFIX = 0x36,
136 X86_DS_PREFIX = 0x3E,
137 X86_ES_PREFIX = 0x26,
138 X86_FS_PREFIX = 0x64,
139 X86_GS_PREFIX = 0x65,
140 X86_UNLIKELY_PREFIX = 0x2E,
141 X86_LIKELY_PREFIX = 0x3E,
142 X86_OPERAND_PREFIX = 0x66,
143 X86_ADDRESS_PREFIX = 0x67
146 static const unsigned char
147 x86_cc_unsigned_map [X86_NCC] = {
162 static const unsigned char
163 x86_cc_signed_map [X86_NCC] = {
183 #define X86_NOBASEREG (-1)
186 // bitvector mask for callee-saved registers
188 #define X86_ESI_MASK (1<<X86_ESI)
189 #define X86_EDI_MASK (1<<X86_EDI)
190 #define X86_EBX_MASK (1<<X86_EBX)
191 #define X86_EBP_MASK (1<<X86_EBP)
193 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
194 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
195 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
197 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
198 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
200 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
205 // +--------------------------------+
206 // | in_arg[0] = var[0] |
207 // | in_arg[1] = var[1] |
209 // | in_arg[n_arg-1] = var[n_arg-1] |
210 // +--------------------------------+
212 // +--------------------------------+
213 // | saved EBP | <-- frame pointer (EBP)
214 // +--------------------------------+
216 // +--------------------------------+
218 // | var[n_arg+1] | local variables area
221 // +--------------------------------+
224 // | spill area | area for spilling mimic stack
226 // +--------------------------------|
228 // | ebp [ESP_Frame only] |
229 // | esi | 0..3 callee-saved regs
230 // | edi | <-- stack pointer (ESP)
231 // +--------------------------------+
233 // | stk1 | operand stack area/
234 // | . . . | out args
236 // +--------------------------------|
243 * useful building blocks
245 #define x86_modrm_mod(modrm) ((modrm) >> 6)
246 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
247 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
249 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
250 #define x86_imm_emit32(inst,imm) \
252 x86_imm_buf imb; imb.val = (int) (imm); \
253 *(inst)++ = imb.b [0]; \
254 *(inst)++ = imb.b [1]; \
255 *(inst)++ = imb.b [2]; \
256 *(inst)++ = imb.b [3]; \
258 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
259 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
260 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
261 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
263 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
264 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
265 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
266 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
268 #define x86_membase_emit(inst,r,basereg,disp) do {\
269 if ((basereg) == X86_ESP) { \
271 x86_address_byte ((inst), 0, (r), X86_ESP); \
272 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
273 } else if (x86_is_imm8((disp))) { \
274 x86_address_byte ((inst), 1, (r), X86_ESP); \
275 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
276 x86_imm_emit8 ((inst), (disp)); \
278 x86_address_byte ((inst), 2, (r), X86_ESP); \
279 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
280 x86_imm_emit32 ((inst), (disp)); \
284 if ((disp) == 0 && (basereg) != X86_EBP) { \
285 x86_address_byte ((inst), 0, (r), (basereg)); \
288 if (x86_is_imm8((disp))) { \
289 x86_address_byte ((inst), 1, (r), (basereg)); \
290 x86_imm_emit8 ((inst), (disp)); \
292 x86_address_byte ((inst), 2, (r), (basereg)); \
293 x86_imm_emit32 ((inst), (disp)); \
297 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
299 if ((basereg) == X86_NOBASEREG) { \
300 x86_address_byte ((inst), 0, (r), 4); \
301 x86_address_byte ((inst), (shift), (indexreg), 5); \
302 x86_imm_emit32 ((inst), (disp)); \
303 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
304 x86_address_byte ((inst), 0, (r), 4); \
305 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
306 } else if (x86_is_imm8((disp))) { \
307 x86_address_byte ((inst), 1, (r), 4); \
308 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
309 x86_imm_emit8 ((inst), (disp)); \
311 x86_address_byte ((inst), 2, (r), 4); \
312 x86_address_byte ((inst), (shift), (indexreg), 5); \
313 x86_imm_emit32 ((inst), (disp)); \
318 * target is the position in the code where to jump to:
320 * .. output loop code...
321 * x86_mov_reg_imm (code, X86_EAX, 0);
323 * x86_loop (code, -1);
327 * x86_patch (loop, target);
329 * ins should point at the start of the instruction that encodes a target.
330 * the instruction is inspected for validity and the correct displacement
333 #define x86_patch(ins,target) \
335 unsigned char* pos = (ins) + 1; \
336 int disp, size = 0; \
337 switch (*(unsigned char*)(ins)) { \
338 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
339 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
340 ++size; ++pos; break; /* prefix for 32-bit disp */ \
341 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
342 case 0xeb: /* jump8 */ \
343 /* conditional jump opcodes */ \
344 case 0x70: case 0x71: case 0x72: case 0x73: \
345 case 0x74: case 0x75: case 0x76: case 0x77: \
346 case 0x78: case 0x79: case 0x7a: case 0x7b: \
347 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
349 default: assert (0); \
351 disp = (target) - pos; \
352 if (size) x86_imm_emit32 (pos, disp - 4); \
353 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
357 #define x86_breakpoint(inst) \
362 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
363 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
364 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
365 #define x86_stosd(inst) x86_stosl((inst))
366 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
367 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
368 #define x86_movsd(inst) x86_movsl((inst))
370 #define x86_prefix(inst,p) do { *(inst)++ =(unsigned char) (p); } while (0)
372 #define x86_rdtsc(inst) \
378 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
380 *(inst)++ = (unsigned char)0x0f; \
381 *(inst)++ = (unsigned char)0xb1; \
382 x86_reg_emit ((inst), (reg), (dreg)); \
385 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
387 *(inst)++ = (unsigned char)0x0f; \
388 *(inst)++ = (unsigned char)0xb1; \
389 x86_mem_emit ((inst), (reg), (mem)); \
392 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
394 *(inst)++ = (unsigned char)0x0f; \
395 *(inst)++ = (unsigned char)0xb1; \
396 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
399 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
402 *(inst)++ = (unsigned char)0x86; \
404 *(inst)++ = (unsigned char)0x87; \
405 x86_reg_emit ((inst), (reg), (dreg)); \
408 #define x86_xchg_mem_reg(inst,mem,reg,size) \
411 *(inst)++ = (unsigned char)0x86; \
413 *(inst)++ = (unsigned char)0x87; \
414 x86_mem_emit ((inst), (reg), (mem)); \
417 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
420 *(inst)++ = (unsigned char)0x86; \
422 *(inst)++ = (unsigned char)0x87; \
423 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
426 #define x86_inc_mem(inst,mem) \
428 *(inst)++ = (unsigned char)0xff; \
429 x86_mem_emit ((inst), 0, (mem)); \
432 #define x86_inc_membase(inst,basereg,disp) \
434 *(inst)++ = (unsigned char)0xff; \
435 x86_membase_emit ((inst), 0, (basereg), (disp)); \
438 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
440 #define x86_dec_mem(inst,mem) \
442 *(inst)++ = (unsigned char)0xff; \
443 x86_mem_emit ((inst), 1, (mem)); \
446 #define x86_dec_membase(inst,basereg,disp) \
448 *(inst)++ = (unsigned char)0xff; \
449 x86_membase_emit ((inst), 1, (basereg), (disp)); \
452 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
454 #define x86_not_mem(inst,mem) \
456 *(inst)++ = (unsigned char)0xf7; \
457 x86_mem_emit ((inst), 2, (mem)); \
460 #define x86_not_membase(inst,basereg,disp) \
462 *(inst)++ = (unsigned char)0xf7; \
463 x86_membase_emit ((inst), 2, (basereg), (disp)); \
466 #define x86_not_reg(inst,reg) \
468 *(inst)++ = (unsigned char)0xf7; \
469 x86_reg_emit ((inst), 2, (reg)); \
472 #define x86_neg_mem(inst,mem) \
474 *(inst)++ = (unsigned char)0xf7; \
475 x86_mem_emit ((inst), 3, (mem)); \
478 #define x86_neg_membase(inst,basereg,disp) \
480 *(inst)++ = (unsigned char)0xf7; \
481 x86_membase_emit ((inst), 3, (basereg), (disp)); \
484 #define x86_neg_reg(inst,reg) \
486 *(inst)++ = (unsigned char)0xf7; \
487 x86_reg_emit ((inst), 3, (reg)); \
490 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
492 #define x86_alu_reg_imm(inst,opc,reg,imm) \
494 if ((reg) == X86_EAX) { \
495 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
496 x86_imm_emit32 ((inst), (imm)); \
499 if (x86_is_imm8((imm))) { \
500 *(inst)++ = (unsigned char)0x83; \
501 x86_reg_emit ((inst), (opc), (reg)); \
502 x86_imm_emit8 ((inst), (imm)); \
504 *(inst)++ = (unsigned char)0x81; \
505 x86_reg_emit ((inst), (opc), (reg)); \
506 x86_imm_emit32 ((inst), (imm)); \
510 #define x86_alu_mem_imm(inst,opc,mem,imm) \
512 if (x86_is_imm8((imm))) { \
513 *(inst)++ = (unsigned char)0x83; \
514 x86_mem_emit ((inst), (opc), (mem)); \
515 x86_imm_emit8 ((inst), (imm)); \
517 *(inst)++ = (unsigned char)0x81; \
518 x86_mem_emit ((inst), (opc), (mem)); \
519 x86_imm_emit32 ((inst), (imm)); \
523 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
525 if (x86_is_imm8((imm))) { \
526 *(inst)++ = (unsigned char)0x83; \
527 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
528 x86_imm_emit8 ((inst), (imm)); \
530 *(inst)++ = (unsigned char)0x81; \
531 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
532 x86_imm_emit32 ((inst), (imm)); \
536 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
538 *(inst)++ = (unsigned char)0x80; \
539 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
540 x86_imm_emit8 ((inst), (imm)); \
543 #define x86_alu_mem_reg(inst,opc,mem,reg) \
545 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
546 x86_mem_emit ((inst), (reg), (mem)); \
549 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
551 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
552 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
555 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
557 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
558 x86_reg_emit ((inst), (dreg), (reg)); \
562 * @x86_alu_reg8_reg8:
563 * Supports ALU operations between two 8-bit registers.
564 * dreg := dreg opc reg
565 * X86_Reg_No enum is used to specify the registers.
566 * Additionally is_*_h flags are used to specify what part
567 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
568 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
570 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
572 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
573 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
576 #define x86_alu_reg_mem(inst,opc,reg,mem) \
578 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
579 x86_mem_emit ((inst), (reg), (mem)); \
582 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
584 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
585 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
588 #define x86_test_reg_imm(inst,reg,imm) \
590 if ((reg) == X86_EAX) { \
591 *(inst)++ = (unsigned char)0xa9; \
593 *(inst)++ = (unsigned char)0xf7; \
594 x86_reg_emit ((inst), 0, (reg)); \
596 x86_imm_emit32 ((inst), (imm)); \
599 #define x86_test_mem_imm(inst,mem,imm) \
601 *(inst)++ = (unsigned char)0xf7; \
602 x86_mem_emit ((inst), 0, (mem)); \
603 x86_imm_emit32 ((inst), (imm)); \
606 #define x86_test_membase_imm(inst,basereg,disp,imm) \
608 *(inst)++ = (unsigned char)0xf7; \
609 x86_membase_emit ((inst), 0, (basereg), (disp)); \
610 x86_imm_emit32 ((inst), (imm)); \
613 #define x86_test_reg_reg(inst,dreg,reg) \
615 *(inst)++ = (unsigned char)0x85; \
616 x86_reg_emit ((inst), (reg), (dreg)); \
619 #define x86_test_mem_reg(inst,mem,reg) \
621 *(inst)++ = (unsigned char)0x85; \
622 x86_mem_emit ((inst), (reg), (mem)); \
625 #define x86_test_membase_reg(inst,basereg,disp,reg) \
627 *(inst)++ = (unsigned char)0x85; \
628 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
631 #define x86_shift_reg_imm(inst,opc,reg,imm) \
634 *(inst)++ = (unsigned char)0xd1; \
635 x86_reg_emit ((inst), (opc), (reg)); \
637 *(inst)++ = (unsigned char)0xc1; \
638 x86_reg_emit ((inst), (opc), (reg)); \
639 x86_imm_emit8 ((inst), (imm)); \
643 #define x86_shift_mem_imm(inst,opc,mem,imm) \
646 *(inst)++ = (unsigned char)0xd1; \
647 x86_mem_emit ((inst), (opc), (mem)); \
649 *(inst)++ = (unsigned char)0xc1; \
650 x86_mem_emit ((inst), (opc), (mem)); \
651 x86_imm_emit8 ((inst), (imm)); \
655 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
658 *(inst)++ = (unsigned char)0xd1; \
659 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
661 *(inst)++ = (unsigned char)0xc1; \
662 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
663 x86_imm_emit8 ((inst), (imm)); \
667 #define x86_shift_reg(inst,opc,reg) \
669 *(inst)++ = (unsigned char)0xd3; \
670 x86_reg_emit ((inst), (opc), (reg)); \
673 #define x86_shift_mem(inst,opc,mem) \
675 *(inst)++ = (unsigned char)0xd3; \
676 x86_mem_emit ((inst), (opc), (mem)); \
679 #define x86_shift_membase(inst,opc,basereg,disp) \
681 *(inst)++ = (unsigned char)0xd3; \
682 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
686 * Multi op shift missing.
689 #define x86_shrd_reg(inst,dreg,reg) \
691 *(inst)++ = (unsigned char)0x0f; \
692 *(inst)++ = (unsigned char)0xad; \
693 x86_reg_emit ((inst), (reg), (dreg)); \
696 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
698 *(inst)++ = (unsigned char)0x0f; \
699 *(inst)++ = (unsigned char)0xac; \
700 x86_reg_emit ((inst), (reg), (dreg)); \
701 x86_imm_emit8 ((inst), (shamt)); \
704 #define x86_shld_reg(inst,dreg,reg) \
706 *(inst)++ = (unsigned char)0x0f; \
707 *(inst)++ = (unsigned char)0xa5; \
708 x86_reg_emit ((inst), (reg), (dreg)); \
711 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
713 *(inst)++ = (unsigned char)0x0f; \
714 *(inst)++ = (unsigned char)0xa4; \
715 x86_reg_emit ((inst), (reg), (dreg)); \
716 x86_imm_emit8 ((inst), (shamt)); \
722 #define x86_mul_reg(inst,reg,is_signed) \
724 *(inst)++ = (unsigned char)0xf7; \
725 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
728 #define x86_mul_mem(inst,mem,is_signed) \
730 *(inst)++ = (unsigned char)0xf7; \
731 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
734 #define x86_mul_membase(inst,basereg,disp,is_signed) \
736 *(inst)++ = (unsigned char)0xf7; \
737 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
743 #define x86_imul_reg_reg(inst,dreg,reg) \
745 *(inst)++ = (unsigned char)0x0f; \
746 *(inst)++ = (unsigned char)0xaf; \
747 x86_reg_emit ((inst), (dreg), (reg)); \
750 #define x86_imul_reg_mem(inst,reg,mem) \
752 *(inst)++ = (unsigned char)0x0f; \
753 *(inst)++ = (unsigned char)0xaf; \
754 x86_mem_emit ((inst), (reg), (mem)); \
757 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
759 *(inst)++ = (unsigned char)0x0f; \
760 *(inst)++ = (unsigned char)0xaf; \
761 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
767 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
769 if (x86_is_imm8 ((imm))) { \
770 *(inst)++ = (unsigned char)0x6b; \
771 x86_reg_emit ((inst), (dreg), (reg)); \
772 x86_imm_emit8 ((inst), (imm)); \
774 *(inst)++ = (unsigned char)0x69; \
775 x86_reg_emit ((inst), (dreg), (reg)); \
776 x86_imm_emit32 ((inst), (imm)); \
780 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
782 if (x86_is_imm8 ((imm))) { \
783 *(inst)++ = (unsigned char)0x6b; \
784 x86_mem_emit ((inst), (reg), (mem)); \
785 x86_imm_emit8 ((inst), (imm)); \
787 *(inst)++ = (unsigned char)0x69; \
788 x86_reg_emit ((inst), (reg), (mem)); \
789 x86_imm_emit32 ((inst), (imm)); \
793 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
795 if (x86_is_imm8 ((imm))) { \
796 *(inst)++ = (unsigned char)0x6b; \
797 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
798 x86_imm_emit8 ((inst), (imm)); \
800 *(inst)++ = (unsigned char)0x69; \
801 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
802 x86_imm_emit32 ((inst), (imm)); \
807 * divide EDX:EAX by rm;
808 * eax = quotient, edx = remainder
811 #define x86_div_reg(inst,reg,is_signed) \
813 *(inst)++ = (unsigned char)0xf7; \
814 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
817 #define x86_div_mem(inst,mem,is_signed) \
819 *(inst)++ = (unsigned char)0xf7; \
820 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
823 #define x86_div_membase(inst,basereg,disp,is_signed) \
825 *(inst)++ = (unsigned char)0xf7; \
826 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
829 #define x86_mov_mem_reg(inst,mem,reg,size) \
832 case 1: *(inst)++ = (unsigned char)0x88; break; \
833 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
834 case 4: *(inst)++ = (unsigned char)0x89; break; \
835 default: assert (0); \
837 x86_mem_emit ((inst), (reg), (mem)); \
840 #define x86_mov_regp_reg(inst,regp,reg,size) \
843 case 1: *(inst)++ = (unsigned char)0x88; break; \
844 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
845 case 4: *(inst)++ = (unsigned char)0x89; break; \
846 default: assert (0); \
848 x86_regp_emit ((inst), (reg), (regp)); \
851 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
854 case 1: *(inst)++ = (unsigned char)0x88; break; \
855 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
856 case 4: *(inst)++ = (unsigned char)0x89; break; \
857 default: assert (0); \
859 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
862 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
865 case 1: *(inst)++ = (unsigned char)0x88; break; \
866 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
867 case 4: *(inst)++ = (unsigned char)0x89; break; \
868 default: assert (0); \
870 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
873 #define x86_mov_reg_reg(inst,dreg,reg,size) \
876 case 1: *(inst)++ = (unsigned char)0x8a; break; \
877 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
878 case 4: *(inst)++ = (unsigned char)0x8b; break; \
879 default: assert (0); \
881 x86_reg_emit ((inst), (dreg), (reg)); \
884 #define x86_mov_reg_mem(inst,reg,mem,size) \
887 case 1: *(inst)++ = (unsigned char)0x8a; break; \
888 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
889 case 4: *(inst)++ = (unsigned char)0x8b; break; \
890 default: assert (0); \
892 x86_mem_emit ((inst), (reg), (mem)); \
895 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
898 case 1: *(inst)++ = (unsigned char)0x8a; break; \
899 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
900 case 4: *(inst)++ = (unsigned char)0x8b; break; \
901 default: assert (0); \
903 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
906 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
909 case 1: *(inst)++ = (unsigned char)0x8a; break; \
910 case 2: *(inst)++ = (unsigned char)0x66; /* fall through */ \
911 case 4: *(inst)++ = (unsigned char)0x8b; break; \
912 default: assert (0); \
914 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
918 * Note: x86_clear_reg () chacnges the condition code!
920 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
922 #define x86_mov_reg_imm(inst,reg,imm) \
924 *(inst)++ = (unsigned char)0xb8 + (reg); \
925 x86_imm_emit32 ((inst), (imm)); \
928 #define x86_mov_mem_imm(inst,mem,imm,size) \
931 *(inst)++ = (unsigned char)0xc6; \
932 x86_mem_emit ((inst), 0, (mem)); \
933 x86_imm_emit8 ((inst), (imm)); \
934 } else if ((size) == 2) { \
935 *(inst)++ = (unsigned char)0x66; \
936 *(inst)++ = (unsigned char)0xc7; \
937 x86_mem_emit ((inst), 0, (mem)); \
938 x86_imm_emit16 ((inst), (imm)); \
940 *(inst)++ = (unsigned char)0xc7; \
941 x86_mem_emit ((inst), 0, (mem)); \
942 x86_imm_emit32 ((inst), (imm)); \
946 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
949 *(inst)++ = (unsigned char)0xc6; \
950 x86_membase_emit ((inst), 0, (basereg), (disp)); \
951 x86_imm_emit8 ((inst), (imm)); \
952 } else if ((size) == 2) { \
953 *(inst)++ = (unsigned char)0x66; \
954 *(inst)++ = (unsigned char)0xc7; \
955 x86_membase_emit ((inst), 0, (basereg), (disp)); \
956 x86_imm_emit16 ((inst), (imm)); \
958 *(inst)++ = (unsigned char)0xc7; \
959 x86_membase_emit ((inst), 0, (basereg), (disp)); \
960 x86_imm_emit32 ((inst), (imm)); \
964 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
967 *(inst)++ = (unsigned char)0xc6; \
968 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
969 x86_imm_emit8 ((inst), (imm)); \
970 } else if ((size) == 2) { \
971 *(inst)++ = (unsigned char)0x66; \
972 *(inst)++ = (unsigned char)0xc7; \
973 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
974 x86_imm_emit16 ((inst), (imm)); \
976 *(inst)++ = (unsigned char)0xc7; \
977 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
978 x86_imm_emit32 ((inst), (imm)); \
982 #define x86_lea_mem(inst,reg,mem) \
984 *(inst)++ = (unsigned char)0x8d; \
985 x86_mem_emit ((inst), (reg), (mem)); \
988 #define x86_lea_membase(inst,reg,basereg,disp) \
990 *(inst)++ = (unsigned char)0x8d; \
991 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
994 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
996 *(inst)++ = (unsigned char)0x8d; \
997 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1000 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1002 unsigned char op = 0xb6; \
1003 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1004 *(inst)++ = (unsigned char)0x0f; \
1005 if ((is_signed)) op += 0x08; \
1006 if ((is_half)) op += 0x01; \
1008 x86_reg_emit ((inst), (dreg), (reg)); \
1011 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1013 unsigned char op = 0xb6; \
1014 *(inst)++ = (unsigned char)0x0f; \
1015 if ((is_signed)) op += 0x08; \
1016 if ((is_half)) op += 0x01; \
1018 x86_mem_emit ((inst), (dreg), (mem)); \
1021 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1023 unsigned char op = 0xb6; \
1024 *(inst)++ = (unsigned char)0x0f; \
1025 if ((is_signed)) op += 0x08; \
1026 if ((is_half)) op += 0x01; \
1028 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1031 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1033 unsigned char op = 0xb6; \
1034 *(inst)++ = (unsigned char)0x0f; \
1035 if ((is_signed)) op += 0x08; \
1036 if ((is_half)) op += 0x01; \
1038 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1041 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1042 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1044 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1046 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1047 x86_mem_emit ((inst), (opc), (mem)); \
1050 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1052 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1053 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1056 #define x86_fp_op(inst,opc,index) \
1058 *(inst)++ = (unsigned char)0xd8; \
1059 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1062 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1064 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1065 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1066 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1070 * @x86_fp_int_op_membase
1071 * Supports FPU operations between ST(0) and integer operand in memory.
1072 * Operation encoded using X86_FP_Opcode enum.
1073 * Operand is addressed by [basereg + disp].
1074 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1076 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1078 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1079 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1082 #define x86_fstp(inst,index) \
1084 *(inst)++ = (unsigned char)0xdd; \
1085 *(inst)++ = (unsigned char)0xd8+(index); \
1088 #define x86_fcompp(inst) \
1090 *(inst)++ = (unsigned char)0xde; \
1091 *(inst)++ = (unsigned char)0xd9; \
1094 #define x86_fucompp(inst) \
1096 *(inst)++ = (unsigned char)0xda; \
1097 *(inst)++ = (unsigned char)0xe9; \
1100 #define x86_fnstsw(inst) \
1102 *(inst)++ = (unsigned char)0xdf; \
1103 *(inst)++ = (unsigned char)0xe0; \
1106 #define x86_fnstcw(inst,mem) \
1108 *(inst)++ = (unsigned char)0xd9; \
1109 x86_mem_emit ((inst), 7, (mem)); \
1112 #define x86_fnstcw_membase(inst,basereg,disp) \
1114 *(inst)++ = (unsigned char)0xd9; \
1115 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1118 #define x86_fldcw(inst,mem) \
1120 *(inst)++ = (unsigned char)0xd9; \
1121 x86_mem_emit ((inst), 5, (mem)); \
1124 #define x86_fldcw_membase(inst,basereg,disp) \
1126 *(inst)++ = (unsigned char)0xd9; \
1127 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1130 #define x86_fchs(inst) \
1132 *(inst)++ = (unsigned char)0xd9; \
1133 *(inst)++ = (unsigned char)0xe0; \
1136 #define x86_frem(inst) \
1138 *(inst)++ = (unsigned char)0xd9; \
1139 *(inst)++ = (unsigned char)0xf8; \
1142 #define x86_fxch(inst,index) \
1144 *(inst)++ = (unsigned char)0xd9; \
1145 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1148 #define x86_fcomi(inst,index) \
1150 *(inst)++ = (unsigned char)0xdb; \
1151 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1154 #define x86_fcomip(inst,index) \
1156 *(inst)++ = (unsigned char)0xdf; \
1157 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1160 #define x86_fucomi(inst,index) \
1162 *(inst)++ = (unsigned char)0xdb; \
1163 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1166 #define x86_fucomip(inst,index) \
1168 *(inst)++ = (unsigned char)0xdf; \
1169 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1172 #define x86_fld(inst,mem,is_double) \
1174 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1175 x86_mem_emit ((inst), 0, (mem)); \
1178 #define x86_fld_membase(inst,basereg,disp,is_double) \
1180 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1181 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1184 #define x86_fld80_mem(inst,mem) \
1186 *(inst)++ = (unsigned char)0xdb; \
1187 x86_mem_emit ((inst), 5, (mem)); \
1190 #define x86_fld80_membase(inst,basereg,disp) \
1192 *(inst)++ = (unsigned char)0xdb; \
1193 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1196 #define x86_fild(inst,mem,is_long) \
1199 *(inst)++ = (unsigned char)0xdf; \
1200 x86_mem_emit ((inst), 5, (mem)); \
1202 *(inst)++ = (unsigned char)0xdb; \
1203 x86_mem_emit ((inst), 0, (mem)); \
1207 #define x86_fild_membase(inst,basereg,disp,is_long) \
1210 *(inst)++ = (unsigned char)0xdf; \
1211 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1213 *(inst)++ = (unsigned char)0xdb; \
1214 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1218 #define x86_fld_reg(inst,index) \
1220 *(inst)++ = (unsigned char)0xd9; \
1221 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1224 #define x86_fldz(inst) \
1226 *(inst)++ = (unsigned char)0xd9; \
1227 *(inst)++ = (unsigned char)0xee; \
1230 #define x86_fld1(inst) \
1232 *(inst)++ = (unsigned char)0xd9; \
1233 *(inst)++ = (unsigned char)0xe8; \
1236 #define x86_fldpi(inst) \
1238 *(inst)++ = (unsigned char)0xd9; \
1239 *(inst)++ = (unsigned char)0xeb; \
1242 #define x86_fst(inst,mem,is_double,pop_stack) \
1244 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1245 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1248 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1250 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1251 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1254 #define x86_fst80_mem(inst,mem) \
1256 *(inst)++ = (unsigned char)0xdb; \
1257 x86_mem_emit ((inst), 7, (mem)); \
1261 #define x86_fst80_membase(inst,basereg,disp) \
1263 *(inst)++ = (unsigned char)0xdb; \
1264 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1268 #define x86_fist_pop(inst,mem,is_long) \
1271 *(inst)++ = (unsigned char)0xdf; \
1272 x86_mem_emit ((inst), 7, (mem)); \
1274 *(inst)++ = (unsigned char)0xdb; \
1275 x86_mem_emit ((inst), 3, (mem)); \
1279 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1282 *(inst)++ = (unsigned char)0xdf; \
1283 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1285 *(inst)++ = (unsigned char)0xdb; \
1286 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1290 #define x86_fstsw(inst) \
1292 *(inst)++ = (unsigned char)0x9b; \
1293 *(inst)++ = (unsigned char)0xdf; \
1294 *(inst)++ = (unsigned char)0xe0; \
1299 * Converts content of ST(0) to integer and stores it at memory location
1300 * addressed by [basereg + disp].
1301 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1303 #define x86_fist_membase(inst,basereg,disp,is_int) \
1306 *(inst)++ = (unsigned char)0xdb; \
1307 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1309 *(inst)++ = (unsigned char)0xdf; \
1310 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1315 #define x86_push_reg(inst,reg) \
1317 *(inst)++ = (unsigned char)0x50 + (reg); \
1320 #define x86_push_regp(inst,reg) \
1322 *(inst)++ = (unsigned char)0xff; \
1323 x86_regp_emit ((inst), 6, (reg)); \
1326 #define x86_push_mem(inst,mem) \
1328 *(inst)++ = (unsigned char)0xff; \
1329 x86_mem_emit ((inst), 6, (mem)); \
1332 #define x86_push_membase(inst,basereg,disp) \
1334 *(inst)++ = (unsigned char)0xff; \
1335 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1338 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1340 *(inst)++ = (unsigned char)0xff; \
1341 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1344 #define x86_push_imm(inst,imm) \
1346 *(inst)++ = (unsigned char)0x68; \
1347 x86_imm_emit32 ((inst), (imm)); \
1350 #define x86_pop_reg(inst,reg) \
1352 *(inst)++ = (unsigned char)0x58 + (reg); \
1355 #define x86_pop_mem(inst,mem) \
1357 *(inst)++ = (unsigned char)0x87; \
1358 x86_mem_emit ((inst), 0, (mem)); \
1361 #define x86_pop_membase(inst,basereg,disp) \
1363 *(inst)++ = (unsigned char)0x87; \
1364 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1367 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1368 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1369 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1370 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1372 #define x86_loop(inst,imm) \
1374 *(inst)++ = (unsigned char)0xe2; \
1375 x86_imm_emit8 ((inst), (imm)); \
1378 #define x86_loope(inst,imm) \
1380 *(inst)++ = (unsigned char)0xe1; \
1381 x86_imm_emit8 ((inst), (imm)); \
1384 #define x86_loopne(inst,imm) \
1386 *(inst)++ = (unsigned char)0xe0; \
1387 x86_imm_emit8 ((inst), (imm)); \
1390 #define x86_jump32(inst,imm) \
1392 *(inst)++ = (unsigned char)0xe9; \
1393 x86_imm_emit32 ((inst), (imm)); \
1396 #define x86_jump8(inst,imm) \
1398 *(inst)++ = (unsigned char)0xeb; \
1399 x86_imm_emit8 ((inst), (imm)); \
1402 #define x86_jump_reg(inst,reg) \
1404 *(inst)++ = (unsigned char)0xff; \
1405 x86_reg_emit ((inst), 4, (reg)); \
1408 #define x86_jump_mem(inst,mem) \
1410 *(inst)++ = (unsigned char)0xff; \
1411 x86_mem_emit ((inst), 4, (mem)); \
1414 #define x86_jump_membase(inst,basereg,disp) \
1416 *(inst)++ = (unsigned char)0xff; \
1417 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1421 * target is a pointer in our buffer.
1423 #define x86_jump_code(inst,target) \
1425 int t = (unsigned char*)(target) - (inst) - 2; \
1426 if (x86_is_imm8(t)) { \
1427 x86_jump8 ((inst), t); \
1430 x86_jump32 ((inst), t); \
1434 #define x86_jump_disp(inst,disp) \
1436 int t = (disp) - 2; \
1437 if (x86_is_imm8(t)) { \
1438 x86_jump8 ((inst), t); \
1441 x86_jump32 ((inst), t); \
1445 #define x86_branch8(inst,cond,imm,is_signed) \
1448 *(inst)++ = x86_cc_signed_map [(cond)]; \
1450 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1451 x86_imm_emit8 ((inst), (imm)); \
1454 #define x86_branch32(inst,cond,imm,is_signed) \
1456 *(inst)++ = (unsigned char)0x0f; \
1458 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1460 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1461 x86_imm_emit32 ((inst), (imm)); \
1464 #define x86_branch(inst,cond,target,is_signed) \
1466 int offset = (target) - (inst) - 2; \
1467 if (x86_is_imm8 ((offset))) \
1468 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1471 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1475 #define x86_branch_disp(inst,cond,disp,is_signed) \
1477 int offset = (disp) - 2; \
1478 if (x86_is_imm8 ((offset))) \
1479 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1482 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1486 #define x86_set_reg(inst,cond,reg,is_signed) \
1488 g_assert (X86_IS_BYTE_REG (reg)); \
1489 *(inst)++ = (unsigned char)0x0f; \
1491 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1493 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1494 x86_reg_emit ((inst), 0, (reg)); \
1497 #define x86_set_mem(inst,cond,mem,is_signed) \
1499 *(inst)++ = (unsigned char)0x0f; \
1501 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1503 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1504 x86_mem_emit ((inst), 0, (mem)); \
1507 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
1509 *(inst)++ = (unsigned char)0x0f; \
1511 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1513 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1514 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1517 #define x86_call_imm(inst,disp) \
1519 *(inst)++ = (unsigned char)0xe8; \
1520 x86_imm_emit32 ((inst), (int)(disp)); \
1523 #define x86_call_reg(inst,reg) \
1525 *(inst)++ = (unsigned char)0xff; \
1526 x86_reg_emit ((inst), 2, (reg)); \
1529 #define x86_call_mem(inst,mem) \
1531 *(inst)++ = (unsigned char)0xff; \
1532 x86_mem_emit ((inst), 2, (mem)); \
1535 #define x86_call_membase(inst,basereg,disp) \
1537 *(inst)++ = (unsigned char)0xff; \
1538 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1541 #define x86_call_code(inst,target) \
1543 int _x86_offset = (unsigned char*)(target) - (inst); \
1545 x86_call_imm ((inst), _x86_offset); \
1548 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
1550 #define x86_ret_imm(inst,imm) \
1555 *(inst)++ = (unsigned char)0xc2; \
1556 x86_imm_emit16 ((inst), (imm)); \
1560 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
1562 *(inst)++ = (unsigned char) 0x0f; \
1564 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1566 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1567 x86_reg_emit ((inst), (dreg), (reg)); \
1570 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
1572 *(inst)++ = (unsigned char) 0x0f; \
1574 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1576 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1577 x86_mem_emit ((inst), (reg), (mem)); \
1580 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
1582 *(inst)++ = (unsigned char) 0x0f; \
1584 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1586 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1587 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1590 #define x86_enter(inst,framesize) \
1592 *(inst)++ = (unsigned char)0xc8; \
1593 x86_imm_emit16 ((inst), (framesize)); \
1597 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
1598 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
1600 #define x86_fsin(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
1601 #define x86_fcos(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
1602 #define x86_fabs(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
1603 #define x86_ftst(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
1604 #define x86_fxam(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
1605 #define x86_fpatan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
1606 #define x86_fprem(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
1607 #define x86_fprem1(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
1608 #define x86_frndint(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
1609 #define x86_fsqrt(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
1610 #define x86_fptan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
1612 #define x86_padding(inst,size) \
1615 case 1: x86_nop ((inst)); break; \
1616 case 2: *(inst)++ = 0x8b; \
1617 *(inst)++ = 0xc0; break; \
1618 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
1619 *(inst)++ = 0x00; break; \
1620 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1621 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1623 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1624 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1625 x86_nop ((inst)); break; \
1626 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
1627 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1628 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1630 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
1631 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1632 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1633 *(inst)++ = 0x00; break; \
1634 default: assert (0); \
1638 #define x86_prolog(inst,frame_size,reg_mask) \
1640 unsigned i, m = 1; \
1641 x86_enter ((inst), (frame_size)); \
1642 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
1643 if ((reg_mask) & m) \
1644 x86_push_reg ((inst), i); \
1648 #define x86_epilog(inst,reg_mask) \
1650 unsigned i, m = 1 << X86_EDI; \
1651 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
1652 if ((reg_mask) & m) \
1653 x86_pop_reg ((inst), i); \
1655 x86_leave ((inst)); \