2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 #ifdef __native_client_codegen__
20 extern gint8 nacl_align_byte;
21 #endif /* __native_client_codegen__ */
24 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
25 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do { mono_nacl_align_inst(inst_ptr_ptr, inst_len); } while (0)
26 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
27 #define x86_call_sequence_post_val(inst) \
28 (mono_nacl_align_call(&_code_start, &(inst)), _code_start);
29 #define x86_call_sequence_pre(inst) x86_call_sequence_pre_val((inst))
30 #define x86_call_sequence_post(inst) x86_call_sequence_post_val((inst))
32 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do {} while (0)
33 /* Two variants are needed to avoid warnings */
34 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
35 #define x86_call_sequence_post_val(inst) _code_start
36 #define x86_call_sequence_pre(inst)
37 #define x86_call_sequence_post(inst)
38 #endif /* __native_client_codegen__ */
42 // x86 register numbers
69 // opcodes for alu instructions
83 // opcodes for shift instructions
98 // opcodes for floating-point instructions
112 // integer conditions codes
115 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
116 X86_CC_NE = 1, X86_CC_NZ = 1,
117 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
118 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
119 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
120 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
121 X86_CC_LZ = 6, X86_CC_S = 6,
122 X86_CC_GEZ = 7, X86_CC_NS = 7,
123 X86_CC_P = 8, X86_CC_PE = 8,
124 X86_CC_NP = 9, X86_CC_PO = 9,
136 X86_FP_CC_MASK = 0x4500
139 /* FP control word */
141 X86_FPCW_INVOPEX_MASK = 0x1,
142 X86_FPCW_DENOPEX_MASK = 0x2,
143 X86_FPCW_ZERODIV_MASK = 0x4,
144 X86_FPCW_OVFEX_MASK = 0x8,
145 X86_FPCW_UNDFEX_MASK = 0x10,
146 X86_FPCW_PRECEX_MASK = 0x20,
147 X86_FPCW_PRECC_MASK = 0x300,
148 X86_FPCW_ROUNDC_MASK = 0xc00,
150 /* values for precision control */
151 X86_FPCW_PREC_SINGLE = 0,
152 X86_FPCW_PREC_DOUBLE = 0x200,
153 X86_FPCW_PREC_EXTENDED = 0x300,
155 /* values for rounding control */
156 X86_FPCW_ROUND_NEAREST = 0,
157 X86_FPCW_ROUND_DOWN = 0x400,
158 X86_FPCW_ROUND_UP = 0x800,
159 X86_FPCW_ROUND_TOZERO = 0xc00
166 X86_LOCK_PREFIX = 0xF0,
167 X86_REPNZ_PREFIX = 0xF2,
168 X86_REPZ_PREFIX = 0xF3,
169 X86_REP_PREFIX = 0xF3,
170 X86_CS_PREFIX = 0x2E,
171 X86_SS_PREFIX = 0x36,
172 X86_DS_PREFIX = 0x3E,
173 X86_ES_PREFIX = 0x26,
174 X86_FS_PREFIX = 0x64,
175 X86_GS_PREFIX = 0x65,
176 X86_UNLIKELY_PREFIX = 0x2E,
177 X86_LIKELY_PREFIX = 0x3E,
178 X86_OPERAND_PREFIX = 0x66,
179 X86_ADDRESS_PREFIX = 0x67
182 static const unsigned char
183 x86_cc_unsigned_map [X86_NCC] = {
198 static const unsigned char
199 x86_cc_signed_map [X86_NCC] = {
219 #define X86_NOBASEREG (-1)
222 // bitvector mask for callee-saved registers
224 #define X86_ESI_MASK (1<<X86_ESI)
225 #define X86_EDI_MASK (1<<X86_EDI)
226 #define X86_EBX_MASK (1<<X86_EBX)
227 #define X86_EBP_MASK (1<<X86_EBP)
229 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
230 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
231 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
233 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
234 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
236 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
241 // +--------------------------------+
242 // | in_arg[0] = var[0] |
243 // | in_arg[1] = var[1] |
245 // | in_arg[n_arg-1] = var[n_arg-1] |
246 // +--------------------------------+
248 // +--------------------------------+
249 // | saved EBP | <-- frame pointer (EBP)
250 // +--------------------------------+
252 // +--------------------------------+
254 // | var[n_arg+1] | local variables area
257 // +--------------------------------+
260 // | spill area | area for spilling mimic stack
262 // +--------------------------------|
264 // | ebp [ESP_Frame only] |
265 // | esi | 0..3 callee-saved regs
266 // | edi | <-- stack pointer (ESP)
267 // +--------------------------------+
269 // | stk1 | operand stack area/
270 // | . . . | out args
272 // +--------------------------------|
279 * useful building blocks
281 #define x86_modrm_mod(modrm) ((modrm) >> 6)
282 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
283 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
285 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
286 #define x86_imm_emit32(inst,imm) \
288 x86_imm_buf imb; imb.val = (int) (imm); \
289 *(inst)++ = imb.b [0]; \
290 *(inst)++ = imb.b [1]; \
291 *(inst)++ = imb.b [2]; \
292 *(inst)++ = imb.b [3]; \
294 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
295 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
296 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
297 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
299 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
300 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
301 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
302 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
304 #define kMaxMembaseEmitPadding 6
306 #define x86_membase_emit_body(inst,r,basereg,disp) do {\
307 if ((basereg) == X86_ESP) { \
309 x86_address_byte ((inst), 0, (r), X86_ESP); \
310 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
311 } else if (x86_is_imm8((disp))) { \
312 x86_address_byte ((inst), 1, (r), X86_ESP); \
313 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
314 x86_imm_emit8 ((inst), (disp)); \
316 x86_address_byte ((inst), 2, (r), X86_ESP); \
317 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
318 x86_imm_emit32 ((inst), (disp)); \
322 if ((disp) == 0 && (basereg) != X86_EBP) { \
323 x86_address_byte ((inst), 0, (r), (basereg)); \
326 if (x86_is_imm8((disp))) { \
327 x86_address_byte ((inst), 1, (r), (basereg)); \
328 x86_imm_emit8 ((inst), (disp)); \
330 x86_address_byte ((inst), 2, (r), (basereg)); \
331 x86_imm_emit32 ((inst), (disp)); \
335 #if defined(__native_client_codegen__) && defined(TARGET_AMD64)
336 #define x86_membase_emit(inst,r,basereg,disp) \
338 amd64_nacl_membase_handler(&(inst), (basereg), (disp), (r)) ; \
340 #else /* __default_codegen__ || 32-bit NaCl codegen */
341 #define x86_membase_emit(inst,r,basereg,disp) \
343 x86_membase_emit_body((inst),(r),(basereg),(disp)); \
347 #define kMaxMemindexEmitPadding 6
349 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
351 if ((basereg) == X86_NOBASEREG) { \
352 x86_address_byte ((inst), 0, (r), 4); \
353 x86_address_byte ((inst), (shift), (indexreg), 5); \
354 x86_imm_emit32 ((inst), (disp)); \
355 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
356 x86_address_byte ((inst), 0, (r), 4); \
357 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
358 } else if (x86_is_imm8((disp))) { \
359 x86_address_byte ((inst), 1, (r), 4); \
360 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
361 x86_imm_emit8 ((inst), (disp)); \
363 x86_address_byte ((inst), 2, (r), 4); \
364 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
365 x86_imm_emit32 ((inst), (disp)); \
370 * target is the position in the code where to jump to:
372 * .. output loop code...
373 * x86_mov_reg_imm (code, X86_EAX, 0);
375 * x86_loop (code, -1);
379 * x86_patch (loop, target);
381 * ins should point at the start of the instruction that encodes a target.
382 * the instruction is inspected for validity and the correct displacement
385 #define x86_do_patch(ins,target) \
387 unsigned char* pos = (ins) + 1; \
388 int disp, size = 0; \
389 switch (*(unsigned char*)(ins)) { \
390 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
391 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
392 ++size; ++pos; break; /* prefix for 32-bit disp */ \
393 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
394 case 0xeb: /* jump8 */ \
395 /* conditional jump opcodes */ \
396 case 0x70: case 0x71: case 0x72: case 0x73: \
397 case 0x74: case 0x75: case 0x76: case 0x77: \
398 case 0x78: case 0x79: case 0x7a: case 0x7b: \
399 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
401 default: assert (0); \
403 disp = (target) - pos; \
404 if (size) x86_imm_emit32 (pos, disp - 4); \
405 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
409 #if defined( __native_client_codegen__ ) && defined(TARGET_X86)
411 #define x86_skip_nops(inst) \
416 if (inst[0] == 0x90) { \
420 if (inst[0] == 0x8b && inst[1] == 0xc0) { \
424 if (inst[0] == 0x8d && inst[1] == 0x6d \
425 && inst[2] == 0x00) { \
429 if (inst[0] == 0x8d && inst[1] == 0x64 \
430 && inst[2] == 0x24 && inst[3] == 0x00) { \
434 /* skip inst+=5 case because it's the 4-byte + 1-byte case */ \
435 if (inst[0] == 0x8d && inst[1] == 0xad \
436 && inst[2] == 0x00 && inst[3] == 0x00 \
437 && inst[4] == 0x00 && inst[5] == 0x00) { \
441 if (inst[0] == 0x8d && inst[1] == 0xa4 \
442 && inst[2] == 0x24 && inst[3] == 0x00 \
443 && inst[4] == 0x00 && inst[5] == 0x00 \
444 && inst[6] == 0x00 ) { \
448 } while ( in_nop ); \
451 #if defined(__native_client__)
452 #define x86_patch(ins,target) \
454 unsigned char* inst = (ins); \
455 guint8* new_target = nacl_modify_patch_target((target)); \
456 x86_skip_nops((inst)); \
457 x86_do_patch((inst), new_target); \
459 #else /* __native_client__ */
460 #define x86_patch(ins,target) \
462 unsigned char* inst = (ins); \
463 guint8* new_target = (target); \
464 x86_skip_nops((inst)); \
465 x86_do_patch((inst), new_target); \
467 #endif /* __native_client__ */
470 #define x86_patch(ins,target) do { x86_do_patch((ins), (target)); } while (0)
471 #endif /* __native_client_codegen__ */
473 #ifdef __native_client_codegen__
474 /* The breakpoint instruction is illegal in Native Client, although the HALT */
475 /* instruction is allowed. The breakpoint is used several places in mini-x86.c */
476 /* and exceptions-x86.c. */
477 #define x86_breakpoint(inst) \
482 #define x86_breakpoint(inst) \
488 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
489 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
490 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
491 #define x86_stosd(inst) x86_stosl((inst))
492 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
493 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
494 #define x86_movsd(inst) x86_movsl((inst))
496 #if defined(__default_codegen__)
497 #define x86_prefix(inst,p) \
499 *(inst)++ =(unsigned char) (p); \
501 #elif defined(__native_client_codegen__)
502 #if defined(TARGET_X86)
503 /* kNaClAlignment - 1 is the max value we can pass into x86_codegen_pre. */
504 /* This keeps us from having to call x86_codegen_pre with specific */
505 /* knowledge of the size of the instruction that follows it, and */
506 /* localizes the alignment requirement to this spot. */
507 #define x86_prefix(inst,p) \
509 x86_codegen_pre(&(inst), kNaClAlignment - 1); \
510 *(inst)++ =(unsigned char) (p); \
512 #elif defined(TARGET_AMD64)
513 /* We need to tag any prefixes so we can perform proper membase sandboxing */
514 /* See: mini-amd64.c:amd64_nacl_membase_handler for verbose details */
515 #define x86_prefix(inst,p) \
517 amd64_nacl_tag_legacy_prefix((inst)); \
518 *(inst)++ =(unsigned char) (p); \
521 #endif /* TARGET_AMD64 */
523 #endif /* __native_client_codegen__ */
525 #define x86_rdtsc(inst) \
531 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
533 x86_codegen_pre(&(inst), 3); \
534 *(inst)++ = (unsigned char)0x0f; \
535 *(inst)++ = (unsigned char)0xb1; \
536 x86_reg_emit ((inst), (reg), (dreg)); \
539 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
541 x86_codegen_pre(&(inst), 7); \
542 *(inst)++ = (unsigned char)0x0f; \
543 *(inst)++ = (unsigned char)0xb1; \
544 x86_mem_emit ((inst), (reg), (mem)); \
547 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
549 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
550 *(inst)++ = (unsigned char)0x0f; \
551 *(inst)++ = (unsigned char)0xb1; \
552 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
555 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
557 x86_codegen_pre(&(inst), 2); \
559 *(inst)++ = (unsigned char)0x86; \
561 *(inst)++ = (unsigned char)0x87; \
562 x86_reg_emit ((inst), (reg), (dreg)); \
565 #define x86_xchg_mem_reg(inst,mem,reg,size) \
567 x86_codegen_pre(&(inst), 6); \
569 *(inst)++ = (unsigned char)0x86; \
571 *(inst)++ = (unsigned char)0x87; \
572 x86_mem_emit ((inst), (reg), (mem)); \
575 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
577 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
579 *(inst)++ = (unsigned char)0x86; \
581 *(inst)++ = (unsigned char)0x87; \
582 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
585 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
587 x86_codegen_pre(&(inst), 4); \
588 *(inst)++ = (unsigned char)0x0F; \
590 *(inst)++ = (unsigned char)0xC0; \
592 *(inst)++ = (unsigned char)0xC1; \
593 x86_reg_emit ((inst), (reg), (dreg)); \
596 #define x86_xadd_mem_reg(inst,mem,reg,size) \
598 x86_codegen_pre(&(inst), 7); \
599 *(inst)++ = (unsigned char)0x0F; \
601 *(inst)++ = (unsigned char)0xC0; \
603 *(inst)++ = (unsigned char)0xC1; \
604 x86_mem_emit ((inst), (reg), (mem)); \
607 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
609 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
610 *(inst)++ = (unsigned char)0x0F; \
612 *(inst)++ = (unsigned char)0xC0; \
614 *(inst)++ = (unsigned char)0xC1; \
615 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
618 #define x86_inc_mem(inst,mem) \
620 x86_codegen_pre(&(inst), 6); \
621 *(inst)++ = (unsigned char)0xff; \
622 x86_mem_emit ((inst), 0, (mem)); \
625 #define x86_inc_membase(inst,basereg,disp) \
627 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
628 *(inst)++ = (unsigned char)0xff; \
629 x86_membase_emit ((inst), 0, (basereg), (disp)); \
632 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
634 #define x86_dec_mem(inst,mem) \
636 x86_codegen_pre(&(inst), 6); \
637 *(inst)++ = (unsigned char)0xff; \
638 x86_mem_emit ((inst), 1, (mem)); \
641 #define x86_dec_membase(inst,basereg,disp) \
643 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
644 *(inst)++ = (unsigned char)0xff; \
645 x86_membase_emit ((inst), 1, (basereg), (disp)); \
648 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
650 #define x86_not_mem(inst,mem) \
652 x86_codegen_pre(&(inst), 6); \
653 *(inst)++ = (unsigned char)0xf7; \
654 x86_mem_emit ((inst), 2, (mem)); \
657 #define x86_not_membase(inst,basereg,disp) \
659 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
660 *(inst)++ = (unsigned char)0xf7; \
661 x86_membase_emit ((inst), 2, (basereg), (disp)); \
664 #define x86_not_reg(inst,reg) \
666 x86_codegen_pre(&(inst), 2); \
667 *(inst)++ = (unsigned char)0xf7; \
668 x86_reg_emit ((inst), 2, (reg)); \
671 #define x86_neg_mem(inst,mem) \
673 x86_codegen_pre(&(inst), 2); \
674 *(inst)++ = (unsigned char)0xf7; \
675 x86_mem_emit ((inst), 3, (mem)); \
678 #define x86_neg_membase(inst,basereg,disp) \
680 x86_codegen_pre(&(inst), 6); \
681 *(inst)++ = (unsigned char)0xf7; \
682 x86_membase_emit ((inst), 3, (basereg), (disp)); \
685 #define x86_neg_reg(inst,reg) \
687 x86_codegen_pre(&(inst), 2); \
688 *(inst)++ = (unsigned char)0xf7; \
689 x86_reg_emit ((inst), 3, (reg)); \
692 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
694 #define x86_alu_reg_imm(inst,opc,reg,imm) \
696 if ((reg) == X86_EAX) { \
697 x86_codegen_pre(&(inst), 5); \
698 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
699 x86_imm_emit32 ((inst), (imm)); \
702 if (x86_is_imm8((imm))) { \
703 x86_codegen_pre(&(inst), 3); \
704 *(inst)++ = (unsigned char)0x83; \
705 x86_reg_emit ((inst), (opc), (reg)); \
706 x86_imm_emit8 ((inst), (imm)); \
708 x86_codegen_pre(&(inst), 6); \
709 *(inst)++ = (unsigned char)0x81; \
710 x86_reg_emit ((inst), (opc), (reg)); \
711 x86_imm_emit32 ((inst), (imm)); \
715 #define x86_alu_mem_imm(inst,opc,mem,imm) \
717 if (x86_is_imm8((imm))) { \
718 x86_codegen_pre(&(inst), 7); \
719 *(inst)++ = (unsigned char)0x83; \
720 x86_mem_emit ((inst), (opc), (mem)); \
721 x86_imm_emit8 ((inst), (imm)); \
723 x86_codegen_pre(&(inst), 10); \
724 *(inst)++ = (unsigned char)0x81; \
725 x86_mem_emit ((inst), (opc), (mem)); \
726 x86_imm_emit32 ((inst), (imm)); \
730 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
732 if (x86_is_imm8((imm))) { \
733 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
734 *(inst)++ = (unsigned char)0x83; \
735 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
736 x86_imm_emit8 ((inst), (imm)); \
738 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
739 *(inst)++ = (unsigned char)0x81; \
740 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
741 x86_imm_emit32 ((inst), (imm)); \
745 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
747 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
748 *(inst)++ = (unsigned char)0x80; \
749 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
750 x86_imm_emit8 ((inst), (imm)); \
753 #define x86_alu_mem_reg(inst,opc,mem,reg) \
755 x86_codegen_pre(&(inst), 6); \
756 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
757 x86_mem_emit ((inst), (reg), (mem)); \
760 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
762 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
763 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
764 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
767 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
769 x86_codegen_pre(&(inst), 2); \
770 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
771 x86_reg_emit ((inst), (dreg), (reg)); \
775 * @x86_alu_reg8_reg8:
776 * Supports ALU operations between two 8-bit registers.
777 * dreg := dreg opc reg
778 * X86_Reg_No enum is used to specify the registers.
779 * Additionally is_*_h flags are used to specify what part
780 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
781 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
783 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
785 x86_codegen_pre(&(inst), 2); \
786 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
787 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
790 #define x86_alu_reg_mem(inst,opc,reg,mem) \
792 x86_codegen_pre(&(inst), 6); \
793 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
794 x86_mem_emit ((inst), (reg), (mem)); \
797 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
799 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
800 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
801 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
804 #define x86_test_reg_imm(inst,reg,imm) \
806 x86_codegen_pre(&(inst), 6); \
807 if ((reg) == X86_EAX) { \
808 *(inst)++ = (unsigned char)0xa9; \
810 *(inst)++ = (unsigned char)0xf7; \
811 x86_reg_emit ((inst), 0, (reg)); \
813 x86_imm_emit32 ((inst), (imm)); \
816 #define x86_test_mem_imm(inst,mem,imm) \
818 x86_codegen_pre(&(inst), 10); \
819 *(inst)++ = (unsigned char)0xf7; \
820 x86_mem_emit ((inst), 0, (mem)); \
821 x86_imm_emit32 ((inst), (imm)); \
824 #define x86_test_membase_imm(inst,basereg,disp,imm) \
826 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
827 *(inst)++ = (unsigned char)0xf7; \
828 x86_membase_emit ((inst), 0, (basereg), (disp)); \
829 x86_imm_emit32 ((inst), (imm)); \
832 #define x86_test_reg_reg(inst,dreg,reg) \
834 x86_codegen_pre(&(inst), 2); \
835 *(inst)++ = (unsigned char)0x85; \
836 x86_reg_emit ((inst), (reg), (dreg)); \
839 #define x86_test_mem_reg(inst,mem,reg) \
841 x86_codegen_pre(&(inst), 6); \
842 *(inst)++ = (unsigned char)0x85; \
843 x86_mem_emit ((inst), (reg), (mem)); \
846 #define x86_test_membase_reg(inst,basereg,disp,reg) \
848 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
849 *(inst)++ = (unsigned char)0x85; \
850 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
853 #define x86_shift_reg_imm(inst,opc,reg,imm) \
856 x86_codegen_pre(&(inst), 2); \
857 *(inst)++ = (unsigned char)0xd1; \
858 x86_reg_emit ((inst), (opc), (reg)); \
860 x86_codegen_pre(&(inst), 3); \
861 *(inst)++ = (unsigned char)0xc1; \
862 x86_reg_emit ((inst), (opc), (reg)); \
863 x86_imm_emit8 ((inst), (imm)); \
867 #define x86_shift_mem_imm(inst,opc,mem,imm) \
870 x86_codegen_pre(&(inst), 6); \
871 *(inst)++ = (unsigned char)0xd1; \
872 x86_mem_emit ((inst), (opc), (mem)); \
874 x86_codegen_pre(&(inst), 7); \
875 *(inst)++ = (unsigned char)0xc1; \
876 x86_mem_emit ((inst), (opc), (mem)); \
877 x86_imm_emit8 ((inst), (imm)); \
881 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
884 x86_codegen_pre(&(inst), 6); \
885 *(inst)++ = (unsigned char)0xd1; \
886 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
888 x86_codegen_pre(&(inst), 7); \
889 *(inst)++ = (unsigned char)0xc1; \
890 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
891 x86_imm_emit8 ((inst), (imm)); \
895 #define x86_shift_reg(inst,opc,reg) \
897 x86_codegen_pre(&(inst), 2); \
898 *(inst)++ = (unsigned char)0xd3; \
899 x86_reg_emit ((inst), (opc), (reg)); \
902 #define x86_shift_mem(inst,opc,mem) \
904 x86_codegen_pre(&(inst), 6); \
905 *(inst)++ = (unsigned char)0xd3; \
906 x86_mem_emit ((inst), (opc), (mem)); \
909 #define x86_shift_membase(inst,opc,basereg,disp) \
911 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
912 *(inst)++ = (unsigned char)0xd3; \
913 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
917 * Multi op shift missing.
920 #define x86_shrd_reg(inst,dreg,reg) \
922 x86_codegen_pre(&(inst), 3); \
923 *(inst)++ = (unsigned char)0x0f; \
924 *(inst)++ = (unsigned char)0xad; \
925 x86_reg_emit ((inst), (reg), (dreg)); \
928 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
930 x86_codegen_pre(&(inst), 4); \
931 *(inst)++ = (unsigned char)0x0f; \
932 *(inst)++ = (unsigned char)0xac; \
933 x86_reg_emit ((inst), (reg), (dreg)); \
934 x86_imm_emit8 ((inst), (shamt)); \
937 #define x86_shld_reg(inst,dreg,reg) \
939 x86_codegen_pre(&(inst), 3); \
940 *(inst)++ = (unsigned char)0x0f; \
941 *(inst)++ = (unsigned char)0xa5; \
942 x86_reg_emit ((inst), (reg), (dreg)); \
945 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
947 x86_codegen_pre(&(inst), 4); \
948 *(inst)++ = (unsigned char)0x0f; \
949 *(inst)++ = (unsigned char)0xa4; \
950 x86_reg_emit ((inst), (reg), (dreg)); \
951 x86_imm_emit8 ((inst), (shamt)); \
957 #define x86_mul_reg(inst,reg,is_signed) \
959 x86_codegen_pre(&(inst), 2); \
960 *(inst)++ = (unsigned char)0xf7; \
961 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
964 #define x86_mul_mem(inst,mem,is_signed) \
966 x86_codegen_pre(&(inst), 6); \
967 *(inst)++ = (unsigned char)0xf7; \
968 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
971 #define x86_mul_membase(inst,basereg,disp,is_signed) \
973 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
974 *(inst)++ = (unsigned char)0xf7; \
975 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
981 #define x86_imul_reg_reg(inst,dreg,reg) \
983 x86_codegen_pre(&(inst), 3); \
984 *(inst)++ = (unsigned char)0x0f; \
985 *(inst)++ = (unsigned char)0xaf; \
986 x86_reg_emit ((inst), (dreg), (reg)); \
989 #define x86_imul_reg_mem(inst,reg,mem) \
991 x86_codegen_pre(&(inst), 7); \
992 *(inst)++ = (unsigned char)0x0f; \
993 *(inst)++ = (unsigned char)0xaf; \
994 x86_mem_emit ((inst), (reg), (mem)); \
997 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
999 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1000 *(inst)++ = (unsigned char)0x0f; \
1001 *(inst)++ = (unsigned char)0xaf; \
1002 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1008 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
1010 if (x86_is_imm8 ((imm))) { \
1011 x86_codegen_pre(&(inst), 3); \
1012 *(inst)++ = (unsigned char)0x6b; \
1013 x86_reg_emit ((inst), (dreg), (reg)); \
1014 x86_imm_emit8 ((inst), (imm)); \
1016 x86_codegen_pre(&(inst), 6); \
1017 *(inst)++ = (unsigned char)0x69; \
1018 x86_reg_emit ((inst), (dreg), (reg)); \
1019 x86_imm_emit32 ((inst), (imm)); \
1023 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
1025 if (x86_is_imm8 ((imm))) { \
1026 x86_codegen_pre(&(inst), 7); \
1027 *(inst)++ = (unsigned char)0x6b; \
1028 x86_mem_emit ((inst), (reg), (mem)); \
1029 x86_imm_emit8 ((inst), (imm)); \
1031 x86_codegen_pre(&(inst), 6); \
1032 *(inst)++ = (unsigned char)0x69; \
1033 x86_reg_emit ((inst), (reg), (mem)); \
1034 x86_imm_emit32 ((inst), (imm)); \
1038 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
1040 if (x86_is_imm8 ((imm))) { \
1041 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1042 *(inst)++ = (unsigned char)0x6b; \
1043 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1044 x86_imm_emit8 ((inst), (imm)); \
1046 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1047 *(inst)++ = (unsigned char)0x69; \
1048 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1049 x86_imm_emit32 ((inst), (imm)); \
1054 * divide EDX:EAX by rm;
1055 * eax = quotient, edx = remainder
1058 #define x86_div_reg(inst,reg,is_signed) \
1060 x86_codegen_pre(&(inst), 2); \
1061 *(inst)++ = (unsigned char)0xf7; \
1062 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
1065 #define x86_div_mem(inst,mem,is_signed) \
1067 x86_codegen_pre(&(inst), 6); \
1068 *(inst)++ = (unsigned char)0xf7; \
1069 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
1072 #define x86_div_membase(inst,basereg,disp,is_signed) \
1074 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1075 *(inst)++ = (unsigned char)0xf7; \
1076 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
1079 #define x86_mov_mem_reg(inst,mem,reg,size) \
1081 x86_codegen_pre(&(inst), 7); \
1083 case 1: *(inst)++ = (unsigned char)0x88; break; \
1084 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1085 case 4: *(inst)++ = (unsigned char)0x89; break; \
1086 default: assert (0); \
1088 x86_mem_emit ((inst), (reg), (mem)); \
1091 #define x86_mov_regp_reg(inst,regp,reg,size) \
1093 x86_codegen_pre(&(inst), 3); \
1095 case 1: *(inst)++ = (unsigned char)0x88; break; \
1096 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1097 case 4: *(inst)++ = (unsigned char)0x89; break; \
1098 default: assert (0); \
1100 x86_regp_emit ((inst), (reg), (regp)); \
1103 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
1105 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1107 case 1: *(inst)++ = (unsigned char)0x88; break; \
1108 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1109 case 4: *(inst)++ = (unsigned char)0x89; break; \
1110 default: assert (0); \
1112 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1115 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
1117 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1119 case 1: *(inst)++ = (unsigned char)0x88; break; \
1120 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1121 case 4: *(inst)++ = (unsigned char)0x89; break; \
1122 default: assert (0); \
1124 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1127 #define x86_mov_reg_reg(inst,dreg,reg,size) \
1129 x86_codegen_pre(&(inst), 3); \
1131 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1132 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1133 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1134 default: assert (0); \
1136 x86_reg_emit ((inst), (dreg), (reg)); \
1139 #define x86_mov_reg_mem(inst,reg,mem,size) \
1141 x86_codegen_pre(&(inst), 7); \
1143 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1144 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1145 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1146 default: assert (0); \
1148 x86_mem_emit ((inst), (reg), (mem)); \
1151 #define kMovRegMembasePadding (2 + kMaxMembaseEmitPadding)
1153 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
1155 x86_codegen_pre(&(inst), kMovRegMembasePadding); \
1157 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1158 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1159 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1160 default: assert (0); \
1162 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1165 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
1167 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1169 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1170 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1171 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1172 default: assert (0); \
1174 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1178 * Note: x86_clear_reg () chacnges the condition code!
1180 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
1182 #define x86_mov_reg_imm(inst,reg,imm) \
1184 x86_codegen_pre(&(inst), 5); \
1185 *(inst)++ = (unsigned char)0xb8 + (reg); \
1186 x86_imm_emit32 ((inst), (imm)); \
1189 #define x86_mov_mem_imm(inst,mem,imm,size) \
1191 if ((size) == 1) { \
1192 x86_codegen_pre(&(inst), 7); \
1193 *(inst)++ = (unsigned char)0xc6; \
1194 x86_mem_emit ((inst), 0, (mem)); \
1195 x86_imm_emit8 ((inst), (imm)); \
1196 } else if ((size) == 2) { \
1197 x86_codegen_pre(&(inst), 9); \
1198 x86_prefix((inst), X86_OPERAND_PREFIX); \
1199 *(inst)++ = (unsigned char)0xc7; \
1200 x86_mem_emit ((inst), 0, (mem)); \
1201 x86_imm_emit16 ((inst), (imm)); \
1203 x86_codegen_pre(&(inst), 10); \
1204 *(inst)++ = (unsigned char)0xc7; \
1205 x86_mem_emit ((inst), 0, (mem)); \
1206 x86_imm_emit32 ((inst), (imm)); \
1210 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
1212 if ((size) == 1) { \
1213 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1214 *(inst)++ = (unsigned char)0xc6; \
1215 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1216 x86_imm_emit8 ((inst), (imm)); \
1217 } else if ((size) == 2) { \
1218 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
1219 x86_prefix((inst), X86_OPERAND_PREFIX); \
1220 *(inst)++ = (unsigned char)0xc7; \
1221 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1222 x86_imm_emit16 ((inst), (imm)); \
1224 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1225 *(inst)++ = (unsigned char)0xc7; \
1226 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1227 x86_imm_emit32 ((inst), (imm)); \
1231 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1233 if ((size) == 1) { \
1234 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1235 *(inst)++ = (unsigned char)0xc6; \
1236 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1237 x86_imm_emit8 ((inst), (imm)); \
1238 } else if ((size) == 2) { \
1239 x86_codegen_pre(&(inst), 4 + kMaxMemindexEmitPadding); \
1240 x86_prefix((inst), X86_OPERAND_PREFIX); \
1241 *(inst)++ = (unsigned char)0xc7; \
1242 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1243 x86_imm_emit16 ((inst), (imm)); \
1245 x86_codegen_pre(&(inst), 5 + kMaxMemindexEmitPadding); \
1246 *(inst)++ = (unsigned char)0xc7; \
1247 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1248 x86_imm_emit32 ((inst), (imm)); \
1252 #define x86_lea_mem(inst,reg,mem) \
1254 x86_codegen_pre(&(inst), 5); \
1255 *(inst)++ = (unsigned char)0x8d; \
1256 x86_mem_emit ((inst), (reg), (mem)); \
1259 #define x86_lea_membase(inst,reg,basereg,disp) \
1261 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1262 *(inst)++ = (unsigned char)0x8d; \
1263 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1266 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1268 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1269 *(inst)++ = (unsigned char)0x8d; \
1270 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1273 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1275 unsigned char op = 0xb6; \
1276 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1277 x86_codegen_pre(&(inst), 3); \
1278 *(inst)++ = (unsigned char)0x0f; \
1279 if ((is_signed)) op += 0x08; \
1280 if ((is_half)) op += 0x01; \
1282 x86_reg_emit ((inst), (dreg), (reg)); \
1285 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1287 unsigned char op = 0xb6; \
1288 x86_codegen_pre(&(inst), 7); \
1289 *(inst)++ = (unsigned char)0x0f; \
1290 if ((is_signed)) op += 0x08; \
1291 if ((is_half)) op += 0x01; \
1293 x86_mem_emit ((inst), (dreg), (mem)); \
1296 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1298 unsigned char op = 0xb6; \
1299 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1300 *(inst)++ = (unsigned char)0x0f; \
1301 if ((is_signed)) op += 0x08; \
1302 if ((is_half)) op += 0x01; \
1304 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1307 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1309 unsigned char op = 0xb6; \
1310 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1311 *(inst)++ = (unsigned char)0x0f; \
1312 if ((is_signed)) op += 0x08; \
1313 if ((is_half)) op += 0x01; \
1315 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1318 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1319 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1321 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1323 x86_codegen_pre(&(inst), 6); \
1324 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1325 x86_mem_emit ((inst), (opc), (mem)); \
1328 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1330 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1331 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1332 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1335 #define x86_fp_op(inst,opc,index) \
1337 x86_codegen_pre(&(inst), 2); \
1338 *(inst)++ = (unsigned char)0xd8; \
1339 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1342 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1344 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1345 x86_codegen_pre(&(inst), 2); \
1346 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1347 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1351 * @x86_fp_int_op_membase
1352 * Supports FPU operations between ST(0) and integer operand in memory.
1353 * Operation encoded using X86_FP_Opcode enum.
1354 * Operand is addressed by [basereg + disp].
1355 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1357 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1359 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1360 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1361 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1364 #define x86_fstp(inst,index) \
1366 x86_codegen_pre(&(inst), 2); \
1367 *(inst)++ = (unsigned char)0xdd; \
1368 *(inst)++ = (unsigned char)0xd8+(index); \
1371 #define x86_fcompp(inst) \
1373 x86_codegen_pre(&(inst), 2); \
1374 *(inst)++ = (unsigned char)0xde; \
1375 *(inst)++ = (unsigned char)0xd9; \
1378 #define x86_fucompp(inst) \
1380 x86_codegen_pre(&(inst), 2); \
1381 *(inst)++ = (unsigned char)0xda; \
1382 *(inst)++ = (unsigned char)0xe9; \
1385 #define x86_fnstsw(inst) \
1387 x86_codegen_pre(&(inst), 2); \
1388 *(inst)++ = (unsigned char)0xdf; \
1389 *(inst)++ = (unsigned char)0xe0; \
1392 #define x86_fnstcw(inst,mem) \
1394 x86_codegen_pre(&(inst), 6); \
1395 *(inst)++ = (unsigned char)0xd9; \
1396 x86_mem_emit ((inst), 7, (mem)); \
1399 #define x86_fnstcw_membase(inst,basereg,disp) \
1401 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1402 *(inst)++ = (unsigned char)0xd9; \
1403 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1406 #define x86_fldcw(inst,mem) \
1408 x86_codegen_pre(&(inst), 6); \
1409 *(inst)++ = (unsigned char)0xd9; \
1410 x86_mem_emit ((inst), 5, (mem)); \
1413 #define x86_fldcw_membase(inst,basereg,disp) \
1415 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1416 *(inst)++ = (unsigned char)0xd9; \
1417 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1420 #define x86_fchs(inst) \
1422 x86_codegen_pre(&(inst), 2); \
1423 *(inst)++ = (unsigned char)0xd9; \
1424 *(inst)++ = (unsigned char)0xe0; \
1427 #define x86_frem(inst) \
1429 x86_codegen_pre(&(inst), 2); \
1430 *(inst)++ = (unsigned char)0xd9; \
1431 *(inst)++ = (unsigned char)0xf8; \
1434 #define x86_fxch(inst,index) \
1436 x86_codegen_pre(&(inst), 2); \
1437 *(inst)++ = (unsigned char)0xd9; \
1438 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1441 #define x86_fcomi(inst,index) \
1443 x86_codegen_pre(&(inst), 2); \
1444 *(inst)++ = (unsigned char)0xdb; \
1445 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1448 #define x86_fcomip(inst,index) \
1450 x86_codegen_pre(&(inst), 2); \
1451 *(inst)++ = (unsigned char)0xdf; \
1452 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1455 #define x86_fucomi(inst,index) \
1457 x86_codegen_pre(&(inst), 2); \
1458 *(inst)++ = (unsigned char)0xdb; \
1459 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1462 #define x86_fucomip(inst,index) \
1464 x86_codegen_pre(&(inst), 2); \
1465 *(inst)++ = (unsigned char)0xdf; \
1466 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1469 #define x86_fld(inst,mem,is_double) \
1471 x86_codegen_pre(&(inst), 6); \
1472 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1473 x86_mem_emit ((inst), 0, (mem)); \
1476 #define x86_fld_membase(inst,basereg,disp,is_double) \
1478 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1479 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1480 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1483 #define x86_fld80_mem(inst,mem) \
1485 x86_codegen_pre(&(inst), 6); \
1486 *(inst)++ = (unsigned char)0xdb; \
1487 x86_mem_emit ((inst), 5, (mem)); \
1490 #define x86_fld80_membase(inst,basereg,disp) \
1492 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1493 *(inst)++ = (unsigned char)0xdb; \
1494 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1497 #define x86_fild(inst,mem,is_long) \
1499 x86_codegen_pre(&(inst), 6); \
1501 *(inst)++ = (unsigned char)0xdf; \
1502 x86_mem_emit ((inst), 5, (mem)); \
1504 *(inst)++ = (unsigned char)0xdb; \
1505 x86_mem_emit ((inst), 0, (mem)); \
1509 #define x86_fild_membase(inst,basereg,disp,is_long) \
1511 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1513 *(inst)++ = (unsigned char)0xdf; \
1514 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1516 *(inst)++ = (unsigned char)0xdb; \
1517 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1521 #define x86_fld_reg(inst,index) \
1523 x86_codegen_pre(&(inst), 2); \
1524 *(inst)++ = (unsigned char)0xd9; \
1525 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1528 #define x86_fldz(inst) \
1530 x86_codegen_pre(&(inst), 2); \
1531 *(inst)++ = (unsigned char)0xd9; \
1532 *(inst)++ = (unsigned char)0xee; \
1535 #define x86_fld1(inst) \
1537 x86_codegen_pre(&(inst), 2); \
1538 *(inst)++ = (unsigned char)0xd9; \
1539 *(inst)++ = (unsigned char)0xe8; \
1542 #define x86_fldpi(inst) \
1544 x86_codegen_pre(&(inst), 2); \
1545 *(inst)++ = (unsigned char)0xd9; \
1546 *(inst)++ = (unsigned char)0xeb; \
1549 #define x86_fst(inst,mem,is_double,pop_stack) \
1551 x86_codegen_pre(&(inst), 6); \
1552 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1553 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1556 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1558 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1559 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1560 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1563 #define x86_fst80_mem(inst,mem) \
1565 x86_codegen_pre(&(inst), 6); \
1566 *(inst)++ = (unsigned char)0xdb; \
1567 x86_mem_emit ((inst), 7, (mem)); \
1571 #define x86_fst80_membase(inst,basereg,disp) \
1573 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1574 *(inst)++ = (unsigned char)0xdb; \
1575 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1579 #define x86_fist_pop(inst,mem,is_long) \
1581 x86_codegen_pre(&(inst), 6); \
1583 *(inst)++ = (unsigned char)0xdf; \
1584 x86_mem_emit ((inst), 7, (mem)); \
1586 *(inst)++ = (unsigned char)0xdb; \
1587 x86_mem_emit ((inst), 3, (mem)); \
1591 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1593 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1595 *(inst)++ = (unsigned char)0xdf; \
1596 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1598 *(inst)++ = (unsigned char)0xdb; \
1599 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1603 #define x86_fstsw(inst) \
1605 x86_codegen_pre(&(inst), 3); \
1606 *(inst)++ = (unsigned char)0x9b; \
1607 *(inst)++ = (unsigned char)0xdf; \
1608 *(inst)++ = (unsigned char)0xe0; \
1613 * Converts content of ST(0) to integer and stores it at memory location
1614 * addressed by [basereg + disp].
1615 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1617 #define x86_fist_membase(inst,basereg,disp,is_int) \
1619 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1621 *(inst)++ = (unsigned char)0xdb; \
1622 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1624 *(inst)++ = (unsigned char)0xdf; \
1625 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1630 #define x86_push_reg(inst,reg) \
1632 *(inst)++ = (unsigned char)0x50 + (reg); \
1635 #define x86_push_regp(inst,reg) \
1637 x86_codegen_pre(&(inst), 2); \
1638 *(inst)++ = (unsigned char)0xff; \
1639 x86_regp_emit ((inst), 6, (reg)); \
1642 #define x86_push_mem(inst,mem) \
1644 x86_codegen_pre(&(inst), 6); \
1645 *(inst)++ = (unsigned char)0xff; \
1646 x86_mem_emit ((inst), 6, (mem)); \
1649 #define x86_push_membase(inst,basereg,disp) \
1651 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1652 *(inst)++ = (unsigned char)0xff; \
1653 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1656 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1658 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1659 *(inst)++ = (unsigned char)0xff; \
1660 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1663 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1665 #define x86_push_imm(inst,imm) \
1667 int _imm = (int) (imm); \
1668 if (x86_is_imm8 (_imm)) { \
1669 x86_codegen_pre(&(inst), 2); \
1670 *(inst)++ = (unsigned char)0x6A; \
1671 x86_imm_emit8 ((inst), (_imm)); \
1673 x86_codegen_pre(&(inst), 5); \
1674 *(inst)++ = (unsigned char)0x68; \
1675 x86_imm_emit32 ((inst), (_imm)); \
1679 #define x86_pop_reg(inst,reg) \
1681 *(inst)++ = (unsigned char)0x58 + (reg); \
1684 #define x86_pop_mem(inst,mem) \
1686 x86_codegen_pre(&(inst), 6); \
1687 *(inst)++ = (unsigned char)0x87; \
1688 x86_mem_emit ((inst), 0, (mem)); \
1691 #define x86_pop_membase(inst,basereg,disp) \
1693 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1694 *(inst)++ = (unsigned char)0x87; \
1695 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1698 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1699 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1700 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1701 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1703 #define x86_loop(inst,imm) \
1705 x86_codegen_pre(&(inst), 2); \
1706 *(inst)++ = (unsigned char)0xe2; \
1707 x86_imm_emit8 ((inst), (imm)); \
1710 #define x86_loope(inst,imm) \
1712 x86_codegen_pre(&(inst), 2); \
1713 *(inst)++ = (unsigned char)0xe1; \
1714 x86_imm_emit8 ((inst), (imm)); \
1717 #define x86_loopne(inst,imm) \
1719 x86_codegen_pre(&(inst), 2); \
1720 *(inst)++ = (unsigned char)0xe0; \
1721 x86_imm_emit8 ((inst), (imm)); \
1724 #if defined(TARGET_X86)
1725 #define x86_jump32(inst,imm) \
1727 x86_codegen_pre(&(inst), 5); \
1728 *(inst)++ = (unsigned char)0xe9; \
1729 x86_imm_emit32 ((inst), (imm)); \
1732 #define x86_jump8(inst,imm) \
1734 x86_codegen_pre(&(inst), 2); \
1735 *(inst)++ = (unsigned char)0xeb; \
1736 x86_imm_emit8 ((inst), (imm)); \
1738 #elif defined(TARGET_AMD64)
1739 /* These macros are used directly from mini-amd64.c and other */
1740 /* amd64 specific files, so they need to be instrumented directly. */
1741 #define x86_jump32(inst,imm) \
1743 amd64_codegen_pre(inst); \
1744 *(inst)++ = (unsigned char)0xe9; \
1745 x86_imm_emit32 ((inst), (imm)); \
1746 amd64_codegen_post(inst); \
1749 #define x86_jump8(inst,imm) \
1751 amd64_codegen_pre(inst); \
1752 *(inst)++ = (unsigned char)0xeb; \
1753 x86_imm_emit8 ((inst), (imm)); \
1754 amd64_codegen_post(inst); \
1758 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
1759 #define x86_jump_reg(inst,reg) do { \
1760 x86_codegen_pre(&(inst), 5); \
1761 *(inst)++ = (unsigned char)0x83; /* and */ \
1762 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
1763 *(inst)++ = (unsigned char)nacl_align_byte; \
1764 *(inst)++ = (unsigned char)0xff; \
1765 x86_reg_emit ((inst), 4, (reg)); \
1768 /* Let's hope ECX is available for these... */
1769 #define x86_jump_mem(inst,mem) do { \
1770 x86_mov_reg_mem(inst, (X86_ECX), (mem), 4); \
1771 x86_jump_reg(inst, (X86_ECX)); \
1774 #define x86_jump_membase(inst,basereg,disp) do { \
1775 x86_mov_reg_membase(inst, (X86_ECX), basereg, disp, 4); \
1776 x86_jump_reg(inst, (X86_ECX)); \
1779 /* like x86_jump_membase, but force a 32-bit displacement */
1780 #define x86_jump_membase32(inst,basereg,disp) do { \
1781 x86_codegen_pre(&(inst), 6); \
1782 *(inst)++ = (unsigned char)0x8b; \
1783 x86_address_byte ((inst), 2, X86_ECX, (basereg)); \
1784 x86_imm_emit32 ((inst), (disp)); \
1785 x86_jump_reg(inst, (X86_ECX)); \
1787 #else /* __native_client_codegen__ */
1788 #define x86_jump_reg(inst,reg) \
1790 *(inst)++ = (unsigned char)0xff; \
1791 x86_reg_emit ((inst), 4, (reg)); \
1794 #define x86_jump_mem(inst,mem) \
1796 *(inst)++ = (unsigned char)0xff; \
1797 x86_mem_emit ((inst), 4, (mem)); \
1800 #define x86_jump_membase(inst,basereg,disp) \
1802 *(inst)++ = (unsigned char)0xff; \
1803 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1805 #endif /* __native_client_codegen__ */
1807 * target is a pointer in our buffer.
1809 #define x86_jump_code_body(inst,target) \
1812 x86_codegen_pre(&(inst), 2); \
1813 t = (unsigned char*)(target) - (inst) - 2; \
1814 if (x86_is_imm8(t)) { \
1815 x86_jump8 ((inst), t); \
1817 x86_codegen_pre(&(inst), 5); \
1818 t = (unsigned char*)(target) - (inst) - 5; \
1819 x86_jump32 ((inst), t); \
1823 #if defined(__default_codegen__)
1824 #define x86_jump_code(inst,target) \
1826 x86_jump_code_body((inst),(target)); \
1828 #elif defined(__native_client_codegen__) && defined(TARGET_X86)
1829 #define x86_jump_code(inst,target) \
1831 guint8* jump_start = (inst); \
1832 x86_jump_code_body((inst),(target)); \
1833 x86_patch(jump_start, (target)); \
1835 #elif defined(__native_client_codegen__) && defined(TARGET_AMD64)
1836 #define x86_jump_code(inst,target) \
1838 /* jump_code_body is used twice because there are offsets */ \
1839 /* calculated based on the IP, which can change after the */ \
1840 /* call to amd64_codegen_post */ \
1841 amd64_codegen_pre(inst); \
1842 x86_jump_code_body((inst),(target)); \
1843 inst = amd64_codegen_post(inst); \
1844 x86_jump_code_body((inst),(target)); \
1846 #endif /* __native_client_codegen__ */
1848 #define x86_jump_disp(inst,disp) \
1850 int t = (disp) - 2; \
1851 if (x86_is_imm8(t)) { \
1852 x86_jump8 ((inst), t); \
1855 x86_jump32 ((inst), t); \
1859 #if defined(TARGET_X86)
1860 #define x86_branch8(inst,cond,imm,is_signed) \
1862 x86_codegen_pre(&(inst), 2); \
1864 *(inst)++ = x86_cc_signed_map [(cond)]; \
1866 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1867 x86_imm_emit8 ((inst), (imm)); \
1870 #define x86_branch32(inst,cond,imm,is_signed) \
1872 x86_codegen_pre(&(inst), 6); \
1873 *(inst)++ = (unsigned char)0x0f; \
1875 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1877 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1878 x86_imm_emit32 ((inst), (imm)); \
1880 #elif defined(TARGET_AMD64)
1881 /* These macros are used directly from mini-amd64.c and other */
1882 /* amd64 specific files, so they need to be instrumented directly. */
1883 #define x86_branch8(inst,cond,imm,is_signed) \
1885 amd64_codegen_pre(inst); \
1887 *(inst)++ = x86_cc_signed_map [(cond)]; \
1889 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1890 x86_imm_emit8 ((inst), (imm)); \
1891 amd64_codegen_post(inst); \
1893 #define x86_branch32(inst,cond,imm,is_signed) \
1895 amd64_codegen_pre(inst); \
1896 *(inst)++ = (unsigned char)0x0f; \
1898 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1900 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1901 x86_imm_emit32 ((inst), (imm)); \
1902 amd64_codegen_post(inst); \
1906 #if defined(TARGET_X86)
1907 #define x86_branch(inst,cond,target,is_signed) \
1910 guint8* branch_start; \
1911 x86_codegen_pre(&(inst), 2); \
1912 offset = (target) - (inst) - 2; \
1913 branch_start = (inst); \
1914 if (x86_is_imm8 ((offset))) \
1915 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1917 x86_codegen_pre(&(inst), 6); \
1918 offset = (target) - (inst) - 6; \
1919 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1921 x86_patch(branch_start, (target)); \
1923 #elif defined(TARGET_AMD64)
1924 /* This macro is used directly from mini-amd64.c and other */
1925 /* amd64 specific files, so it needs to be instrumented directly. */
1927 #define x86_branch_body(inst,cond,target,is_signed) \
1929 int offset = (target) - (inst) - 2; \
1930 if (x86_is_imm8 ((offset))) \
1931 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1933 offset = (target) - (inst) - 6; \
1934 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1938 #if defined(__default_codegen__)
1939 #define x86_branch(inst,cond,target,is_signed) \
1941 x86_branch_body((inst),(cond),(target),(is_signed)); \
1943 #elif defined(__native_client_codegen__)
1944 #define x86_branch(inst,cond,target,is_signed) \
1946 /* branch_body is used twice because there are offsets */ \
1947 /* calculated based on the IP, which can change after */ \
1948 /* the call to amd64_codegen_post */ \
1949 amd64_codegen_pre(inst); \
1950 x86_branch_body((inst),(cond),(target),(is_signed)); \
1951 inst = amd64_codegen_post(inst); \
1952 x86_branch_body((inst),(cond),(target),(is_signed)); \
1954 #endif /* __native_client_codegen__ */
1956 #endif /* TARGET_AMD64 */
1958 #define x86_branch_disp(inst,cond,disp,is_signed) \
1960 int offset = (disp) - 2; \
1961 if (x86_is_imm8 ((offset))) \
1962 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1965 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1969 #define x86_set_reg(inst,cond,reg,is_signed) \
1971 g_assert (X86_IS_BYTE_REG (reg)); \
1972 x86_codegen_pre(&(inst), 3); \
1973 *(inst)++ = (unsigned char)0x0f; \
1975 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1977 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1978 x86_reg_emit ((inst), 0, (reg)); \
1981 #define x86_set_mem(inst,cond,mem,is_signed) \
1983 x86_codegen_pre(&(inst), 7); \
1984 *(inst)++ = (unsigned char)0x0f; \
1986 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1988 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1989 x86_mem_emit ((inst), 0, (mem)); \
1992 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
1994 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1995 *(inst)++ = (unsigned char)0x0f; \
1997 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1999 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
2000 x86_membase_emit ((inst), 0, (basereg), (disp)); \
2003 #define x86_call_imm_body(inst,disp) \
2005 *(inst)++ = (unsigned char)0xe8; \
2006 x86_imm_emit32 ((inst), (int)(disp)); \
2009 #define x86_call_imm(inst,disp) \
2011 x86_call_sequence_pre((inst)); \
2012 x86_call_imm_body((inst), (disp)); \
2013 x86_call_sequence_post((inst)); \
2017 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2018 #define x86_call_reg_internal(inst,reg) \
2020 *(inst)++ = (unsigned char)0x83; /* and */ \
2021 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
2022 *(inst)++ = (unsigned char)nacl_align_byte; \
2023 *(inst)++ = (unsigned char)0xff; /* call */ \
2024 x86_reg_emit ((inst), 2, (reg)); /* reg */ \
2027 #define x86_call_reg(inst, reg) do { \
2028 x86_call_sequence_pre((inst)); \
2029 x86_call_reg_internal(inst, reg); \
2030 x86_call_sequence_post((inst)); \
2034 /* It appears that x86_call_mem() is never used, so I'm leaving it out. */
2035 #define x86_call_membase(inst,basereg,disp) do { \
2036 x86_call_sequence_pre((inst)); \
2037 /* x86_mov_reg_membase() inlined so its fixed size */ \
2038 *(inst)++ = (unsigned char)0x8b; \
2039 x86_address_byte ((inst), 2, (X86_ECX), (basereg)); \
2040 x86_imm_emit32 ((inst), (disp)); \
2041 x86_call_reg_internal(inst, X86_ECX); \
2042 x86_call_sequence_post((inst)); \
2044 #else /* __native_client_codegen__ */
2045 #define x86_call_reg(inst,reg) \
2047 *(inst)++ = (unsigned char)0xff; \
2048 x86_reg_emit ((inst), 2, (reg)); \
2051 #define x86_call_mem(inst,mem) \
2053 *(inst)++ = (unsigned char)0xff; \
2054 x86_mem_emit ((inst), 2, (mem)); \
2057 #define x86_call_membase(inst,basereg,disp) \
2059 *(inst)++ = (unsigned char)0xff; \
2060 x86_membase_emit ((inst), 2, (basereg), (disp)); \
2062 #endif /* __native_client_codegen__ */
2065 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2067 #define x86_call_code(inst,target) \
2070 guint8* call_start; \
2071 guint8* _aligned_start; \
2072 x86_call_sequence_pre_val((inst)); \
2073 _x86_offset = (unsigned char*)(target) - (inst); \
2075 x86_call_imm_body ((inst), _x86_offset); \
2076 _aligned_start = x86_call_sequence_post_val((inst)); \
2077 call_start = _aligned_start; \
2078 _x86_offset = (unsigned char*)(target) - (_aligned_start); \
2080 x86_call_imm_body ((_aligned_start), _x86_offset); \
2081 x86_patch(call_start, (target)); \
2084 #define SIZE_OF_RET 6
2085 #define x86_ret(inst) do { \
2086 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2087 x86_codegen_pre(&(inst), 5); \
2088 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2089 *(inst)++ = (unsigned char)0xe1; \
2090 *(inst)++ = (unsigned char)nacl_align_byte; \
2091 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2092 *(inst)++ = (unsigned char)0xe1; \
2095 /* pop return address */
2096 /* pop imm bytes from stack */
2098 #define x86_ret_imm(inst,imm) do { \
2099 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2100 x86_alu_reg_imm ((inst), X86_ADD, X86_ESP, imm); \
2101 x86_codegen_pre(&(inst), 5); \
2102 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2103 *(inst)++ = (unsigned char)0xe1; \
2104 *(inst)++ = (unsigned char)nacl_align_byte; \
2105 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2106 *(inst)++ = (unsigned char)0xe1; \
2108 #else /* __native_client_codegen__ */
2110 #define x86_call_code(inst,target) \
2113 _x86_offset = (unsigned char*)(target) - (inst); \
2115 x86_call_imm_body ((inst), _x86_offset); \
2118 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
2120 #define x86_ret_imm(inst,imm) \
2125 x86_codegen_pre(&(inst), 3); \
2126 *(inst)++ = (unsigned char)0xc2; \
2127 x86_imm_emit16 ((inst), (imm)); \
2130 #endif /* __native_client_codegen__ */
2132 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
2134 x86_codegen_pre(&(inst), 3); \
2135 *(inst)++ = (unsigned char) 0x0f; \
2137 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2139 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2140 x86_reg_emit ((inst), (dreg), (reg)); \
2143 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
2145 x86_codegen_pre(&(inst), 7); \
2146 *(inst)++ = (unsigned char) 0x0f; \
2148 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2150 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2151 x86_mem_emit ((inst), (reg), (mem)); \
2154 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
2156 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2157 *(inst)++ = (unsigned char) 0x0f; \
2159 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2161 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2162 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2165 #define x86_enter(inst,framesize) \
2167 x86_codegen_pre(&(inst), 4); \
2168 *(inst)++ = (unsigned char)0xc8; \
2169 x86_imm_emit16 ((inst), (framesize)); \
2173 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
2174 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
2176 #define x86_fsin(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
2177 #define x86_fcos(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
2178 #define x86_fabs(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
2179 #define x86_ftst(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
2180 #define x86_fxam(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
2181 #define x86_fpatan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
2182 #define x86_fprem(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
2183 #define x86_fprem1(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
2184 #define x86_frndint(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
2185 #define x86_fsqrt(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
2186 #define x86_fptan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
2188 #define x86_padding(inst,size) \
2191 case 1: x86_nop ((inst)); break; \
2192 case 2: *(inst)++ = 0x8b; \
2193 *(inst)++ = 0xc0; break; \
2194 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
2195 *(inst)++ = 0x00; break; \
2196 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2197 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2199 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2200 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2201 x86_nop ((inst)); break; \
2202 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
2203 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2204 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2206 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
2207 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2208 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2209 *(inst)++ = 0x00; break; \
2210 default: assert (0); \
2214 #ifdef __native_client_codegen__
2216 #define kx86NaClLengthOfCallReg 5
2217 #define kx86NaClLengthOfCallImm 5
2218 #define kx86NaClLengthOfCallMembase (kx86NaClLengthOfCallReg + 6)
2220 #endif /* __native_client_codegen__ */
2222 #define x86_prolog(inst,frame_size,reg_mask) \
2224 unsigned i, m = 1; \
2225 x86_enter ((inst), (frame_size)); \
2226 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
2227 if ((reg_mask) & m) \
2228 x86_push_reg ((inst), i); \
2232 #define x86_epilog(inst,reg_mask) \
2234 unsigned i, m = 1 << X86_EDI; \
2235 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
2236 if ((reg_mask) & m) \
2237 x86_pop_reg ((inst), i); \
2239 x86_leave ((inst)); \
2245 X86_SSE_SQRT = 0x51,
2246 X86_SSE_RSQRT = 0x52,
2254 X86_SSE_COMP = 0xC2,
2256 X86_SSE_ANDN = 0x55,
2259 X86_SSE_UNPCKL = 0x14,
2260 X86_SSE_UNPCKH = 0x15,
2262 X86_SSE_ADDSUB = 0xD0,
2263 X86_SSE_HADD = 0x7C,
2264 X86_SSE_HSUB = 0x7D,
2265 X86_SSE_MOVSHDUP = 0x16,
2266 X86_SSE_MOVSLDUP = 0x12,
2267 X86_SSE_MOVDDUP = 0x12,
2269 X86_SSE_PAND = 0xDB,
2271 X86_SSE_PXOR = 0xEF,
2273 X86_SSE_PADDB = 0xFC,
2274 X86_SSE_PADDW = 0xFD,
2275 X86_SSE_PADDD = 0xFE,
2276 X86_SSE_PADDQ = 0xD4,
2278 X86_SSE_PSUBB = 0xF8,
2279 X86_SSE_PSUBW = 0xF9,
2280 X86_SSE_PSUBD = 0xFA,
2281 X86_SSE_PSUBQ = 0xFB,
2283 X86_SSE_PMAXSB = 0x3C, /*sse41*/
2284 X86_SSE_PMAXSW = 0xEE,
2285 X86_SSE_PMAXSD = 0x3D, /*sse41*/
2287 X86_SSE_PMAXUB = 0xDE,
2288 X86_SSE_PMAXUW = 0x3E, /*sse41*/
2289 X86_SSE_PMAXUD = 0x3F, /*sse41*/
2291 X86_SSE_PMINSB = 0x38, /*sse41*/
2292 X86_SSE_PMINSW = 0xEA,
2293 X86_SSE_PMINSD = 0x39,/*sse41*/
2295 X86_SSE_PMINUB = 0xDA,
2296 X86_SSE_PMINUW = 0x3A, /*sse41*/
2297 X86_SSE_PMINUD = 0x3B, /*sse41*/
2299 X86_SSE_PAVGB = 0xE0,
2300 X86_SSE_PAVGW = 0xE3,
2302 X86_SSE_PCMPEQB = 0x74,
2303 X86_SSE_PCMPEQW = 0x75,
2304 X86_SSE_PCMPEQD = 0x76,
2305 X86_SSE_PCMPEQQ = 0x29, /*sse41*/
2307 X86_SSE_PCMPGTB = 0x64,
2308 X86_SSE_PCMPGTW = 0x65,
2309 X86_SSE_PCMPGTD = 0x66,
2310 X86_SSE_PCMPGTQ = 0x37, /*sse42*/
2312 X86_SSE_PSADBW = 0xf6,
2314 X86_SSE_PSHUFD = 0x70,
2316 X86_SSE_PUNPCKLBW = 0x60,
2317 X86_SSE_PUNPCKLWD = 0x61,
2318 X86_SSE_PUNPCKLDQ = 0x62,
2319 X86_SSE_PUNPCKLQDQ = 0x6C,
2321 X86_SSE_PUNPCKHBW = 0x68,
2322 X86_SSE_PUNPCKHWD = 0x69,
2323 X86_SSE_PUNPCKHDQ = 0x6A,
2324 X86_SSE_PUNPCKHQDQ = 0x6D,
2326 X86_SSE_PACKSSWB = 0x63,
2327 X86_SSE_PACKSSDW = 0x6B,
2329 X86_SSE_PACKUSWB = 0x67,
2330 X86_SSE_PACKUSDW = 0x2B,/*sse41*/
2332 X86_SSE_PADDUSB = 0xDC,
2333 X86_SSE_PADDUSW = 0xDD,
2334 X86_SSE_PSUBUSB = 0xD8,
2335 X86_SSE_PSUBUSW = 0xD9,
2337 X86_SSE_PADDSB = 0xEC,
2338 X86_SSE_PADDSW = 0xED,
2339 X86_SSE_PSUBSB = 0xE8,
2340 X86_SSE_PSUBSW = 0xE9,
2342 X86_SSE_PMULLW = 0xD5,
2343 X86_SSE_PMULLD = 0x40,/*sse41*/
2344 X86_SSE_PMULHUW = 0xE4,
2345 X86_SSE_PMULHW = 0xE5,
2346 X86_SSE_PMULUDQ = 0xF4,
2348 X86_SSE_PMOVMSKB = 0xD7,
2350 X86_SSE_PSHIFTW = 0x71,
2351 X86_SSE_PSHIFTD = 0x72,
2352 X86_SSE_PSHIFTQ = 0x73,
2357 X86_SSE_PSRLW_REG = 0xD1,
2358 X86_SSE_PSRAW_REG = 0xE1,
2359 X86_SSE_PSLLW_REG = 0xF1,
2361 X86_SSE_PSRLD_REG = 0xD2,
2362 X86_SSE_PSRAD_REG = 0xE2,
2363 X86_SSE_PSLLD_REG = 0xF2,
2365 X86_SSE_PSRLQ_REG = 0xD3,
2366 X86_SSE_PSLLQ_REG = 0xF3,
2368 X86_SSE_PREFETCH = 0x18,
2369 X86_SSE_MOVNTPS = 0x2B,
2370 X86_SSE_MOVHPD_REG_MEMBASE = 0x16,
2371 X86_SSE_MOVHPD_MEMBASE_REG = 0x17,
2373 X86_SSE_MOVSD_REG_MEMBASE = 0x10,
2374 X86_SSE_MOVSD_MEMBASE_REG = 0x11,
2376 X86_SSE_PINSRB = 0x20,/*sse41*/
2377 X86_SSE_PINSRW = 0xC4,
2378 X86_SSE_PINSRD = 0x22,/*sse41*/
2380 X86_SSE_PEXTRB = 0x14,/*sse41*/
2381 X86_SSE_PEXTRW = 0xC5,
2382 X86_SSE_PEXTRD = 0x16,/*sse41*/
2384 X86_SSE_SHUFP = 0xC6,
2389 /* minimal SSE* support */
2390 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
2392 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2393 *(inst)++ = (unsigned char)0xf2; \
2394 *(inst)++ = (unsigned char)0x0f; \
2395 *(inst)++ = (unsigned char)0x10; \
2396 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
2399 #define x86_cvttsd2si(inst,dreg,reg) \
2401 x86_codegen_pre(&(inst), 4); \
2402 *(inst)++ = (unsigned char)0xf2; \
2403 *(inst)++ = (unsigned char)0x0f; \
2404 *(inst)++ = (unsigned char)0x2c; \
2405 x86_reg_emit ((inst), (dreg), (reg)); \
2408 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
2410 x86_codegen_pre(&(inst), 3); \
2411 *(inst)++ = (unsigned char)0x0F; \
2412 *(inst)++ = (unsigned char)(opc); \
2413 x86_reg_emit ((inst), (dreg), (reg)); \
2416 #define x86_sse_alu_reg_membase(inst,opc,sreg,basereg,disp) \
2418 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2419 *(inst)++ = (unsigned char)0x0f; \
2420 *(inst)++ = (unsigned char)(opc); \
2421 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2424 #define x86_sse_alu_membase_reg(inst,opc,basereg,disp,reg) \
2426 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2427 *(inst)++ = (unsigned char)0x0F; \
2428 *(inst)++ = (unsigned char)(opc); \
2429 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2432 #define x86_sse_alu_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2434 x86_codegen_pre(&(inst), 4); \
2435 *(inst)++ = (unsigned char)0x0F; \
2436 *(inst)++ = (unsigned char)(opc); \
2437 x86_reg_emit ((inst), (dreg), (reg)); \
2438 *(inst)++ = (unsigned char)(imm8); \
2441 #define x86_sse_alu_pd_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2443 x86_codegen_pre(&(inst), 5); \
2444 *(inst)++ = (unsigned char)0x66; \
2445 x86_sse_alu_reg_reg_imm8 ((inst), (opc), (dreg), (reg), (imm8)); \
2448 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
2450 x86_codegen_pre(&(inst), 4); \
2451 *(inst)++ = (unsigned char)0x66; \
2452 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2455 #define x86_sse_alu_pd_membase_reg(inst,opc,basereg,disp,reg) \
2457 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2458 *(inst)++ = (unsigned char)0x66; \
2459 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2462 #define x86_sse_alu_pd_reg_membase(inst,opc,dreg,basereg,disp) \
2464 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2465 *(inst)++ = (unsigned char)0x66; \
2466 x86_sse_alu_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2469 #define x86_sse_alu_pd_reg_reg_imm(inst,opc,dreg,reg,imm) \
2471 x86_codegen_pre(&(inst), 5); \
2472 x86_sse_alu_pd_reg_reg ((inst), (opc), (dreg), (reg)); \
2473 *(inst)++ = (unsigned char)(imm); \
2476 #define x86_sse_alu_pd_reg_membase_imm(inst,opc,dreg,basereg,disp,imm) \
2478 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
2479 x86_sse_alu_pd_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2480 *(inst)++ = (unsigned char)(imm); \
2484 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
2486 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2489 #define x86_sse_alu_ps_reg_reg_imm(inst,opc,dreg,reg, imm) \
2491 x86_codegen_pre(&(inst), 4); \
2492 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2493 *(inst)++ = (unsigned char)imm; \
2497 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
2499 x86_codegen_pre(&(inst), 4); \
2500 *(inst)++ = (unsigned char)0xF2; \
2501 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2504 #define x86_sse_alu_sd_membase_reg(inst,opc,basereg,disp,reg) \
2506 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2507 *(inst)++ = (unsigned char)0xF2; \
2508 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2512 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
2514 x86_codegen_pre(&(inst), 4); \
2515 *(inst)++ = (unsigned char)0xF3; \
2516 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2519 #define x86_sse_alu_ss_membase_reg(inst,opc,basereg,disp,reg) \
2521 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2522 *(inst)++ = (unsigned char)0xF3; \
2523 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2528 #define x86_sse_alu_sse41_reg_reg(inst,opc,dreg,reg) \
2530 x86_codegen_pre(&(inst), 5); \
2531 *(inst)++ = (unsigned char)0x66; \
2532 *(inst)++ = (unsigned char)0x0F; \
2533 *(inst)++ = (unsigned char)0x38; \
2534 *(inst)++ = (unsigned char)(opc); \
2535 x86_reg_emit ((inst), (dreg), (reg)); \
2538 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
2540 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2541 *(inst)++ = (unsigned char)0x0f; \
2542 *(inst)++ = (unsigned char)0x10; \
2543 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2546 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
2548 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2549 *(inst)++ = (unsigned char)0x0f; \
2550 *(inst)++ = (unsigned char)0x11; \
2551 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2554 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
2556 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2557 *(inst)++ = (unsigned char)0x0f; \
2558 *(inst)++ = (unsigned char)0x28; \
2559 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2562 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
2564 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2565 *(inst)++ = (unsigned char)0x0f; \
2566 *(inst)++ = (unsigned char)0x29; \
2567 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2570 #define x86_movaps_reg_reg(inst,dreg,sreg) \
2572 x86_codegen_pre(&(inst), 3); \
2573 *(inst)++ = (unsigned char)0x0f; \
2574 *(inst)++ = (unsigned char)0x28; \
2575 x86_reg_emit ((inst), (dreg), (sreg)); \
2579 #define x86_movd_reg_xreg(inst,dreg,sreg) \
2581 x86_codegen_pre(&(inst), 4); \
2582 *(inst)++ = (unsigned char)0x66; \
2583 *(inst)++ = (unsigned char)0x0f; \
2584 *(inst)++ = (unsigned char)0x7e; \
2585 x86_reg_emit ((inst), (sreg), (dreg)); \
2588 #define x86_movd_xreg_reg(inst,dreg,sreg) \
2590 x86_codegen_pre(&(inst), 4); \
2591 *(inst)++ = (unsigned char)0x66; \
2592 *(inst)++ = (unsigned char)0x0f; \
2593 *(inst)++ = (unsigned char)0x6e; \
2594 x86_reg_emit ((inst), (dreg), (sreg)); \
2597 #define x86_movd_xreg_membase(inst,sreg,basereg,disp) \
2599 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2600 *(inst)++ = (unsigned char)0x66; \
2601 *(inst)++ = (unsigned char)0x0f; \
2602 *(inst)++ = (unsigned char)0x6e; \
2603 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2606 #define x86_pshufw_reg_reg(inst,dreg,sreg,mask,high_words) \
2608 x86_codegen_pre(&(inst), 5); \
2609 *(inst)++ = (unsigned char)(high_words) ? 0xF3 : 0xF2; \
2610 *(inst)++ = (unsigned char)0x0f; \
2611 *(inst)++ = (unsigned char)0x70; \
2612 x86_reg_emit ((inst), (dreg), (sreg)); \
2613 *(inst)++ = (unsigned char)mask; \
2616 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
2618 x86_codegen_pre(&(inst), 5); \
2619 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
2620 x86_imm_emit8 ((inst), (imm)); \
2623 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
2625 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \