3 * Copyright (c) 2002-2003 Sergey Chaban <serge@wildwestsoftware.com>
4 * Copyright 2005-2011 Novell Inc
5 * Copyright 2011 Xamarin Inc
6 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 typedef unsigned int arminstr_t;
18 typedef unsigned int armword_t;
20 #if defined(_MSC_VER) || defined(__CC_NORCROFT)
21 void __inline _arm_emit(arminstr_t** p, arminstr_t i) {**p = i; (*p)++;}
22 # define ARM_EMIT(p, i) _arm_emit((arminstr_t**)&p, (arminstr_t)(i))
24 # define ARM_EMIT(p, i) do { arminstr_t *__ainstrp = (void*)(p); *__ainstrp = (arminstr_t)(i); (p) = (void*)(__ainstrp+1);} while (0)
27 #if defined(_MSC_VER) && !defined(ARM_NOIASM)
28 # define ARM_IASM(_expr) __emit (_expr)
30 # define ARM_IASM(_expr)
33 /* even_scale = rot << 1 */
34 #define ARM_SCALE(imm8, even_scale) ( ((imm8) >> (even_scale)) | ((imm8) << (32 - even_scale)) )
59 ARMREG_A1 = ARMREG_R0,
60 ARMREG_A2 = ARMREG_R1,
61 ARMREG_A3 = ARMREG_R2,
62 ARMREG_A4 = ARMREG_R3,
65 ARMREG_V1 = ARMREG_R4,
66 ARMREG_V2 = ARMREG_R5,
67 ARMREG_V3 = ARMREG_R6,
68 ARMREG_V4 = ARMREG_R7,
69 ARMREG_V5 = ARMREG_R8,
70 ARMREG_V6 = ARMREG_R9,
71 ARMREG_V7 = ARMREG_R10,
73 ARMREG_FP = ARMREG_R11,
74 ARMREG_IP = ARMREG_R12,
75 ARMREG_SP = ARMREG_R13,
76 ARMREG_LR = ARMREG_R14,
77 ARMREG_PC = ARMREG_R15,
97 /* XScale: acc0 on CP0 */
98 ARMREG_ACC0 = ARMREG_CR0,
100 ARMREG_MAX = ARMREG_R15
103 /* number of argument registers */
104 #define ARM_NUM_ARG_REGS 4
106 /* bitvector for all argument regs (A1-A4) */
107 #define ARM_ALL_ARG_REGS \
108 (1 << ARMREG_A1) | (1 << ARMREG_A2) | (1 << ARMREG_A3) | (1 << ARMREG_A4)
112 ARMCOND_EQ = 0x0, /* Equal; Z = 1 */
113 ARMCOND_NE = 0x1, /* Not equal, or unordered; Z = 0 */
114 ARMCOND_CS = 0x2, /* Carry set; C = 1 */
115 ARMCOND_HS = ARMCOND_CS, /* Unsigned higher or same; */
116 ARMCOND_CC = 0x3, /* Carry clear; C = 0 */
117 ARMCOND_LO = ARMCOND_CC, /* Unsigned lower */
118 ARMCOND_MI = 0x4, /* Negative; N = 1 */
119 ARMCOND_PL = 0x5, /* Positive or zero; N = 0 */
120 ARMCOND_VS = 0x6, /* Overflow; V = 1 */
121 ARMCOND_VC = 0x7, /* No overflow; V = 0 */
122 ARMCOND_HI = 0x8, /* Unsigned higher; C = 1 && Z = 0 */
123 ARMCOND_LS = 0x9, /* Unsigned lower or same; C = 0 || Z = 1 */
124 ARMCOND_GE = 0xA, /* Signed greater than or equal; N = V */
125 ARMCOND_LT = 0xB, /* Signed less than; N != V */
126 ARMCOND_GT = 0xC, /* Signed greater than; Z = 0 && N = V */
127 ARMCOND_LE = 0xD, /* Signed less than or equal; Z = 1 && N != V */
128 ARMCOND_AL = 0xE, /* Always */
129 ARMCOND_NV = 0xF, /* Never */
134 #define ARMCOND_MASK (ARMCOND_NV << ARMCOND_SHIFT)
136 #define ARM_DEF_COND(cond) (((cond) & 0xF) << ARMCOND_SHIFT)
146 ARMSHIFT_ASL = ARMSHIFT_LSL
177 /* not really opcodes */
183 ARMOP_MUL = 0x0, /* Rd := Rm*Rs */
184 ARMOP_MLA = 0x1, /* Rd := (Rm*Rs)+Rn */
192 /* for data transfers with register offset */
223 /* Generic form - all ARM instructions are conditional. */
225 arminstr_t icode : 28;
231 /* Branch or Branch with Link instructions. */
233 arminstr_t offset : 24;
235 arminstr_t tag : 3; /* 1 0 1 */
240 #define ARM_BR_MASK 7 << 25
241 #define ARM_BR_TAG ARM_BR_ID << 25
243 #define ARM_DEF_BR(offs, l, cond) ((offs) | ((l) << 24) | (ARM_BR_TAG) | (cond << ARMCOND_SHIFT))
246 #define ARM_B_COND(p, cond, offset) ARM_EMIT(p, ARM_DEF_BR(offset, 0, cond))
247 #define ARM_B(p, offs) ARM_B_COND((p), ARMCOND_AL, (offs))
248 /* branch with link */
249 #define ARM_BL_COND(p, cond, offset) ARM_EMIT(p, ARM_DEF_BR(offset, 1, cond))
250 #define ARM_BL(p, offs) ARM_BL_COND((p), ARMCOND_AL, (offs))
252 #define ARM_DEF_BX(reg,sub,cond) (0x12fff << 8 | (reg) | ((sub) << 4) | ((cond) << ARMCOND_SHIFT))
254 #define ARM_BX_COND(p, cond, reg) ARM_EMIT(p, ARM_DEF_BX(reg, 1, cond))
255 #define ARM_BX(p, reg) ARM_BX_COND((p), ARMCOND_AL, (reg))
257 #define ARM_BLX_REG_COND(p, cond, reg) ARM_EMIT(p, ARM_DEF_BX(reg, 3, cond))
258 #define ARM_BLX_REG(p, reg) ARM_BLX_REG_COND((p), ARMCOND_AL, (reg))
260 /* Data Processing Instructions - there are 3 types. */
269 arminstr_t tag : 1; /* 0 - immediate shift, 1 - reg shift */
270 arminstr_t type : 2; /* shift type - logical, arithmetic, rotate */
271 } ARMDPI_op2_reg_shift;
274 /* op2 is reg shift by imm */
276 ARMDPI_op2_reg_shift r2;
278 arminstr_t _dummy_r2 : 7;
279 arminstr_t shift : 5;
281 } ARMDPI_op2_reg_imm;
283 /* op2 is reg shift by reg */
285 ARMDPI_op2_reg_shift r2;
287 arminstr_t _dummy_r2 : 7;
288 arminstr_t pad : 1; /* always 0, to differentiate from HXFER etc. */
291 } ARMDPI_op2_reg_reg;
293 /* Data processing instrs */
295 ARMDPI_op2_imm op2_imm;
297 ARMDPI_op2_reg_shift op2_reg;
298 ARMDPI_op2_reg_imm op2_reg_imm;
299 ARMDPI_op2_reg_reg op2_reg_reg;
302 arminstr_t op2 : 12; /* raw operand 2 */
303 arminstr_t rd : 4; /* destination reg */
304 arminstr_t rn : 4; /* first operand reg */
305 arminstr_t s : 1; /* S-bit controls PSR update */
306 arminstr_t opcode : 4; /* arithmetic/logic operation */
307 arminstr_t type : 1; /* type of op2, 0 = register, 1 = immediate */
308 arminstr_t tag : 2; /* 0 0 */
314 #define ARM_DPI_MASK 3 << 26
315 #define ARM_DPI_TAG ARM_DPI_ID << 26
317 #define ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, cond) \
319 (((rot) & 0xF) << 8) | \
329 #define ARM_DEF_DPI_IMM(imm8, rot, rd, rn, s, op) \
330 ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, ARMCOND_AL)
333 #define ARM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
334 ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond))
335 #define ARM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
336 ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond))
339 #define ARM_IASM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
340 ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond))
341 #define ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
342 ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond))
346 #define ARM_DEF_DPI_REG_IMMSHIFT_COND(rm, shift_type, imm_shift, rd, rn, s, op, cond) \
348 ((shift_type & 3) << 5) | \
349 (((imm_shift) & 0x1F) << 7) | \
358 #define ARM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
359 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 0, (op), cond))
361 #define ARM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
362 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 1, (op), cond))
364 #define ARM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \
365 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond))
367 #define ARM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \
368 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond))
371 #define ARM_IASM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
372 ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 0, (op), cond))
374 #define ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
375 ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 1, (op), cond))
377 #define ARM_IASM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \
378 ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond))
380 #define ARM_IASM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \
381 ARM_IASM_EMIT(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond))
384 /* Rd := Rn op (Rm shift_type Rs) */
385 #define ARM_DEF_DPI_REG_REGSHIFT_COND(rm, shift_type, rs, rd, rn, s, op, cond) \
388 ((shift_type & 3) << 5) | \
398 #define ARM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
399 ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 0, (op), cond))
401 #define ARM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
402 ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 1, (op), cond))
405 #define ARM_IASM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
406 ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 0, (op), cond))
408 #define ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
409 ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 1, (op), cond))
413 /* Multiple register transfer. */
415 arminstr_t reg_list : 16; /* bitfield */
416 arminstr_t rn : 4; /* base reg */
417 arminstr_t ls : 1; /* load(1)/store(0) */
418 arminstr_t wb : 1; /* write-back "!" */
419 arminstr_t s : 1; /* restore PSR, force user bit */
420 arminstr_t u : 1; /* up/down */
421 arminstr_t p : 1; /* pre(1)/post(0) index */
422 arminstr_t tag : 3; /* 1 0 0 */
427 #define ARM_MRT_MASK 7 << 25
428 #define ARM_MRT_TAG ARM_MRT_ID << 25
430 #define ARM_DEF_MRT(regs, rn, l, w, s, u, p, cond) \
442 #define ARM_LDM(p, base, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, base, 1, 0, 0, 1, 0, ARMCOND_AL))
443 #define ARM_STM(p, base, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, base, 0, 0, 0, 1, 0, ARMCOND_AL))
445 /* stmdb sp!, {regs} */
446 #define ARM_PUSH(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL))
447 #define ARM_IASM_PUSH(regs) ARM_IASM(ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL))
449 /* ldmia sp!, {regs} */
450 #define ARM_POP(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL))
451 #define ARM_IASM_POP(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL))
453 /* ldmia sp, {regs} ; (no write-back) */
454 #define ARM_POP_NWB(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL))
455 #define ARM_IASM_POP_NWB(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL))
457 #define ARM_PUSH1(p, r1) ARM_PUSH(p, (1 << r1))
458 #define ARM_PUSH2(p, r1, r2) ARM_PUSH(p, (1 << r1) | (1 << r2))
459 #define ARM_PUSH3(p, r1, r2, r3) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3))
460 #define ARM_PUSH4(p, r1, r2, r3, r4) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4))
461 #define ARM_PUSH5(p, r1, r2, r3, r4, r5) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5))
462 #define ARM_PUSH6(p, r1, r2, r3, r4, r5, r6) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6))
463 #define ARM_PUSH7(p, r1, r2, r3, r4, r5, r6, r7) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7))
464 #define ARM_PUSH8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8))
466 #define ARM_POP8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8))
467 #define ARM_POP7(p, r1, r2, r3, r4, r5, r6, r7) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7))
468 #define ARM_POP6(p, r1, r2, r3, r4, r5, r6) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6))
469 #define ARM_POP5(p, r1, r2, r3, r4, r5) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5))
470 #define ARM_POP4(p, r1, r2, r3, r4) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4))
471 #define ARM_POP3(p, r1, r2, r3) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3))
472 #define ARM_POP2(p, r1, r2) ARM_POP(p, (1 << r1) | (1 << r2))
473 #define ARM_POP1(p, r1) ARM_POP(p, (1 << r1))
476 /* Multiply instructions */
479 arminstr_t tag2 : 4; /* 9 */
484 arminstr_t opcode : 3;
490 #define ARM_DEF_MUL_COND(op, rd, rm, rs, rn, s, cond) \
500 /* Rd := (Rm * Rs)[31:0]; 32 x 32 -> 32 */
501 #define ARM_MUL_COND(p, rd, rm, rs, cond) \
502 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond))
503 #define ARM_UMULL_COND(p, rdhi, rdlo, rm, rs, cond) \
504 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_UMULL, rdhi, rm, rs, rdlo, 0, cond))
505 #define ARM_SMULL_COND(p, rdhi, rdlo, rm, rs, cond) \
506 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMULL, rdhi, rm, rs, rdlo, 0, cond))
507 #define ARM_MUL(p, rd, rm, rs) \
508 ARM_MUL_COND(p, rd, rm, rs, ARMCOND_AL)
509 #define ARM_UMULL(p, rdhi, rdlo, rm, rs) \
510 ARM_UMULL_COND(p, rdhi, rdlo, rm, rs, ARMCOND_AL)
511 #define ARM_SMULL(p, rdhi, rdlo, rm, rs) \
512 ARM_SMULL_COND(p, rdhi, rdlo, rm, rs, ARMCOND_AL)
513 #define ARM_MULS_COND(p, rd, rm, rs, cond) \
514 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond))
515 #define ARM_MULS(p, rd, rm, rs) \
516 ARM_MULS_COND(p, rd, rm, rs, ARMCOND_AL)
517 #define ARM_MUL_REG_REG(p, rd, rm, rs) ARM_MUL(p, rd, rm, rs)
518 #define ARM_MULS_REG_REG(p, rd, rm, rs) ARM_MULS(p, rd, rm, rs)
519 #define ARM_UMULL_REG_REG(p, rdhi, rdlo, rm, rs) ARM_UMULL(p, rdhi, rdlo, rm, rs)
520 #define ARM_SMULL_REG_REG(p, rdhi, rdlo, rm, rs) ARM_SMULL(p, rdhi, rdlo, rm, rs)
523 #define ARM_IASM_MUL_COND(rd, rm, rs, cond) \
524 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond))
525 #define ARM_IASM_MUL(rd, rm, rs) \
526 ARM_IASM_MUL_COND(rd, rm, rs, ARMCOND_AL)
527 #define ARM_IASM_MULS_COND(rd, rm, rs, cond) \
528 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond))
529 #define ARM_IASM_MULS(rd, rm, rs) \
530 ARM_IASM_MULS_COND(rd, rm, rs, ARMCOND_AL)
533 /* Rd := (Rm * Rs) + Rn; 32x32+32->32 */
534 #define ARM_MLA_COND(p, rd, rm, rs, rn, cond) \
535 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond))
536 #define ARM_MLA(p, rd, rm, rs, rn) \
537 ARM_MLA_COND(p, rd, rm, rs, rn, ARMCOND_AL)
538 #define ARM_MLAS_COND(p, rd, rm, rs, rn, cond) \
539 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond))
540 #define ARM_MLAS(p, rd, rm, rs, rn) \
541 ARM_MLAS_COND(p, rd, rm, rs, rn, ARMCOND_AL)
544 #define ARM_IASM_MLA_COND(rd, rm, rs, rn, cond) \
545 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond))
546 #define ARM_IASM_MLA(rd, rm, rs, rn) \
547 ARM_IASM_MLA_COND(rd, rm, rs, rn, ARMCOND_AL)
548 #define ARM_IASM_MLAS_COND(rd, rm, rs, rn, cond) \
549 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond))
550 #define ARM_IASM_MLAS(rd, rm, rs, rn) \
551 ARM_IASM_MLAS_COND(rd, rm, rs, rn, ARMCOND_AL)
555 /* Word/byte transfer */
557 ARMDPI_op2_reg_imm op2_reg_imm;
559 arminstr_t op2_imm : 12;
565 arminstr_t u : 1; /* down(0) / up(1) */
566 arminstr_t p : 1; /* post-index(0) / pre-index(1) */
567 arminstr_t type : 1; /* imm(0) / register(1) */
568 arminstr_t tag : 2; /* 0 1 */
573 #define ARM_WXFER_ID 1
574 #define ARM_WXFER_MASK 3 << 26
575 #define ARM_WXFER_TAG ARM_WXFER_ID << 26
578 #define ARM_DEF_WXFER_IMM(imm12, rd, rn, ls, wb, b, p, cond) \
579 ((((int)imm12) < 0) ? -(int)(imm12) : (imm12)) | \
585 (((int)(imm12) >= 0) << 23) | \
590 #define ARM_WXFER_MAX_OFFS 0xFFF
592 /* this macro checks for imm12 bounds */
593 #define ARM_EMIT_WXFER_IMM(ptr, imm12, rd, rn, ls, wb, b, p, cond) \
595 int _imm12 = (int)(imm12) < -ARM_WXFER_MAX_OFFS \
596 ? -ARM_WXFER_MAX_OFFS \
597 : (int)(imm12) > ARM_WXFER_MAX_OFFS \
598 ? ARM_WXFER_MAX_OFFS \
601 ARM_DEF_WXFER_IMM(_imm12, (rd), (rn), (ls), (wb), (b), (p), (cond))); \
606 /* immediate offset, post-index */
607 #define ARM_LDR_IMM_POST_COND(p, rd, rn, imm, cond) \
608 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 0, 0, cond))
610 #define ARM_LDR_IMM_POST(p, rd, rn, imm) ARM_LDR_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
612 #define ARM_LDRB_IMM_POST_COND(p, rd, rn, imm, cond) \
613 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 1, 0, cond))
615 #define ARM_LDRB_IMM_POST(p, rd, rn, imm) ARM_LDRB_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
617 /* immediate offset, pre-index */
618 #define ARM_LDR_IMM_COND(p, rd, rn, imm, cond) \
619 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 0, 1, cond))
621 #define ARM_LDR_IMM(p, rd, rn, imm) ARM_LDR_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
623 #define ARM_LDRB_IMM_COND(p, rd, rn, imm, cond) \
624 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 1, 1, cond))
626 #define ARM_LDRB_IMM(p, rd, rn, imm) ARM_LDRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
629 /* immediate offset, post-index */
630 #define ARM_STR_IMM_POST_COND(p, rd, rn, imm, cond) \
631 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 0, cond))
633 #define ARM_STR_IMM_POST(p, rd, rn, imm) ARM_STR_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
635 #define ARM_STRB_IMM_POST_COND(p, rd, rn, imm, cond) \
636 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 1, 0, cond))
638 #define ARM_STRB_IMM_POST(p, rd, rn, imm) ARM_STRB_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
640 /* immediate offset, pre-index */
641 #define ARM_STR_IMM_COND(p, rd, rn, imm, cond) \
642 ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 0, 0, 1, cond)
643 /* ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 1, cond)) */
645 #define ARM_STR_IMM(p, rd, rn, imm) ARM_STR_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
647 #define ARM_STRB_IMM_COND(p, rd, rn, imm, cond) \
648 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 1, 1, cond))
650 #define ARM_STRB_IMM(p, rd, rn, imm) ARM_STRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
653 #define ARM_STR_IMM_WB_COND(p, rd, rn, imm, cond) \
654 ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 1, 0, 1, cond)
655 #define ARM_STR_IMM_WB(p, rd, rn, imm) ARM_STR_IMM_WB_COND(p, rd, rn, imm, ARMCOND_AL)
658 #define ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, u, p, cond) \
660 ((shift_type) << 5) | \
673 #define ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
674 ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_UP, p, cond)
675 #define ARM_DEF_WXFER_REG_MINUS_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
676 ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_DOWN, p, cond)
679 #define ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
680 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 0, 1, cond))
681 #define ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
682 ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
683 #define ARM_LDR_REG_REG(p, rd, rn, rm) \
684 ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
686 #define ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
687 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 1, 1, cond))
688 #define ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
689 ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
690 #define ARM_LDRB_REG_REG(p, rd, rn, rm) \
691 ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
693 #define ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
694 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 0, 1, cond))
695 #define ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
696 ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
697 #define ARM_STR_REG_REG(p, rd, rn, rm) \
698 ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
701 #define ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
702 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 1, 1, cond))
703 #define ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
704 ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
705 #define ARM_STRB_REG_REG(p, rd, rn, rm) \
706 ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
710 /* Half-word or byte (signed) transfer. */
712 arminstr_t rm : 4; /* imm_lo */
713 arminstr_t tag3 : 1; /* 1 */
714 arminstr_t h : 1; /* half-word or byte */
715 arminstr_t s : 1; /* sign-extend or zero-extend */
716 arminstr_t tag2 : 1; /* 1 */
717 arminstr_t imm_hi : 4;
722 arminstr_t type : 1; /* imm(1) / reg(0) */
723 arminstr_t u : 1; /* +- */
724 arminstr_t p : 1; /* pre/post-index */
729 #define ARM_HXFER_ID 0
730 #define ARM_HXFER_ID2 1
731 #define ARM_HXFER_ID3 1
732 #define ARM_HXFER_MASK ((0x7 << 25) | (0x9 << 4))
733 #define ARM_HXFER_TAG ((ARM_HXFER_ID << 25) | (ARM_HXFER_ID2 << 7) | (ARM_HXFER_ID3 << 4))
735 #define ARM_DEF_HXFER_IMM_COND(imm, h, s, rd, rn, ls, wb, p, cond) \
736 ((imm) < 0?(-(imm)) & 0xF:(imm) & 0xF) | \
739 ((imm) < 0?((-(imm)) << 4) & 0xF00:((imm) << 4) & 0xF00) | \
745 (((int)(imm) >= 0) << 23) | \
750 #define ARM_LDRH_IMM_COND(p, rd, rn, imm, cond) \
751 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond))
752 #define ARM_LDRH_IMM(p, rd, rn, imm) \
753 ARM_LDRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
754 #define ARM_LDRSH_IMM_COND(p, rd, rn, imm, cond) \
755 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
756 #define ARM_LDRSH_IMM(p, rd, rn, imm) \
757 ARM_LDRSH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
758 #define ARM_LDRSB_IMM_COND(p, rd, rn, imm, cond) \
759 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
760 #define ARM_LDRSB_IMM(p, rd, rn, imm) \
761 ARM_LDRSB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
764 #define ARM_STRH_IMM_COND(p, rd, rn, imm, cond) \
765 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond))
766 #define ARM_STRH_IMM(p, rd, rn, imm) \
767 ARM_STRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
770 #define ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, u, p, cond) \
784 #define ARM_DEF_HXFER_REG_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \
785 ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_UP, p, cond)
786 #define ARM_DEF_HXFER_REG_MINUS_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \
787 ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_DOWN, p, cond)
789 #define ARM_LDRH_REG_REG_COND(p, rd, rm, rn, cond) \
790 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond))
791 #define ARM_LDRH_REG_REG(p, rd, rm, rn) \
792 ARM_LDRH_REG_REG_COND(p, rd, rm, rn, ARMCOND_AL)
793 #define ARM_LDRSH_REG_REG_COND(p, rd, rm, rn, cond) \
794 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
795 #define ARM_LDRSH_REG_REG(p, rd, rm, rn) \
796 ARM_LDRSH_REG_REG_COND(p, rd, rm, rn, ARMCOND_AL)
797 #define ARM_LDRSB_REG_REG_COND(p, rd, rm, rn, cond) \
798 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
799 #define ARM_LDRSB_REG_REG(p, rd, rm, rn) ARM_LDRSB_REG_REG_COND(p, rd, rm, rn, ARMCOND_AL)
801 #define ARM_STRH_REG_REG_COND(p, rd, rm, rn, cond) \
802 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond))
803 #define ARM_STRH_REG_REG(p, rd, rm, rn) \
804 ARM_STRH_REG_REG_COND(p, rd, rm, rn, ARMCOND_AL)
811 arminstr_t tag3 : 8; /* 0x9 */
816 arminstr_t tag : 5; /* 0x2 */
821 #define ARM_SWP_ID2 9
822 #define ARM_SWP_MASK ((0x1F << 23) | (3 << 20) | (0xFF << 4))
823 #define ARM_SWP_TAG ((ARM_SWP_ID << 23) | (ARM_SWP_ID2 << 4))
827 /* Software interrupt */
834 #define ARM_SWI_ID 0xF
835 #define ARM_SWI_MASK (0xF << 24)
836 #define ARM_SWI_TAG (ARM_SWI_ID << 24)
840 /* Co-processor Data Processing */
843 arminstr_t tag2 : 1; /* 0 */
845 arminstr_t cpn : 4; /* CP number */
849 arminstr_t tag : 4; /* 0xE */
853 #define ARM_CDP_ID 0xE
854 #define ARM_CDP_ID2 0
855 #define ARM_CDP_MASK ((0xF << 24) | (1 << 4))
856 #define ARM_CDP_TAG ((ARM_CDP_ID << 24) | (ARM_CDP_ID2 << 4))
859 /* Co-processor Data Transfer (ldc/stc) */
875 #define ARM_CDT_MASK (7 << 25)
876 #define ARM_CDT_TAG (ARM_CDT_ID << 25)
879 /* Co-processor Register Transfer (mcr/mrc) */
893 #define ARM_CRT_ID 0xE
894 #define ARM_CRT_ID2 0x1
895 #define ARM_CRT_MASK ((0xF << 24) | (1 << 4))
896 #define ARM_CRT_TAG ((ARM_CRT_ID << 24) | (ARM_CRT_ID2 << 4))
898 /* Move register to PSR. */
900 ARMDPI_op2_imm op2_imm;
903 arminstr_t pad : 8; /* 0 */
904 arminstr_t tag4 : 4; /* 0xF */
906 arminstr_t tag3 : 2; /* 0x2 */
908 arminstr_t tag2 : 2; /* 0x2 */
910 arminstr_t tag : 2; /* 0 */
916 #define ARM_MSR_ID2 2
917 #define ARM_MSR_ID3 2
918 #define ARM_MSR_ID4 0xF
919 #define ARM_MSR_MASK ((3 << 26) | \
923 #define ARM_MSR_TAG ((ARM_MSR_ID << 26) | \
924 (ARM_MSR_ID2 << 23) | \
925 (ARM_MSR_ID3 << 20) | \
929 /* Move PSR to register. */
931 arminstr_t tag3 : 12;
934 arminstr_t sel : 1; /* CPSR | SPSR */
940 #define ARM_MRS_ID2 0xF
941 #define ARM_MRS_ID3 0
942 #define ARM_MRS_MASK ((0x1F << 23) | (0x3F << 16) | 0xFFF)
943 #define ARM_MRS_TAG ((ARM_MRS_ID << 23) | (ARM_MRS_ID2 << 16) | ARM_MRS_ID3)
947 #include "mono/arch/arm/arm_dpimacros.h"
949 #define ARM_NOP(p) ARM_MOV_REG_REG(p, ARMREG_R0, ARMREG_R0)
952 #define ARM_SHL_IMM_COND(p, rd, rm, imm, cond) \
953 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond)
954 #define ARM_SHL_IMM(p, rd, rm, imm) \
955 ARM_SHL_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
956 #define ARM_SHLS_IMM_COND(p, rd, rm, imm, cond) \
957 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond)
958 #define ARM_SHLS_IMM(p, rd, rm, imm) \
959 ARM_SHLS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
961 #define ARM_SHR_IMM_COND(p, rd, rm, imm, cond) \
962 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond)
963 #define ARM_SHR_IMM(p, rd, rm, imm) \
964 ARM_SHR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
965 #define ARM_SHRS_IMM_COND(p, rd, rm, imm, cond) \
966 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond)
967 #define ARM_SHRS_IMM(p, rd, rm, imm) \
968 ARM_SHRS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
970 #define ARM_SAR_IMM_COND(p, rd, rm, imm, cond) \
971 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond)
972 #define ARM_SAR_IMM(p, rd, rm, imm) \
973 ARM_SAR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
974 #define ARM_SARS_IMM_COND(p, rd, rm, imm, cond) \
975 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond)
976 #define ARM_SARS_IMM(p, rd, rm, imm) \
977 ARM_SARS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
979 #define ARM_ROR_IMM_COND(p, rd, rm, imm, cond) \
980 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond)
981 #define ARM_ROR_IMM(p, rd, rm, imm) \
982 ARM_ROR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
983 #define ARM_RORS_IMM_COND(p, rd, rm, imm, cond) \
984 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond)
985 #define ARM_RORS_IMM(p, rd, rm, imm) \
986 ARM_RORS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
988 #define ARM_SHL_REG_COND(p, rd, rm, rs, cond) \
989 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond)
990 #define ARM_SHL_REG(p, rd, rm, rs) \
991 ARM_SHL_REG_COND(p, rd, rm, rs, ARMCOND_AL)
992 #define ARM_SHLS_REG_COND(p, rd, rm, rs, cond) \
993 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond)
994 #define ARM_SHLS_REG(p, rd, rm, rs) \
995 ARM_SHLS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
996 #define ARM_SHLS_REG_REG(p, rd, rm, rs) ARM_SHLS_REG(p, rd, rm, rs)
998 #define ARM_SHR_REG_COND(p, rd, rm, rs, cond) \
999 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond)
1000 #define ARM_SHR_REG(p, rd, rm, rs) \
1001 ARM_SHR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1002 #define ARM_SHRS_REG_COND(p, rd, rm, rs, cond) \
1003 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond)
1004 #define ARM_SHRS_REG(p, rd, rm, rs) \
1005 ARM_SHRS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1006 #define ARM_SHRS_REG_REG(p, rd, rm, rs) ARM_SHRS_REG(p, rd, rm, rs)
1008 #define ARM_SAR_REG_COND(p, rd, rm, rs, cond) \
1009 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond)
1010 #define ARM_SAR_REG(p, rd, rm, rs) \
1011 ARM_SAR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1012 #define ARM_SARS_REG_COND(p, rd, rm, rs, cond) \
1013 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond)
1014 #define ARM_SARS_REG(p, rd, rm, rs) \
1015 ARM_SARS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1016 #define ARM_SARS_REG_REG(p, rd, rm, rs) ARM_SARS_REG(p, rd, rm, rs)
1018 #define ARM_ROR_REG_COND(p, rd, rm, rs, cond) \
1019 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond)
1020 #define ARM_ROR_REG(p, rd, rm, rs) \
1021 ARM_ROR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1022 #define ARM_RORS_REG_COND(p, rd, rm, rs, cond) \
1023 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond)
1024 #define ARM_RORS_REG(p, rd, rm, rs) \
1025 ARM_RORS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1026 #define ARM_RORS_REG_REG(p, rd, rm, rs) ARM_RORS_REG(p, rd, rm, rs)
1028 #define ARM_DBRK(p) ARM_EMIT(p, 0xE6000010)
1029 #define ARM_IASM_DBRK() ARM_IASM_EMIT(0xE6000010)
1031 #define ARM_INC(p, reg) ARM_ADD_REG_IMM8(p, reg, reg, 1)
1032 #define ARM_DEC(p, reg) ARM_SUB_REG_IMM8(p, reg, reg, 1)
1034 #define ARM_MLS(p, rd, rn, rm, ra) ARM_EMIT((p), (ARMCOND_AL << 28) | (0x6 << 20) | ((rd) << 16) | ((ra) << 12) | ((rm) << 8) | (0x9 << 4) | ((rn) << 0))
1038 /* Count leading zeros, CLZ{cond} Rd, Rm */
1041 arminstr_t tag2 : 8;
1043 arminstr_t tag : 12;
1044 arminstr_t cond : 4;
1047 #define ARM_CLZ_ID 0x16F
1048 #define ARM_CLZ_ID2 0xF1
1049 #define ARM_CLZ_MASK ((0xFFF << 16) | (0xFF < 4))
1050 #define ARM_CLZ_TAG ((ARM_CLZ_ID << 16) | (ARM_CLZ_ID2 << 4))
1060 ARMInstrWXfer wxfer;
1061 ARMInstrHXfer hxfer;
1071 ARMInstrGeneric generic;
1077 #define ARM_MOVW_REG_IMM_COND(p, rd, imm16, cond) ARM_EMIT(p, (((cond) << 28) | (3 << 24) | (0 << 20) | ((((guint32)(imm16)) >> 12) << 16) | ((rd) << 12) | (((guint32)(imm16)) & 0xfff)))
1078 #define ARM_MOVW_REG_IMM(p, rd, imm16) ARM_MOVW_REG_IMM_COND ((p), (rd), (imm16), ARMCOND_AL)
1080 #define ARM_MOVT_REG_IMM_COND(p, rd, imm16, cond) ARM_EMIT(p, (((cond) << 28) | (3 << 24) | (4 << 20) | ((((guint32)(imm16)) >> 12) << 16) | ((rd) << 12) | (((guint32)(imm16)) & 0xfff)))
1081 #define ARM_MOVT_REG_IMM(p, rd, imm16) ARM_MOVT_REG_IMM_COND ((p), (rd), (imm16), ARMCOND_AL)
1084 #define ARM_DEF_MCR_COND(coproc, opc1, rt, crn, crm, opc2, cond) \
1085 ARM_DEF_COND ((cond)) | ((0xe << 24) | (((opc1) & 0x7) << 21) | (0 << 20) | (((crn) & 0xf) << 16) | (((rt) & 0xf) << 12) | (((coproc) & 0xf) << 8) | (((opc2) & 0x7) << 5) | (1 << 4) | (((crm) & 0xf) << 0))
1087 #define ARM_MCR_COND(p, coproc, opc1, rt, crn, crm, opc2, cond) \
1088 ARM_EMIT(p, ARM_DEF_MCR_COND ((coproc), (opc1), (rt), (crn), (crm), (opc2), (cond)))
1090 #define ARM_MCR(p, coproc, opc1, rt, crn, crm, opc2) \
1091 ARM_MCR_COND ((p), (coproc), (opc1), (rt), (crn), (crm), (opc2), ARMCOND_AL)
1094 #define ARM_DEF_MRC_COND(coproc, opc1, rt, crn, crm, opc2, cond) \
1095 ARM_DEF_COND ((cond)) | ((0xe << 24) | (((opc1) & 0x7) << 21) | (1 << 20) | (((crn) & 0xf) << 16) | (((rt) & 0xf) << 12) | (((coproc) & 0xf) << 8) | (((opc2) & 0x7) << 5) | (1 << 4) | (((crm) & 0xf) << 0))
1097 #define ARM_MRC_COND(p, coproc, opc1, rt, crn, crm, opc2, cond) \
1098 ARM_EMIT(p, ARM_DEF_MRC_COND ((coproc), (opc1), (rt), (crn), (crm), (opc2), (cond)))
1100 #define ARM_MRC(p, coproc, opc1, rt, crn, crm, opc2) \
1101 ARM_MRC_COND ((p), (coproc), (opc1), (rt), (crn), (crm), (opc2), ARMCOND_AL)
1104 #define ARM_SDIV_COND(p, rd, rn, rm, cond) ARM_EMIT (p, (((cond) << 28) | (0xe << 23) | (0x1 << 20) | ((rd) << 16) | (0xf << 12) | ((rm) << 8) | (0x0 << 5) | (0x1 << 4) | ((rn) << 0)))
1105 #define ARM_SDIV(p, rd, rn, rm) ARM_SDIV_COND ((p), (rd), (rn), (rm), ARMCOND_AL)
1107 #define ARM_UDIV_COND(p, rd, rn, rm, cond) ARM_EMIT (p, (((cond) << 28) | (0xe << 23) | (0x3 << 20) | ((rd) << 16) | (0xf << 12) | ((rm) << 8) | (0x0 << 5) | (0x1 << 4) | ((rn) << 0)))
1108 #define ARM_UDIV(p, rd, rn, rm) ARM_UDIV_COND ((p), (rd), (rn), (rm), ARMCOND_AL)
1116 #define ARM_DMB(p, option) ARM_EMIT ((p), ((0xf << 28) | (0x57 << 20) | (0xf << 16) | (0xf << 12) | (0x0 << 8) | (0x5 << 4) | ((option) << 0)))
1118 #define ARM_LDREX_REG(p, rt, rn) ARM_EMIT ((p), ((ARMCOND_AL << 28) | (0xc << 21) | (0x1 << 20) | ((rn) << 16) | ((rt) << 12)) | (0xf << 8) | (0x9 << 4) | 0xf << 0)
1120 #define ARM_STREX_REG(p, rd, rt, rn) ARM_EMIT ((p), ((ARMCOND_AL << 28) | (0xc << 21) | (0x0 << 20) | ((rn) << 16) | ((rd) << 12)) | (0xf << 8) | (0x9 << 4) | ((rt) << 0))