3 * Copyright (c) 2002 Sergey Chaban <serge@wildwestsoftware.com>
14 typedef unsigned int arminstr_t;
15 typedef unsigned int armword_t;
17 /* Helper functions */
18 arminstr_t* arm_emit_std_prologue(arminstr_t* p, unsigned int local_size);
19 arminstr_t* arm_emit_std_epilogue(arminstr_t* p, unsigned int local_size, int pop_regs);
20 arminstr_t* arm_emit_lean_prologue(arminstr_t* p, unsigned int local_size, int push_regs);
21 int arm_is_power_of_2(armword_t val);
22 int calc_arm_mov_const_shift(armword_t val);
23 int is_arm_const(armword_t val);
24 int arm_bsf(armword_t val);
25 arminstr_t* arm_mov_reg_imm32_cond(arminstr_t* p, int reg, armword_t imm32, int cond);
26 arminstr_t* arm_mov_reg_imm32(arminstr_t* p, int reg, armword_t imm32);
30 #if defined(_MSC_VER) || defined(__CC_NORCROFT)
31 void __inline _arm_emit(arminstr_t** p, arminstr_t i) {**p = i; (*p)++;}
32 # define ARM_EMIT(p, i) _arm_emit((arminstr_t**)&p, (arminstr_t)(i))
34 # define ARM_EMIT(p, i) do { arminstr_t *__ainstrp = (void*)(p); *__ainstrp = (arminstr_t)(i); (p) = (void*)(__ainstrp+1);} while (0)
37 #if defined(_MSC_VER) && !defined(ARM_NOIASM)
38 # define ARM_IASM(_expr) __emit (_expr)
40 # define ARM_IASM(_expr)
43 /* even_scale = rot << 1 */
44 #define ARM_SCALE(imm8, even_scale) ( ((imm8) >> (even_scale)) | ((imm8) << (32 - even_scale)) )
69 ARMREG_A1 = ARMREG_R0,
70 ARMREG_A2 = ARMREG_R1,
71 ARMREG_A3 = ARMREG_R2,
72 ARMREG_A4 = ARMREG_R3,
75 ARMREG_V1 = ARMREG_R4,
76 ARMREG_V2 = ARMREG_R5,
77 ARMREG_V3 = ARMREG_R6,
78 ARMREG_V4 = ARMREG_R7,
79 ARMREG_V5 = ARMREG_R8,
80 ARMREG_V6 = ARMREG_R9,
81 ARMREG_V7 = ARMREG_R10,
83 ARMREG_FP = ARMREG_R11,
84 ARMREG_IP = ARMREG_R12,
85 ARMREG_SP = ARMREG_R13,
86 ARMREG_LR = ARMREG_R14,
87 ARMREG_PC = ARMREG_R15,
107 /* XScale: acc0 on CP0 */
108 ARMREG_ACC0 = ARMREG_CR0,
110 ARMREG_MAX = ARMREG_R15
113 /* number of argument registers */
114 #define ARM_NUM_ARG_REGS 4
116 /* bitvector for all argument regs (A1-A4) */
117 #define ARM_ALL_ARG_REGS \
118 (1 << ARMREG_A1) | (1 << ARMREG_A2) | (1 << ARMREG_A3) | (1 << ARMREG_A4)
122 ARMCOND_EQ = 0x0, /* Equal; Z = 1 */
123 ARMCOND_NE = 0x1, /* Not equal, or unordered; Z = 0 */
124 ARMCOND_CS = 0x2, /* Carry set; C = 1 */
125 ARMCOND_HS = ARMCOND_CS, /* Unsigned higher or same; */
126 ARMCOND_CC = 0x3, /* Carry clear; C = 0 */
127 ARMCOND_LO = ARMCOND_CC, /* Unsigned lower */
128 ARMCOND_MI = 0x4, /* Negative; N = 1 */
129 ARMCOND_PL = 0x5, /* Positive or zero; N = 0 */
130 ARMCOND_VS = 0x6, /* Overflow; V = 1 */
131 ARMCOND_VC = 0x7, /* No overflow; V = 0 */
132 ARMCOND_HI = 0x8, /* Unsigned higher; C = 1 && Z = 0 */
133 ARMCOND_LS = 0x9, /* Unsigned lower or same; C = 0 || Z = 1 */
134 ARMCOND_GE = 0xA, /* Signed greater than or equal; N = V */
135 ARMCOND_LT = 0xB, /* Signed less than; N != V */
136 ARMCOND_GT = 0xC, /* Signed greater than; Z = 0 && N = V */
137 ARMCOND_LE = 0xD, /* Signed less than or equal; Z = 1 && N != V */
138 ARMCOND_AL = 0xE, /* Always */
139 ARMCOND_NV = 0xF, /* Never */
144 #define ARMCOND_MASK (ARMCOND_NV << ARMCOND_SHIFT)
146 #define ARM_DEF_COND(cond) (((cond) & 0xF) << ARMCOND_SHIFT)
156 ARMSHIFT_ASL = ARMSHIFT_LSL
187 /* not really opcodes */
193 ARMOP_MUL = 0x0, /* Rd := Rm*Rs */
194 ARMOP_MLA = 0x1, /* Rd := (Rm*Rs)+Rn */
202 /* for data transfers with register offset */
233 /* Generic form - all ARM instructions are conditional. */
235 arminstr_t icode : 28;
241 /* Branch or Branch with Link instructions. */
243 arminstr_t offset : 24;
245 arminstr_t tag : 3; /* 1 0 1 */
250 #define ARM_BR_MASK 7 << 25
251 #define ARM_BR_TAG ARM_BR_ID << 25
253 #define ARM_DEF_BR(offs, l, cond) ((offs) | ((l) << 24) | (ARM_BR_TAG) | (cond << ARMCOND_SHIFT))
256 #define ARM_B_COND(p, cond, offset) ARM_EMIT(p, ARM_DEF_BR(offset, 0, cond))
257 #define ARM_B(p, offs) ARM_B_COND((p), ARMCOND_AL, (offs))
258 /* branch with link */
259 #define ARM_BL_COND(p, cond, offset) ARM_EMIT(p, ARM_DEF_BR(offset, 1, cond))
260 #define ARM_BL(p, offs) ARM_BL_COND((p), ARMCOND_AL, (offs))
264 /* Data Processing Instructions - there are 3 types. */
273 arminstr_t tag : 1; /* 0 - immediate shift, 1 - reg shift */
274 arminstr_t type : 2; /* shift type - logical, arithmetic, rotate */
275 } ARMDPI_op2_reg_shift;
278 /* op2 is reg shift by imm */
280 ARMDPI_op2_reg_shift r2;
282 arminstr_t _dummy_r2 : 7;
283 arminstr_t shift : 5;
285 } ARMDPI_op2_reg_imm;
287 /* op2 is reg shift by reg */
289 ARMDPI_op2_reg_shift r2;
291 arminstr_t _dummy_r2 : 7;
292 arminstr_t pad : 1; /* always 0, to differentiate from HXFER etc. */
295 } ARMDPI_op2_reg_reg;
297 /* Data processing instrs */
299 ARMDPI_op2_imm op2_imm;
301 ARMDPI_op2_reg_shift op2_reg;
302 ARMDPI_op2_reg_imm op2_reg_imm;
303 ARMDPI_op2_reg_reg op2_reg_reg;
306 arminstr_t op2 : 12; /* raw operand 2 */
307 arminstr_t rd : 4; /* destination reg */
308 arminstr_t rn : 4; /* first operand reg */
309 arminstr_t s : 1; /* S-bit controls PSR update */
310 arminstr_t opcode : 4; /* arithmetic/logic operation */
311 arminstr_t type : 1; /* type of op2, 0 = register, 1 = immediate */
312 arminstr_t tag : 2; /* 0 0 */
318 #define ARM_DPI_MASK 3 << 26
319 #define ARM_DPI_TAG ARM_DPI_ID << 26
321 #define ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, cond) \
323 (((rot) & 0xF) << 8) | \
333 #define ARM_DEF_DPI_IMM(imm8, rot, rd, rn, s, op) \
334 ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, ARMCOND_AL)
337 #define ARM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
338 ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond))
339 #define ARM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
340 ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond))
343 #define ARM_IASM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
344 ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond))
345 #define ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
346 ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond))
350 #define ARM_DEF_DPI_REG_IMMSHIFT_COND(rm, shift_type, imm_shift, rd, rn, s, op, cond) \
352 ((shift_type & 3) << 5) | \
353 (((imm_shift) & 0x1F) << 7) | \
362 #define ARM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
363 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 0, (op), cond))
365 #define ARM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
366 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 1, (op), cond))
368 #define ARM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \
369 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond))
371 #define ARM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \
372 ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond))
375 #define ARM_IASM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
376 ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 0, (op), cond))
378 #define ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
379 ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 1, (op), cond))
381 #define ARM_IASM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \
382 ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond))
384 #define ARM_IASM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \
385 ARM_IASM_EMIT(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond))
388 /* Rd := Rn op (Rm shift_type Rs) */
389 #define ARM_DEF_DPI_REG_REGSHIFT_COND(rm, shift_type, rs, rd, rn, s, op, cond) \
392 ((shift_type & 3) << 5) | \
402 #define ARM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
403 ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 0, (op), cond))
405 #define ARM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
406 ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 1, (op), cond))
409 #define ARM_IASM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
410 ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 0, (op), cond))
412 #define ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
413 ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 1, (op), cond))
417 /* Multiple register transfer. */
419 arminstr_t reg_list : 16; /* bitfield */
420 arminstr_t rn : 4; /* base reg */
421 arminstr_t ls : 1; /* load(1)/store(0) */
422 arminstr_t wb : 1; /* write-back "!" */
423 arminstr_t s : 1; /* restore PSR, force user bit */
424 arminstr_t u : 1; /* up/down */
425 arminstr_t p : 1; /* pre(1)/post(0) index */
426 arminstr_t tag : 3; /* 1 0 0 */
431 #define ARM_MRT_MASK 7 << 25
432 #define ARM_MRT_TAG ARM_MRT_ID << 25
434 #define ARM_DEF_MRT(regs, rn, l, w, s, u, p, cond) \
446 #define ARM_LDMIA(p, base, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, base, 1, 0, 0, 1, 0, ARMCOND_AL))
447 #define ARM_STMIA(p, base, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, base, 0, 0, 0, 1, 0, ARMCOND_AL))
449 /* stmdb sp!, {regs} */
450 #define ARM_PUSH(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL))
451 #define ARM_IASM_PUSH(regs) ARM_IASM(ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL))
453 /* ldmia sp!, {regs} */
454 #define ARM_POP(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL))
455 #define ARM_IASM_POP(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL))
457 /* ldmia sp, {regs} ; (no write-back) */
458 #define ARM_POP_NWB(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL))
459 #define ARM_IASM_POP_NWB(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL))
461 #define ARM_PUSH1(p, r1) ARM_PUSH(p, (1 << r1))
462 #define ARM_PUSH2(p, r1, r2) ARM_PUSH(p, (1 << r1) | (1 << r2))
463 #define ARM_PUSH3(p, r1, r2, r3) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3))
464 #define ARM_PUSH4(p, r1, r2, r3, r4) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4))
465 #define ARM_PUSH5(p, r1, r2, r3, r4, r5) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5))
466 #define ARM_PUSH6(p, r1, r2, r3, r4, r5, r6) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6))
467 #define ARM_PUSH7(p, r1, r2, r3, r4, r5, r6, r7) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7))
468 #define ARM_PUSH8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8))
470 #define ARM_POP8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8))
471 #define ARM_POP7(p, r1, r2, r3, r4, r5, r6, r7) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7))
472 #define ARM_POP6(p, r1, r2, r3, r4, r5, r6) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6))
473 #define ARM_POP5(p, r1, r2, r3, r4, r5) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5))
474 #define ARM_POP4(p, r1, r2, r3, r4) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4))
475 #define ARM_POP3(p, r1, r2, r3) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3))
476 #define ARM_POP2(p, r1, r2) ARM_POP(p, (1 << r1) | (1 << r2))
477 #define ARM_POP1(p, r1) ARM_POP(p, (1 << r1))
480 /* Multiply instructions */
483 arminstr_t tag2 : 4; /* 9 */
488 arminstr_t opcode : 3;
494 #define ARM_MUL_ID2 9
495 #define ARM_MUL_MASK ((0xF << 24) | (0xF << 4))
496 #define ARM_MUL_TAG ((ARM_MUL_ID << 24) | (ARM_MUL_ID2 << 4))
498 #define ARM_DEF_MUL_COND(op, rd, rm, rs, rn, s, cond) \
508 /* Rd := (Rm * Rs)[31:0]; 32 x 32 -> 32 */
509 #define ARM_MUL_COND(p, rd, rm, rs, cond) \
510 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond))
511 #define ARM_MUL(p, rd, rm, rs) \
512 ARM_MUL_COND(p, rd, rm, rs, ARMCOND_AL)
513 #define ARM_MULS_COND(p, rd, rm, rs, cond) \
514 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond))
515 #define ARM_MULS(p, rd, rm, rs) \
516 ARM_MULS_COND(p, rd, rm, rs, ARMCOND_AL)
517 #define ARM_MUL_REG_REG(p, rd, rm, rs) ARM_MUL(p, rd, rm, rs)
518 #define ARM_MULS_REG_REG(p, rd, rm, rs) ARM_MULS(p, rd, rm, rs)
521 #define ARM_IASM_MUL_COND(rd, rm, rs, cond) \
522 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond))
523 #define ARM_IASM_MUL(rd, rm, rs) \
524 ARM_IASM_MUL_COND(rd, rm, rs, ARMCOND_AL)
525 #define ARM_IASM_MULS_COND(rd, rm, rs, cond) \
526 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond))
527 #define ARM_IASM_MULS(rd, rm, rs) \
528 ARM_IASM_MULS_COND(rd, rm, rs, ARMCOND_AL)
531 /* Rd := (Rm * Rs) + Rn; 32x32+32->32 */
532 #define ARM_MLA_COND(p, rd, rm, rs, rn, cond) \
533 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond))
534 #define ARM_MLA(p, rd, rm, rs, rn) \
535 ARM_MLA_COND(p, rd, rm, rs, rn, ARMCOND_AL)
536 #define ARM_MLAS_COND(p, rd, rm, rs, rn, cond) \
537 ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond))
538 #define ARM_MLAS(p, rd, rm, rs, rn) \
539 ARM_MLAS_COND(p, rd, rm, rs, rn, ARMCOND_AL)
542 #define ARM_IASM_MLA_COND(rd, rm, rs, rn, cond) \
543 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond))
544 #define ARM_IASM_MLA(rd, rm, rs, rn) \
545 ARM_IASM_MLA_COND(rd, rm, rs, rn, ARMCOND_AL)
546 #define ARM_IASM_MLAS_COND(rd, rm, rs, rn, cond) \
547 ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond))
548 #define ARM_IASM_MLAS(rd, rm, rs, rn) \
549 ARM_IASM_MLAS_COND(rd, rm, rs, rn, ARMCOND_AL)
553 /* Word/byte transfer */
555 ARMDPI_op2_reg_imm op2_reg_imm;
557 arminstr_t op2_imm : 12;
563 arminstr_t u : 1; /* down(0) / up(1) */
564 arminstr_t p : 1; /* post-index(0) / pre-index(1) */
565 arminstr_t type : 1; /* imm(0) / register(1) */
566 arminstr_t tag : 2; /* 0 1 */
571 #define ARM_WXFER_ID 1
572 #define ARM_WXFER_MASK 3 << 26
573 #define ARM_WXFER_TAG ARM_WXFER_ID << 26
576 #define ARM_DEF_WXFER_IMM(imm12, rd, rn, ls, wb, b, p, cond) \
577 ((((int)imm12) < 0) ? -(int)(imm12) : (imm12)) | \
583 (((int)(imm12) >= 0) << 23) | \
588 #define ARM_WXFER_MAX_OFFS 0xFFF
590 /* this macro checks for imm12 bounds */
591 #define ARM_EMIT_WXFER_IMM(ptr, imm12, rd, rn, ls, wb, b, p, cond) \
593 int _imm12 = (int)(imm12) < -ARM_WXFER_MAX_OFFS \
594 ? -ARM_WXFER_MAX_OFFS \
595 : (int)(imm12) > ARM_WXFER_MAX_OFFS \
596 ? ARM_WXFER_MAX_OFFS \
599 ARM_DEF_WXFER_IMM(_imm12, (rd), (rn), (ls), (wb), (b), (p), (cond))); \
604 /* immediate offset, post-index */
605 #define ARM_LDR_IMM_POST_COND(p, rd, rn, imm, cond) \
606 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 0, 0, cond))
608 #define ARM_LDR_IMM_POST(p, rd, rn, imm) ARM_LDR_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
610 #define ARM_LDRB_IMM_POST_COND(p, rd, rn, imm, cond) \
611 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 1, 0, cond))
613 #define ARM_LDRB_IMM_POST(p, rd, rn, imm) ARM_LDRB_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
615 /* immediate offset, pre-index */
616 #define ARM_LDR_IMM_COND(p, rd, rn, imm, cond) \
617 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 0, 1, cond))
619 #define ARM_LDR_IMM(p, rd, rn, imm) ARM_LDR_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
621 #define ARM_LDRB_IMM_COND(p, rd, rn, imm, cond) \
622 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 1, 1, cond))
624 #define ARM_LDRB_IMM(p, rd, rn, imm) ARM_LDRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
627 /* immediate offset, post-index */
628 #define ARM_STR_IMM_POST_COND(p, rd, rn, imm, cond) \
629 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 0, cond))
631 #define ARM_STR_IMM_POST(p, rd, rn, imm) ARM_STR_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
633 #define ARM_STRB_IMM_POST_COND(p, rd, rn, imm, cond) \
634 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 1, 0, cond))
636 #define ARM_STRB_IMM_POST(p, rd, rn, imm) ARM_STRB_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL)
638 /* immediate offset, pre-index */
639 #define ARM_STR_IMM_COND(p, rd, rn, imm, cond) \
640 ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 0, 0, 1, cond)
641 /* ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 1, cond)) */
643 #define ARM_STR_IMM(p, rd, rn, imm) ARM_STR_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
645 #define ARM_STRB_IMM_COND(p, rd, rn, imm, cond) \
646 ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 1, 1, cond))
648 #define ARM_STRB_IMM(p, rd, rn, imm) ARM_STRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
651 #define ARM_STR_IMM_WB_COND(p, rd, rn, imm, cond) \
652 ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 1, 0, 1, cond)
653 #define ARM_STR_IMM_WB(p, rd, rn, imm) ARM_STR_IMM_WB_COND(p, rd, rn, imm, ARMCOND_AL)
656 #define ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, u, p, cond) \
658 ((shift_type) << 5) | \
671 #define ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
672 ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_UP, p, cond)
673 #define ARM_DEF_WXFER_REG_MINUS_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
674 ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_DOWN, p, cond)
677 #define ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
678 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 0, 1, cond))
679 #define ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
680 ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
681 #define ARM_LDR_REG_REG(p, rd, rn, rm) \
682 ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
684 #define ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
685 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 1, 1, cond))
686 #define ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
687 ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
688 #define ARM_LDRB_REG_REG(p, rd, rn, rm) \
689 ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
691 #define ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
692 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 0, 1, cond))
693 #define ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
694 ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
695 #define ARM_STR_REG_REG(p, rd, rn, rm) \
696 ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
699 #define ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
700 ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 1, 1, cond))
701 #define ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
702 ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
703 #define ARM_STRB_REG_REG(p, rd, rn, rm) \
704 ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
708 /* Half-word or byte (signed) transfer. */
710 arminstr_t rm : 4; /* imm_lo */
711 arminstr_t tag3 : 1; /* 1 */
712 arminstr_t h : 1; /* half-word or byte */
713 arminstr_t s : 1; /* sign-extend or zero-extend */
714 arminstr_t tag2 : 1; /* 1 */
715 arminstr_t imm_hi : 4;
720 arminstr_t type : 1; /* imm(1) / reg(0) */
721 arminstr_t u : 1; /* +- */
722 arminstr_t p : 1; /* pre/post-index */
727 #define ARM_HXFER_ID 0
728 #define ARM_HXFER_ID2 1
729 #define ARM_HXFER_ID3 1
730 #define ARM_HXFER_MASK ((0x7 << 25) | (0x9 << 4))
731 #define ARM_HXFER_TAG ((ARM_HXFER_ID << 25) | (ARM_HXFER_ID2 << 7) | (ARM_HXFER_ID3 << 4))
733 #define ARM_DEF_HXFER_IMM_COND(imm, h, s, rd, rn, ls, wb, p, cond) \
737 (((imm) << 4) & (0xF << 8)) | \
743 (((int)(imm) >= 0) << 23) | \
748 #define ARM_LDRH_IMM_COND(p, rd, rn, imm, cond) \
749 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond))
750 #define ARM_LDRH_IMM(p, rd, rn, imm) \
751 ARM_LDRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
752 #define ARM_LDRSH_IMM_COND(p, rd, rn, imm, cond) \
753 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
754 #define ARM_LDRSH_IMM(p, rd, rn, imm) \
755 ARM_LDRSH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
756 #define ARM_LDRSB_IMM_COND(p, rd, rn, imm, cond) \
757 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
758 #define ARM_LDRSB_IMM(p, rd, rn, imm) \
759 ARM_LDRSB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
762 #define ARM_STRH_IMM_COND(p, rd, rn, imm, cond) \
763 ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond))
764 #define ARM_STRH_IMM(p, rd, rn, imm) \
765 ARM_STRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
768 #define ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, u, p, cond) \
782 #define ARM_DEF_HXFER_REG_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \
783 ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_UP, p, cond)
784 #define ARM_DEF_HXFER_REG_MINUS_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \
785 ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_DOWN, p, cond)
787 #define ARM_LDRH_REG_REG_COND(p, rm, rd, rn, cond) \
788 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond))
789 #define ARM_LDRH_REG_REG(p, rm, rd, rn) \
790 ARM_LDRH_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
791 #define ARM_LDRSH_REG_REG_COND(p, rm, rd, rn, cond) \
792 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
793 #define ARM_LDRSH_REG_REG(p, rm, rd, rn) \
794 ARM_LDRSH_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
795 #define ARM_LDRSB_REG_REG_COND(p, rm, rd, rn, cond) \
796 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
797 #define ARM_LDRSB_REG_REG(p, rm, rd, rn) ARM_LDRSB_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
799 #define ARM_STRH_REG_REG_COND(p, rm, rd, rn, cond) \
800 ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond))
801 #define ARM_STRH_REG_REG(p, rm, rd, rn) \
802 ARM_STRH_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
809 arminstr_t tag3 : 8; /* 0x9 */
814 arminstr_t tag : 5; /* 0x2 */
819 #define ARM_SWP_ID2 9
820 #define ARM_SWP_MASK ((0x1F << 23) | (3 << 20) | (0xFF << 4))
821 #define ARM_SWP_TAG ((ARM_SWP_ID << 23) | (ARM_SWP_ID2 << 4))
825 /* Software interrupt */
832 #define ARM_SWI_ID 0xF
833 #define ARM_SWI_MASK (0xF << 24)
834 #define ARM_SWI_TAG (ARM_SWI_ID << 24)
838 /* Co-processor Data Processing */
841 arminstr_t tag2 : 1; /* 0 */
843 arminstr_t cpn : 4; /* CP number */
847 arminstr_t tag : 4; /* 0xE */
851 #define ARM_CDP_ID 0xE
852 #define ARM_CDP_ID2 0
853 #define ARM_CDP_MASK ((0xF << 24) | (1 << 4))
854 #define ARM_CDP_TAG ((ARM_CDP_ID << 24) | (ARM_CDP_ID2 << 4))
857 /* Co-processor Data Transfer (ldc/stc) */
873 #define ARM_CDT_MASK (7 << 25)
874 #define ARM_CDT_TAG (ARM_CDT_ID << 25)
877 /* Co-processor Register Transfer (mcr/mrc) */
891 #define ARM_CRT_ID 0xE
892 #define ARM_CRT_ID2 0x1
893 #define ARM_CRT_MASK ((0xF << 24) | (1 << 4))
894 #define ARM_CRT_TAG ((ARM_CRT_ID << 24) | (ARM_CRT_ID2 << 4))
896 /* Move register to PSR. */
898 ARMDPI_op2_imm op2_imm;
901 arminstr_t pad : 8; /* 0 */
902 arminstr_t tag4 : 4; /* 0xF */
904 arminstr_t tag3 : 2; /* 0x2 */
906 arminstr_t tag2 : 2; /* 0x2 */
908 arminstr_t tag : 2; /* 0 */
914 #define ARM_MSR_ID2 2
915 #define ARM_MSR_ID3 2
916 #define ARM_MSR_ID4 0xF
917 #define ARM_MSR_MASK ((3 << 26) | \
921 #define ARM_MSR_TAG ((ARM_MSR_ID << 26) | \
922 (ARM_MSR_ID2 << 23) | \
923 (ARM_MSR_ID3 << 20) | \
927 /* Move PSR to register. */
929 arminstr_t tag3 : 12;
932 arminstr_t sel : 1; /* CPSR | SPSR */
938 #define ARM_MRS_ID2 0xF
939 #define ARM_MRS_ID3 0
940 #define ARM_MRS_MASK ((0x1F << 23) | (0x3F << 16) | 0xFFF)
941 #define ARM_MRS_TAG ((ARM_MRS_ID << 23) | (ARM_MRS_ID2 << 16) | ARM_MRS_ID3)
946 #include "arm_dpimacros.h"
948 #define ARM_NOP(p) ARM_MOV_REG_REG(p, ARMREG_R0, ARMREG_R0)
951 #define ARM_SHL_IMM_COND(p, rd, rm, imm, cond) \
952 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond)
953 #define ARM_SHL_IMM(p, rd, rm, imm) \
954 ARM_SHL_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
955 #define ARM_SHLS_IMM_COND(p, rd, rm, imm, cond) \
956 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond)
957 #define ARM_SHLS_IMM(p, rd, rm, imm) \
958 ARM_SHLS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
960 #define ARM_SHR_IMM_COND(p, rd, rm, imm, cond) \
961 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond)
962 #define ARM_SHR_IMM(p, rd, rm, imm) \
963 ARM_SHR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
964 #define ARM_SHRS_IMM_COND(p, rd, rm, imm, cond) \
965 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond)
966 #define ARM_SHRS_IMM(p, rd, rm, imm) \
967 ARM_SHRS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
969 #define ARM_SAR_IMM_COND(p, rd, rm, imm, cond) \
970 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond)
971 #define ARM_SAR_IMM(p, rd, rm, imm) \
972 ARM_SAR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
973 #define ARM_SARS_IMM_COND(p, rd, rm, imm, cond) \
974 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond)
975 #define ARM_SARS_IMM(p, rd, rm, imm) \
976 ARM_SARS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
978 #define ARM_ROR_IMM_COND(p, rd, rm, imm, cond) \
979 ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond)
980 #define ARM_ROR_IMM(p, rd, rm, imm) \
981 ARM_ROR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
982 #define ARM_RORS_IMM_COND(p, rd, rm, imm, cond) \
983 ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond)
984 #define ARM_RORS_IMM(p, rd, rm, imm) \
985 ARM_RORS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
987 #define ARM_SHL_REG_COND(p, rd, rm, rs, cond) \
988 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond)
989 #define ARM_SHL_REG(p, rd, rm, rs) \
990 ARM_SHL_REG_COND(p, rd, rm, rs, ARMCOND_AL)
991 #define ARM_SHLS_REG_COND(p, rd, rm, rs, cond) \
992 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond)
993 #define ARM_SHLS_REG(p, rd, rm, rs) \
994 ARM_SHLS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
995 #define ARM_SHLS_REG_REG(p, rd, rm, rs) ARM_SHLS_REG(p, rd, rm, rs)
997 #define ARM_SHR_REG_COND(p, rd, rm, rs, cond) \
998 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond)
999 #define ARM_SHR_REG(p, rd, rm, rs) \
1000 ARM_SHR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1001 #define ARM_SHRS_REG_COND(p, rd, rm, rs, cond) \
1002 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond)
1003 #define ARM_SHRS_REG(p, rd, rm, rs) \
1004 ARM_SHRS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1005 #define ARM_SHRS_REG_REG(p, rd, rm, rs) ARM_SHRS_REG(p, rd, rm, rs)
1007 #define ARM_SAR_REG_COND(p, rd, rm, rs, cond) \
1008 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond)
1009 #define ARM_SAR_REG(p, rd, rm, rs) \
1010 ARM_SAR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1011 #define ARM_SARS_REG_COND(p, rd, rm, rs, cond) \
1012 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond)
1013 #define ARM_SARS_REG(p, rd, rm, rs) \
1014 ARM_SARS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1015 #define ARM_SARS_REG_REG(p, rd, rm, rs) ARM_SARS_REG(p, rd, rm, rs)
1017 #define ARM_ROR_REG_COND(p, rd, rm, rs, cond) \
1018 ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond)
1019 #define ARM_ROR_REG(p, rd, rm, rs) \
1020 ARM_ROR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1021 #define ARM_RORS_REG_COND(p, rd, rm, rs, cond) \
1022 ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond)
1023 #define ARM_RORS_REG(p, rd, rm, rs) \
1024 ARM_RORS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
1025 #define ARM_RORS_REG_REG(p, rd, rm, rs) ARM_RORS_REG(p, rd, rm, rs)
1027 #define ARM_DBRK(p) ARM_EMIT(p, 0xE6000010)
1028 #define ARM_IASM_DBRK() ARM_IASM_EMIT(0xE6000010)
1030 #define ARM_INC(p, reg) ARM_ADD_REG_IMM8(p, reg, reg, 1)
1031 #define ARM_DEC(p, reg) ARM_SUB_REG_IMM8(p, reg, reg, 1)
1036 /* Count leading zeros, CLZ{cond} Rd, Rm */
1039 arminstr_t tag2 : 8;
1041 arminstr_t tag : 12;
1042 arminstr_t cond : 4;
1045 #define ARM_CLZ_ID 0x16F
1046 #define ARM_CLZ_ID2 0xF1
1047 #define ARM_CLZ_MASK ((0xFFF << 16) | (0xFF < 4))
1048 #define ARM_CLZ_TAG ((ARM_CLZ_ID << 16) | (ARM_CLZ_ID2 << 4))
1058 ARMInstrWXfer wxfer;
1059 ARMInstrHXfer hxfer;
1069 ARMInstrGeneric generic;