2 * Copyright 1988, 1989 Hans-J. Boehm, Alan J. Demers
3 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
4 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
5 * Copyright (c) 1999 by Hewlett-Packard Company. All rights reserved.
8 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
9 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
11 * Permission is hereby granted to use or copy this program
12 * for any purpose, provided the above notices are retained on all copies.
13 * Permission to modify the code and to distribute modified code is granted,
14 * provided the above notices are retained, and a notice that the code was
15 * modified is included with the above copyright notice.
22 * Mutual exclusion between allocator/collector routines.
23 * Needed if there is more than one allocator thread.
24 * FASTLOCK() is assumed to try to acquire the lock in a cheap and
25 * dirty way that is acceptable for a few instructions, e.g. by
26 * inhibiting preemption. This is assumed to have succeeded only
27 * if a subsequent call to FASTLOCK_SUCCEEDED() returns TRUE.
28 * FASTUNLOCK() is called whether or not FASTLOCK_SUCCEEDED().
29 * If signals cannot be tolerated with the FASTLOCK held, then
30 * FASTLOCK should disable signals. The code executed under
31 * FASTLOCK is otherwise immune to interruption, provided it is
33 * DCL_LOCK_STATE declares any local variables needed by LOCK and UNLOCK
34 * and/or DISABLE_SIGNALS and ENABLE_SIGNALS and/or FASTLOCK.
35 * (There is currently no equivalent for FASTLOCK.)
37 * In the PARALLEL_MARK case, we also need to define a number of
38 * other inline finctions here:
39 * GC_bool GC_compare_and_exchange( volatile GC_word *addr,
40 * GC_word old, GC_word new )
41 * GC_word GC_atomic_add( volatile GC_word *addr, GC_word how_much )
42 * void GC_memory_barrier( )
46 void GC_noop1 GC_PROTO((word));
47 # ifdef PCR_OBSOLETE /* Faster, but broken with multiple lwp's */
48 # include "th/PCR_Th.h"
49 # include "th/PCR_ThCrSec.h"
50 extern struct PCR_Th_MLRep GC_allocate_ml;
51 # define DCL_LOCK_STATE PCR_sigset_t GC_old_sig_mask
52 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
53 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
54 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
55 # define FASTLOCK() PCR_ThCrSec_EnterSys()
56 /* Here we cheat (a lot): */
57 # define FASTLOCK_SUCCEEDED() (*(int *)(&GC_allocate_ml) == 0)
58 /* TRUE if nobody currently holds the lock */
59 # define FASTUNLOCK() PCR_ThCrSec_ExitSys()
62 # include <base/PCR_Base.h>
63 # include <th/PCR_Th.h>
64 extern PCR_Th_ML GC_allocate_ml;
65 # define DCL_LOCK_STATE \
66 PCR_ERes GC_fastLockRes; PCR_sigset_t GC_old_sig_mask
67 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
68 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
69 # define FASTLOCK() (GC_fastLockRes = PCR_Th_ML_Try(&GC_allocate_ml))
70 # define FASTLOCK_SUCCEEDED() (GC_fastLockRes == PCR_ERes_okay)
71 # define FASTUNLOCK() {\
72 if( FASTLOCK_SUCCEEDED() ) PCR_Th_ML_Release(&GC_allocate_ml); }
75 extern GC_word RT0u__inCritical;
76 # define LOCK() RT0u__inCritical++
77 # define UNLOCK() RT0u__inCritical--
81 extern pthread_mutex_t GC_allocate_ml;
82 # define LOCK() pthread_mutex_lock(&GC_allocate_ml)
83 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
85 # ifdef GC_SOLARIS_THREADS
88 extern mutex_t GC_allocate_ml;
89 # define LOCK() mutex_lock(&GC_allocate_ml);
90 # define UNLOCK() mutex_unlock(&GC_allocate_ml);
93 /* Try to define GC_TEST_AND_SET and a matching GC_CLEAR for spin lock */
94 /* acquisition and release. We need this for correct operation of the */
98 inline static int GC_test_and_set(volatile unsigned int *addr) {
100 /* Note: the "xchg" instruction does not need a "lock" prefix */
101 __asm__ __volatile__("xchgl %0, %1"
102 : "=r"(oldval), "=m"(*(addr))
103 : "0"(1), "m"(*(addr)) : "memory");
106 # define GC_TEST_AND_SET_DEFINED
109 # if defined(__INTEL_COMPILER)
110 # include <ia64intrin.h>
112 inline static int GC_test_and_set(volatile unsigned int *addr) {
114 # ifndef __INTEL_COMPILER
115 __asm__ __volatile__("xchg4 %0=%1,%2"
116 : "=r"(oldval), "=m"(*addr)
117 : "r"(n) : "memory");
119 oldval = _InterlockedExchange(addr, n);
123 # define GC_TEST_AND_SET_DEFINED
124 /* Should this handle post-increment addressing?? */
125 inline static void GC_clear(volatile unsigned int *addr) {
126 # ifndef __INTEL_COMPILER
127 __asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory");
129 // there is no st4 but I can use xchg I hope
130 _InterlockedExchange(addr, 0);
133 # define GC_CLEAR_DEFINED
136 inline static int GC_test_and_set(volatile unsigned int *addr) {
139 __asm__ __volatile__("ldstub %1,%0"
140 : "=r"(oldval), "=m"(*addr)
141 : "m"(*addr) : "memory");
144 # define GC_TEST_AND_SET_DEFINED
147 /* Contributed by Tony Mantler. I'm not sure how well it was */
149 inline static int GC_test_and_set(volatile unsigned int *addr) {
150 char oldval; /* this must be no longer than 8 bits */
152 /* The return value is semi-phony. */
153 /* 'tas' sets bit 7 while the return */
154 /* value pretends bit 0 was set */
155 __asm__ __volatile__(
156 "tas %1@; sne %0; negb %0"
158 : "a" (addr) : "memory");
161 # define GC_TEST_AND_SET_DEFINED
163 # if defined(POWERPC)
164 inline static int GC_test_and_set(volatile unsigned int *addr) {
166 int temp = 1; /* locked value */
168 __asm__ __volatile__(
169 "1:\tlwarx %0,0,%1\n" /* load and reserve */
170 "\tcmpwi %0, 0\n" /* if load is */
171 "\tbne 2f\n" /* non-zero, return already set */
172 "\tstwcx. %2,0,%1\n" /* else store conditional */
173 "\tbne- 1b\n" /* retry if lost reservation */
174 "\tsync\n" /* import barrier */
175 "2:\t\n" /* oldval is zero if we set */
177 : "r"(addr), "r"(temp)
181 # define GC_TEST_AND_SET_DEFINED
182 inline static void GC_clear(volatile unsigned int *addr) {
183 __asm__ __volatile__("lwsync" : : : "memory");
186 # define GC_CLEAR_DEFINED
189 inline static int GC_test_and_set(volatile unsigned int * addr)
191 unsigned long oldvalue;
194 __asm__ __volatile__(
208 ".section .text2,\"ax\"\n"
212 :"=&r" (temp), "=m" (*addr), "=&r" (oldvalue)
213 :"Ir" (1), "m" (*addr)
218 # define GC_TEST_AND_SET_DEFINED
219 inline static void GC_clear(volatile unsigned int *addr) {
220 __asm__ __volatile__("mb" : : : "memory");
223 # define GC_CLEAR_DEFINED
226 #ifdef __native_client__
227 #define NACL_ALIGN() ".align 4\n"
228 #define MASK_REGISTER(reg) "bic " reg ", " reg ", #0xc0000000\n"
231 #define MASK_REGISTER(reg)
233 inline static int GC_test_and_set(volatile unsigned int *addr) {
234 #if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__)
236 __asm__ __volatile__ (
242 "strex %1, %2, [%3]\n"
245 : "=&r" (ret), "=&r" (tmp)
246 : "r" (1), "r" (addr)
251 /* SWP on ARM is very similar to XCHG on x86. Doesn't lock the
252 * bus because there are no SMP ARM machines. If/when there are,
253 * this code will likely need to be updated. */
254 /* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
255 __asm__ __volatile__(MASK_REGISTER("%2")
263 # define GC_TEST_AND_SET_DEFINED
264 inline static void GC_clear(volatile unsigned int *addr) {
267 __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
271 # define GC_CLEAR_DEFINED
274 inline static int GC_test_and_set(volatile unsigned int *addr) {
275 /* Ripped from linuxthreads/sysdeps/cris/pt-machine.h. */
276 /* Included with Hans-Peter Nilsson's permission. */
277 register unsigned long int ret;
279 /* Note the use of a dummy output of *addr to expose the write.
280 * The memory barrier is to stop *other* writes being moved past
283 __asm__ __volatile__("clearf\n"
290 : "=&r" (ret), "=m" (*addr)
291 : "r" (addr), "r" ((int) 1), "m" (*addr)
295 # define GC_TEST_AND_SET_DEFINED
298 inline static int GC_test_and_set(volatile unsigned int *addr) {
300 __asm__ __volatile__ (
302 "0: cs %0,%1,0(%2)\n"
305 : "d" (1), "a" (addr)
310 # endif /* __GNUC__ */
311 # if (defined(ALPHA) && !defined(__GNUC__))
313 --> We currently assume that if gcc is not used, we are
314 --> running under Tru64.
316 # include <machine/builtins.h>
318 # define GC_test_and_set(addr) __ATOMIC_EXCH_LONG(addr, 1)
319 # define GC_TEST_AND_SET_DEFINED
320 # define GC_clear(addr) { asm("mb"); *(volatile unsigned *)addr = 0; }
321 # define GC_CLEAR_DEFINED
323 # if defined(MSWIN32)
324 # define GC_test_and_set(addr) InterlockedExchange((LPLONG)addr,1)
325 # define GC_TEST_AND_SET_DEFINED
329 # include <sys/tas.h>
330 # define GC_test_and_set(addr) _test_and_set((int *) addr,1)
331 # define GC_TEST_AND_SET_DEFINED
332 # elif __mips < 3 || !(defined (_ABIN32) || defined(_ABI64)) \
333 || !defined(_COMPILER_VERSION) || _COMPILER_VERSION < 700
335 # define GC_test_and_set(addr) _test_and_set((void *)addr,1)
337 # define GC_test_and_set(addr) test_and_set((void *)addr,1)
340 # include <sgidefs.h>
342 # define GC_test_and_set(addr) __test_and_set32((void *)addr,1)
343 # define GC_clear(addr) __lock_release(addr);
344 # define GC_CLEAR_DEFINED
346 # define GC_TEST_AND_SET_DEFINED
349 # include <sys/atomic_op.h>
350 # if (defined(_POWER) || defined(_POWERPC))
351 # if defined(__GNUC__)
352 inline static void GC_memsync() {
353 __asm__ __volatile__ ("sync" : : : "memory");
357 # define inline __inline
359 # pragma mc_func GC_memsync { \
360 "7c0004ac" /* sync (same opcode used for dcs)*/ \
364 # error dont know how to memsync
366 inline static int GC_test_and_set(volatile unsigned int * addr) {
368 if (compare_and_swap((void *)addr, &oldvalue, 1)) {
373 # define GC_TEST_AND_SET_DEFINED
374 inline static void GC_clear(volatile unsigned int *addr) {
378 # define GC_CLEAR_DEFINED
381 # if 0 /* defined(HP_PA) */
382 /* The official recommendation seems to be to not use ldcw from */
383 /* user mode. Since multithreaded incremental collection doesn't */
384 /* work anyway on HP_PA, this shouldn't be a major loss. */
386 /* "set" means 0 and "clear" means 1 here. */
387 # define GC_test_and_set(addr) !GC_test_and_clear(addr);
388 # define GC_TEST_AND_SET_DEFINED
389 # define GC_clear(addr) GC_noop1((word)(addr)); *(volatile unsigned int *)addr = 1;
390 /* The above needs a memory barrier! */
391 # define GC_CLEAR_DEFINED
393 # if defined(GC_TEST_AND_SET_DEFINED) && !defined(GC_CLEAR_DEFINED)
395 inline static void GC_clear(volatile unsigned int *addr) {
396 /* Try to discourage gcc from moving anything past this. */
397 __asm__ __volatile__(" " : : : "memory");
401 /* The function call in the following should prevent the */
402 /* compiler from moving assignments to below the UNLOCK. */
403 # define GC_clear(addr) GC_noop1((word)(addr)); \
404 *((volatile unsigned int *)(addr)) = 0;
406 # define GC_CLEAR_DEFINED
407 # endif /* !GC_CLEAR_DEFINED */
409 # if !defined(GC_TEST_AND_SET_DEFINED)
410 # define USE_PTHREAD_LOCKS
413 # if defined(GC_PTHREADS) && !defined(GC_SOLARIS_THREADS) \
414 && !defined(GC_WIN32_THREADS)
415 # define NO_THREAD (pthread_t)(-1)
416 # include <pthread.h>
417 # if defined(PARALLEL_MARK)
418 /* We need compare-and-swap to update mark bits, where it's */
419 /* performance critical. If USE_MARK_BYTES is defined, it is */
420 /* no longer needed for this purpose. However we use it in */
421 /* either case to implement atomic fetch-and-add, though that's */
422 /* less performance critical, and could perhaps be done with */
424 # if defined(GENERIC_COMPARE_AND_SWAP)
425 /* Probably not useful, except for debugging. */
426 /* We do use GENERIC_COMPARE_AND_SWAP on PA_RISC, but we */
427 /* minimize its use. */
428 extern pthread_mutex_t GC_compare_and_swap_lock;
430 /* Note that if GC_word updates are not atomic, a concurrent */
431 /* reader should acquire GC_compare_and_swap_lock. On */
432 /* currently supported platforms, such updates are atomic. */
433 extern GC_bool GC_compare_and_exchange(volatile GC_word *addr,
434 GC_word old, GC_word new_val);
435 # endif /* GENERIC_COMPARE_AND_SWAP */
437 # if !defined(GENERIC_COMPARE_AND_SWAP)
438 /* Returns TRUE if the comparison succeeded. */
439 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
444 __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
445 : "+m"(*(addr)), "=q"(result)
446 : "r" (new_val), "a"(old) : "memory");
447 return (GC_bool) result;
449 # endif /* !GENERIC_COMPARE_AND_SWAP */
450 inline static void GC_memory_barrier()
452 /* We believe the processor ensures at least processor */
453 /* consistent ordering. Thus a compiler barrier */
454 /* should suffice. */
455 __asm__ __volatile__("" : : : "memory");
460 # if !defined(GENERIC_COMPARE_AND_SWAP)
461 /* Returns TRUE if the comparison succeeded. */
462 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
467 __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
468 : "+m"(*(addr)), "=r"(result)
469 : "r" (new_val), "a"(old) : "memory");
470 return (GC_bool) result;
472 # endif /* !GENERIC_COMPARE_AND_SWAP */
473 inline static void GC_memory_barrier()
475 /* We believe the processor ensures at least processor */
476 /* consistent ordering. Thus a compiler barrier */
477 /* should suffice. */
478 __asm__ __volatile__("" : : : "memory");
482 # if defined(POWERPC)
483 # if !defined(GENERIC_COMPARE_AND_SWAP)
484 # if CPP_WORDSZ == 64
485 /* Returns TRUE if the comparison succeeded. */
486 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
487 GC_word old, GC_word new_val)
489 # if HAS___SYNC_BOOL_COMPARE_AND_SWAP
490 return __sync_bool_compare_and_swap(addr, old, new_val);
492 unsigned long result, dummy;
493 __asm__ __volatile__(
494 "1:\tldarx %0,0,%5\n"
504 : "=&r" (dummy), "=r" (result), "=p" (addr)
505 : "r" (new_val), "r" (old), "2"(addr)
507 return (GC_bool) result;
511 /* Returns TRUE if the comparison succeeded. */
512 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
513 GC_word old, GC_word new_val)
515 # if HAS___SYNC_BOOL_COMPARE_AND_SWAP
516 return __sync_bool_compare_and_swap(addr, old, new_val);
519 __asm__ __volatile__(
520 "1:\tlwarx %0,0,%5\n"
530 : "=&r" (dummy), "=r" (result), "=p" (addr)
531 : "r" (new_val), "r" (old), "2"(addr)
533 return (GC_bool) result;
537 # endif /* !GENERIC_COMPARE_AND_SWAP */
538 inline static void GC_memory_barrier()
540 __asm__ __volatile__("sync" : : : "memory");
542 # endif /* POWERPC */
545 # if !defined(GENERIC_COMPARE_AND_SWAP)
546 # if CPP_WORDSZ == 64
547 /* Returns TRUE if the comparison succeeded. */
548 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
549 GC_word old, GC_word new_val)
551 unsigned long result;
552 __asm__ __volatile__(
555 : "0" (new_val), "r" (addr), "r" (old)
557 return (GC_bool) (result == old);
560 /* Returns TRUE if the comparison succeeded. */
561 inline static GC_bool GC_compare_and_exchange(volatile GC_word *_addr,
562 GC_word _old, GC_word _new_val)
564 register unsigned long result asm("o0");
565 register unsigned long old asm("o1");
566 register volatile GC_word *addr asm("o2");
570 __asm__ __volatile__(
571 /* We encode the instruction directly so that it
572 doesn't taint the whole binary as v9-only. */
573 ".word 0xd1e29009" /* cas [%o2], %o1, %o0 */
575 : "0" (result), "r" (addr), "r"(old)
577 return (GC_bool) (result == old);
580 # endif /* !GENERIC_COMPARE_AND_SWAP */
581 inline static void GC_memory_barrier()
583 /* All sparc v9 chips provice procesor consistent ordering. */
584 /* Thus a compiler barrier should suffice. */
585 __asm__ __volatile__("" : : : "memory");
590 # if !defined(GENERIC_COMPARE_AND_SWAP)
591 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
592 GC_word old, GC_word new_val)
594 unsigned long oldval;
595 # if CPP_WORDSZ == 32
596 __asm__ __volatile__(
598 "mov ar.ccv=%3 ;; cmpxchg4.rel %0=[%0],%2,ar.ccv"
600 : "r"(addr), "r"(new_val), "r"(old) : "memory");
602 __asm__ __volatile__(
603 "mov ar.ccv=%3 ;; cmpxchg8.rel %0=[%1],%2,ar.ccv"
605 : "r"(addr), "r"(new_val), "r"(old) : "memory");
607 return (oldval == old);
609 # endif /* !GENERIC_COMPARE_AND_SWAP */
611 /* Shouldn't be needed; we use volatile stores instead. */
612 inline static void GC_memory_barrier()
614 __asm__ __volatile__("mf" : : : "memory");
619 # if !defined(GENERIC_COMPARE_AND_SWAP)
620 # if defined(__GNUC__)
621 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
622 GC_word old, GC_word new_val)
624 unsigned long was_equal;
627 __asm__ __volatile__(
636 :"=&r" (temp), "=m" (*addr), "=&r" (was_equal)
637 : "r" (new_val), "Ir" (old)
641 # else /* !__GNUC__ */
642 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
643 GC_word old, GC_word new_val)
645 return __CMP_STORE_QUAD(addr, old, new_val, addr);
647 # endif /* !__GNUC__ */
648 # endif /* !GENERIC_COMPARE_AND_SWAP */
650 inline static void GC_memory_barrier()
652 __asm__ __volatile__("mb" : : : "memory");
655 # define GC_memory_barrier() asm("mb")
656 # endif /* !__GNUC__ */
659 # if !defined(GENERIC_COMPARE_AND_SWAP)
660 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
661 GC_word old, GC_word new_val)
664 __asm__ __volatile__ (
672 : "=&d" (retval), "+d" (old)
673 : "d" (new_val), "a" (addr)
678 # define GC_memory_barrier()
680 # if !defined(GENERIC_COMPARE_AND_SWAP)
681 /* Returns the original value of *addr. */
682 inline static GC_word GC_atomic_add(volatile GC_word *addr,
688 } while (!GC_compare_and_exchange(addr, old, old+how_much));
691 # else /* GENERIC_COMPARE_AND_SWAP */
692 /* So long as a GC_word can be atomically updated, it should */
693 /* be OK to read *addr without a lock. */
694 extern GC_word GC_atomic_add(volatile GC_word *addr, GC_word how_much);
695 # endif /* GENERIC_COMPARE_AND_SWAP */
697 # endif /* PARALLEL_MARK */
699 # if !defined(THREAD_LOCAL_ALLOC) && !defined(USE_PTHREAD_LOCKS)
700 /* In the THREAD_LOCAL_ALLOC case, the allocation lock tends to */
701 /* be held for long periods, if it is held at all. Thus spinning */
702 /* and sleeping for fixed periods are likely to result in */
703 /* significant wasted time. We thus rely mostly on queued locks. */
704 # define USE_SPIN_LOCK
705 extern volatile unsigned int GC_allocate_lock;
706 extern void GC_lock(void);
707 /* Allocation lock holder. Only set if acquired by client through */
708 /* GC_call_with_alloc_lock. */
709 # ifdef GC_ASSERTIONS
711 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); \
714 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
715 GC_clear(&GC_allocate_lock); }
718 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
720 GC_clear(&GC_allocate_lock)
721 # endif /* !GC_ASSERTIONS */
723 /* Another alternative for OSF1 might be: */
724 # include <sys/mman.h>
725 extern msemaphore GC_allocate_semaphore;
726 # define LOCK() { if (msem_lock(&GC_allocate_semaphore, MSEM_IF_NOWAIT) \
727 != 0) GC_lock(); else GC_allocate_lock = 1; }
728 /* The following is INCORRECT, since the memory model is too weak. */
729 /* Is this true? Presumably msem_unlock has the right semantics? */
731 # define UNLOCK() { GC_allocate_lock = 0; \
732 msem_unlock(&GC_allocate_semaphore, 0); }
734 # else /* THREAD_LOCAL_ALLOC || USE_PTHREAD_LOCKS */
735 # ifndef USE_PTHREAD_LOCKS
736 # define USE_PTHREAD_LOCKS
738 # endif /* THREAD_LOCAL_ALLOC */
739 # ifdef USE_PTHREAD_LOCKS
740 # include <pthread.h>
741 extern pthread_mutex_t GC_allocate_ml;
742 # ifdef GC_ASSERTIONS
747 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
748 pthread_mutex_unlock(&GC_allocate_ml); }
749 # else /* !GC_ASSERTIONS */
750 # if defined(NO_PTHREAD_TRYLOCK)
751 # define LOCK() GC_lock();
752 # else /* !defined(NO_PTHREAD_TRYLOCK) */
754 { if (0 != pthread_mutex_trylock(&GC_allocate_ml)) GC_lock(); }
756 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
757 # endif /* !GC_ASSERTIONS */
758 # endif /* USE_PTHREAD_LOCKS */
759 # define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
760 # define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
761 # define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
762 extern VOLATILE GC_bool GC_collecting;
763 # define ENTER_GC() GC_collecting = 1;
764 # define EXIT_GC() GC_collecting = 0;
765 extern void GC_lock(void);
766 extern pthread_t GC_lock_holder;
767 # ifdef GC_ASSERTIONS
768 extern pthread_t GC_mark_lock_holder;
770 # endif /* GC_PTHREADS with linux_threads.c implementation */
771 # if defined(GC_WIN32_THREADS)
772 # if defined(GC_PTHREADS)
773 # include <pthread.h>
774 extern pthread_mutex_t GC_allocate_ml;
775 # define LOCK() pthread_mutex_lock(&GC_allocate_ml)
776 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
778 # include <windows.h>
779 GC_API CRITICAL_SECTION GC_allocate_ml;
780 # define LOCK() EnterCriticalSection(&GC_allocate_ml);
781 # define UNLOCK() LeaveCriticalSection(&GC_allocate_ml);
784 # ifndef SET_LOCK_HOLDER
785 # define SET_LOCK_HOLDER()
786 # define UNSET_LOCK_HOLDER()
787 # define I_HOLD_LOCK() FALSE
788 /* Used on platforms were locks can be reacquired, */
789 /* so it doesn't matter if we lie. */
791 # else /* !THREADS */
794 # endif /* !THREADS */
795 # ifndef SET_LOCK_HOLDER
796 # define SET_LOCK_HOLDER()
797 # define UNSET_LOCK_HOLDER()
798 # define I_HOLD_LOCK() FALSE
799 /* Used on platforms were locks can be reacquired, */
800 /* so it doesn't matter if we lie. */
807 # ifndef DCL_LOCK_STATE
808 # define DCL_LOCK_STATE
811 # define FASTLOCK() LOCK()
812 # define FASTLOCK_SUCCEEDED() TRUE
813 # define FASTUNLOCK() UNLOCK()
816 #endif /* GC_LOCKS_H */