2 * Copyright 1988, 1989 Hans-J. Boehm, Alan J. Demers
3 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
4 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
5 * Copyright (c) 1999 by Hewlett-Packard Company. All rights reserved.
8 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
9 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
11 * Permission is hereby granted to use or copy this program
12 * for any purpose, provided the above notices are retained on all copies.
13 * Permission to modify the code and to distribute modified code is granted,
14 * provided the above notices are retained, and a notice that the code was
15 * modified is included with the above copyright notice.
22 * Mutual exclusion between allocator/collector routines.
23 * Needed if there is more than one allocator thread.
24 * FASTLOCK() is assumed to try to acquire the lock in a cheap and
25 * dirty way that is acceptable for a few instructions, e.g. by
26 * inhibiting preemption. This is assumed to have succeeded only
27 * if a subsequent call to FASTLOCK_SUCCEEDED() returns TRUE.
28 * FASTUNLOCK() is called whether or not FASTLOCK_SUCCEEDED().
29 * If signals cannot be tolerated with the FASTLOCK held, then
30 * FASTLOCK should disable signals. The code executed under
31 * FASTLOCK is otherwise immune to interruption, provided it is
33 * DCL_LOCK_STATE declares any local variables needed by LOCK and UNLOCK
34 * and/or DISABLE_SIGNALS and ENABLE_SIGNALS and/or FASTLOCK.
35 * (There is currently no equivalent for FASTLOCK.)
37 * In the PARALLEL_MARK case, we also need to define a number of
38 * other inline finctions here:
39 * GC_bool GC_compare_and_exchange( volatile GC_word *addr,
40 * GC_word old, GC_word new )
41 * GC_word GC_atomic_add( volatile GC_word *addr, GC_word how_much )
42 * void GC_memory_barrier( )
46 void GC_noop1 GC_PROTO((word));
47 # ifdef PCR_OBSOLETE /* Faster, but broken with multiple lwp's */
48 # include "th/PCR_Th.h"
49 # include "th/PCR_ThCrSec.h"
50 extern struct PCR_Th_MLRep GC_allocate_ml;
51 # define DCL_LOCK_STATE PCR_sigset_t GC_old_sig_mask
52 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
53 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
54 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
55 # define FASTLOCK() PCR_ThCrSec_EnterSys()
56 /* Here we cheat (a lot): */
57 # define FASTLOCK_SUCCEEDED() (*(int *)(&GC_allocate_ml) == 0)
58 /* TRUE if nobody currently holds the lock */
59 # define FASTUNLOCK() PCR_ThCrSec_ExitSys()
62 # include <base/PCR_Base.h>
63 # include <th/PCR_Th.h>
64 extern PCR_Th_ML GC_allocate_ml;
65 # define DCL_LOCK_STATE \
66 PCR_ERes GC_fastLockRes; PCR_sigset_t GC_old_sig_mask
67 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
68 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
69 # define FASTLOCK() (GC_fastLockRes = PCR_Th_ML_Try(&GC_allocate_ml))
70 # define FASTLOCK_SUCCEEDED() (GC_fastLockRes == PCR_ERes_okay)
71 # define FASTUNLOCK() {\
72 if( FASTLOCK_SUCCEEDED() ) PCR_Th_ML_Release(&GC_allocate_ml); }
75 extern GC_word RT0u__inCritical;
76 # define LOCK() RT0u__inCritical++
77 # define UNLOCK() RT0u__inCritical--
79 # ifdef GC_SOLARIS_THREADS
82 extern mutex_t GC_allocate_ml;
83 # define LOCK() mutex_lock(&GC_allocate_ml);
84 # define UNLOCK() mutex_unlock(&GC_allocate_ml);
87 /* Try to define GC_TEST_AND_SET and a matching GC_CLEAR for spin lock */
88 /* acquisition and release. We need this for correct operation of the */
92 inline static int GC_test_and_set(volatile unsigned int *addr) {
94 /* Note: the "xchg" instruction does not need a "lock" prefix */
95 __asm__ __volatile__("xchgl %0, %1"
96 : "=r"(oldval), "=m"(*(addr))
97 : "0"(1), "m"(*(addr)) : "memory");
100 # define GC_TEST_AND_SET_DEFINED
103 # if defined(__INTEL_COMPILER)
104 # include <ia64intrin.h>
106 inline static int GC_test_and_set(volatile unsigned int *addr) {
108 # ifndef __INTEL_COMPILER
109 __asm__ __volatile__("xchg4 %0=%1,%2"
110 : "=r"(oldval), "=m"(*addr)
111 : "r"(n) : "memory");
113 oldval = _InterlockedExchange(addr, n);
117 # define GC_TEST_AND_SET_DEFINED
118 /* Should this handle post-increment addressing?? */
119 inline static void GC_clear(volatile unsigned int *addr) {
120 # ifndef __INTEL_COMPILER
121 __asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory");
123 // there is no st4 but I can use xchg I hope
124 _InterlockedExchange(addr, 0);
127 # define GC_CLEAR_DEFINED
130 inline static int GC_test_and_set(volatile unsigned int *addr) {
133 __asm__ __volatile__("ldstub %1,%0"
134 : "=r"(oldval), "=m"(*addr)
135 : "m"(*addr) : "memory");
138 # define GC_TEST_AND_SET_DEFINED
141 /* Contributed by Tony Mantler. I'm not sure how well it was */
143 inline static int GC_test_and_set(volatile unsigned int *addr) {
144 char oldval; /* this must be no longer than 8 bits */
146 /* The return value is semi-phony. */
147 /* 'tas' sets bit 7 while the return */
148 /* value pretends bit 0 was set */
149 __asm__ __volatile__(
150 "tas %1@; sne %0; negb %0"
152 : "a" (addr) : "memory");
155 # define GC_TEST_AND_SET_DEFINED
157 # if defined(POWERPC)
158 inline static int GC_test_and_set(volatile unsigned int *addr) {
160 int temp = 1; /* locked value */
162 __asm__ __volatile__(
163 "1:\tlwarx %0,0,%1\n" /* load and reserve */
164 "\tcmpwi %0, 0\n" /* if load is */
165 "\tbne 2f\n" /* non-zero, return already set */
166 "\tstwcx. %2,0,%1\n" /* else store conditional */
167 "\tbne- 1b\n" /* retry if lost reservation */
168 "\tsync\n" /* import barrier */
169 "2:\t\n" /* oldval is zero if we set */
171 : "r"(addr), "r"(temp)
175 # define GC_TEST_AND_SET_DEFINED
176 inline static void GC_clear(volatile unsigned int *addr) {
177 __asm__ __volatile__("lwsync" : : : "memory");
180 # define GC_CLEAR_DEFINED
183 inline static int GC_test_and_set(volatile unsigned int * addr)
185 unsigned long oldvalue;
188 __asm__ __volatile__(
202 ".section .text2,\"ax\"\n"
206 :"=&r" (temp), "=m" (*addr), "=&r" (oldvalue)
207 :"Ir" (1), "m" (*addr)
212 # define GC_TEST_AND_SET_DEFINED
213 inline static void GC_clear(volatile unsigned int *addr) {
214 __asm__ __volatile__("mb" : : : "memory");
217 # define GC_CLEAR_DEFINED
220 inline static int GC_test_and_set(volatile unsigned int *addr) {
222 /* SWP on ARM is very similar to XCHG on x86. Doesn't lock the
223 * bus because there are no SMP ARM machines. If/when there are,
224 * this code will likely need to be updated. */
225 /* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
226 __asm__ __volatile__("swp %0, %1, [%2]"
232 # define GC_TEST_AND_SET_DEFINED
235 inline static int GC_test_and_set(volatile unsigned int *addr) {
236 /* Ripped from linuxthreads/sysdeps/cris/pt-machine.h. */
237 /* Included with Hans-Peter Nilsson's permission. */
238 register unsigned long int ret;
240 /* Note the use of a dummy output of *addr to expose the write.
241 * The memory barrier is to stop *other* writes being moved past
244 __asm__ __volatile__("clearf\n"
251 : "=&r" (ret), "=m" (*addr)
252 : "r" (addr), "r" ((int) 1), "m" (*addr)
256 # define GC_TEST_AND_SET_DEFINED
259 inline static int GC_test_and_set(volatile unsigned int *addr) {
261 __asm__ __volatile__ (
263 "0: cs %0,%1,0(%2)\n"
266 : "d" (1), "a" (addr)
271 # endif /* __GNUC__ */
272 # if (defined(ALPHA) && !defined(__GNUC__))
274 --> We currently assume that if gcc is not used, we are
275 --> running under Tru64.
277 # include <machine/builtins.h>
279 # define GC_test_and_set(addr) __ATOMIC_EXCH_LONG(addr, 1)
280 # define GC_TEST_AND_SET_DEFINED
281 # define GC_clear(addr) { asm("mb"); *(volatile unsigned *)addr = 0; }
282 # define GC_CLEAR_DEFINED
284 # if defined(MSWIN32)
285 # define GC_test_and_set(addr) InterlockedExchange((LPLONG)addr,1)
286 # define GC_TEST_AND_SET_DEFINED
290 # include <sys/tas.h>
291 # define GC_test_and_set(addr) _test_and_set((int *) addr,1)
292 # define GC_TEST_AND_SET_DEFINED
293 # elif __mips < 3 || !(defined (_ABIN32) || defined(_ABI64)) \
294 || !defined(_COMPILER_VERSION) || _COMPILER_VERSION < 700
296 # define GC_test_and_set(addr) _test_and_set((void *)addr,1)
298 # define GC_test_and_set(addr) test_and_set((void *)addr,1)
301 # include <sgidefs.h>
303 # define GC_test_and_set(addr) __test_and_set32((void *)addr,1)
304 # define GC_clear(addr) __lock_release(addr);
305 # define GC_CLEAR_DEFINED
307 # define GC_TEST_AND_SET_DEFINED
310 # include <sys/atomic_op.h>
311 # if (defined(_POWER) || defined(_POWERPC))
312 # if defined(__GNUC__)
313 inline static void GC_memsync() {
314 __asm__ __volatile__ ("sync" : : : "memory");
318 # define inline __inline
320 # pragma mc_func GC_memsync { \
321 "7c0004ac" /* sync (same opcode used for dcs)*/ \
325 # error dont know how to memsync
327 inline static int GC_test_and_set(volatile unsigned int * addr) {
329 if (compare_and_swap((void *)addr, &oldvalue, 1)) {
334 # define GC_TEST_AND_SET_DEFINED
335 inline static void GC_clear(volatile unsigned int *addr) {
339 # define GC_CLEAR_DEFINED
342 # if 0 /* defined(HP_PA) */
343 /* The official recommendation seems to be to not use ldcw from */
344 /* user mode. Since multithreaded incremental collection doesn't */
345 /* work anyway on HP_PA, this shouldn't be a major loss. */
347 /* "set" means 0 and "clear" means 1 here. */
348 # define GC_test_and_set(addr) !GC_test_and_clear(addr);
349 # define GC_TEST_AND_SET_DEFINED
350 # define GC_clear(addr) GC_noop1((word)(addr)); *(volatile unsigned int *)addr = 1;
351 /* The above needs a memory barrier! */
352 # define GC_CLEAR_DEFINED
354 # if defined(GC_TEST_AND_SET_DEFINED) && !defined(GC_CLEAR_DEFINED)
356 inline static void GC_clear(volatile unsigned int *addr) {
357 /* Try to discourage gcc from moving anything past this. */
358 __asm__ __volatile__(" " : : : "memory");
362 /* The function call in the following should prevent the */
363 /* compiler from moving assignments to below the UNLOCK. */
364 # define GC_clear(addr) GC_noop1((word)(addr)); \
365 *((volatile unsigned int *)(addr)) = 0;
367 # define GC_CLEAR_DEFINED
368 # endif /* !GC_CLEAR_DEFINED */
370 # if !defined(GC_TEST_AND_SET_DEFINED)
371 # define USE_PTHREAD_LOCKS
374 # if defined(GC_PTHREADS) && !defined(GC_SOLARIS_THREADS) \
375 && !defined(GC_WIN32_THREADS)
376 # define NO_THREAD (pthread_t)(-1)
377 # include <pthread.h>
378 # if defined(PARALLEL_MARK)
379 /* We need compare-and-swap to update mark bits, where it's */
380 /* performance critical. If USE_MARK_BYTES is defined, it is */
381 /* no longer needed for this purpose. However we use it in */
382 /* either case to implement atomic fetch-and-add, though that's */
383 /* less performance critical, and could perhaps be done with */
385 # if defined(GENERIC_COMPARE_AND_SWAP)
386 /* Probably not useful, except for debugging. */
387 /* We do use GENERIC_COMPARE_AND_SWAP on PA_RISC, but we */
388 /* minimize its use. */
389 extern pthread_mutex_t GC_compare_and_swap_lock;
391 /* Note that if GC_word updates are not atomic, a concurrent */
392 /* reader should acquire GC_compare_and_swap_lock. On */
393 /* currently supported platforms, such updates are atomic. */
394 extern GC_bool GC_compare_and_exchange(volatile GC_word *addr,
395 GC_word old, GC_word new_val);
396 # endif /* GENERIC_COMPARE_AND_SWAP */
398 # if !defined(GENERIC_COMPARE_AND_SWAP)
399 /* Returns TRUE if the comparison succeeded. */
400 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
405 __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
406 : "+m"(*(addr)), "=r"(result)
407 : "r" (new_val), "a"(old) : "memory");
408 return (GC_bool) result;
410 # endif /* !GENERIC_COMPARE_AND_SWAP */
411 inline static void GC_memory_barrier()
413 /* We believe the processor ensures at least processor */
414 /* consistent ordering. Thus a compiler barrier */
415 /* should suffice. */
416 __asm__ __volatile__("" : : : "memory");
421 # if !defined(GENERIC_COMPARE_AND_SWAP)
422 /* Returns TRUE if the comparison succeeded. */
423 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
428 __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
429 : "+m"(*(addr)), "=r"(result)
430 : "r" (new_val), "a"(old) : "memory");
431 return (GC_bool) result;
433 # endif /* !GENERIC_COMPARE_AND_SWAP */
434 inline static void GC_memory_barrier()
436 /* We believe the processor ensures at least processor */
437 /* consistent ordering. Thus a compiler barrier */
438 /* should suffice. */
439 __asm__ __volatile__("" : : : "memory");
443 # if defined(POWERPC)
444 # if !defined(GENERIC_COMPARE_AND_SWAP)
445 # if CPP_WORDSZ == 64
446 /* Returns TRUE if the comparison succeeded. */
447 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
448 GC_word old, GC_word new_val)
450 unsigned long result, dummy;
451 __asm__ __volatile__(
452 "1:\tldarx %0,0,%5\n"
462 : "=&r" (dummy), "=r" (result), "=p" (addr)
463 : "r" (new_val), "r" (old), "2"(addr)
465 return (GC_bool) result;
468 /* Returns TRUE if the comparison succeeded. */
469 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
470 GC_word old, GC_word new_val)
473 __asm__ __volatile__(
474 "1:\tlwarx %0,0,%5\n"
484 : "=&r" (dummy), "=r" (result), "=p" (addr)
485 : "r" (new_val), "r" (old), "2"(addr)
487 return (GC_bool) result;
490 # endif /* !GENERIC_COMPARE_AND_SWAP */
491 inline static void GC_memory_barrier()
493 __asm__ __volatile__("sync" : : : "memory");
495 # endif /* POWERPC */
498 # if !defined(GENERIC_COMPARE_AND_SWAP)
499 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
500 GC_word old, GC_word new_val)
502 unsigned long oldval;
503 # if CPP_WORDSZ == 32
504 __asm__ __volatile__(
506 "mov ar.ccv=%3 ;; cmpxchg4.rel %0=[%0],%2,ar.ccv"
508 : "r"(addr), "r"(new_val), "r"(old) : "memory");
510 __asm__ __volatile__(
511 "mov ar.ccv=%3 ;; cmpxchg8.rel %0=[%1],%2,ar.ccv"
513 : "r"(addr), "r"(new_val), "r"(old) : "memory");
515 return (oldval == old);
517 # endif /* !GENERIC_COMPARE_AND_SWAP */
519 /* Shouldn't be needed; we use volatile stores instead. */
520 inline static void GC_memory_barrier()
522 __asm__ __volatile__("mf" : : : "memory");
527 # if !defined(GENERIC_COMPARE_AND_SWAP)
528 # if defined(__GNUC__)
529 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
530 GC_word old, GC_word new_val)
532 unsigned long was_equal;
535 __asm__ __volatile__(
544 :"=&r" (temp), "=m" (*addr), "=&r" (was_equal)
545 : "r" (new_val), "Ir" (old)
549 # else /* !__GNUC__ */
550 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
551 GC_word old, GC_word new_val)
553 return __CMP_STORE_QUAD(addr, old, new_val, addr);
555 # endif /* !__GNUC__ */
556 # endif /* !GENERIC_COMPARE_AND_SWAP */
558 inline static void GC_memory_barrier()
560 __asm__ __volatile__("mb" : : : "memory");
563 # define GC_memory_barrier() asm("mb")
564 # endif /* !__GNUC__ */
567 # if !defined(GENERIC_COMPARE_AND_SWAP)
568 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
569 GC_word old, GC_word new_val)
572 __asm__ __volatile__ (
580 : "=&d" (retval), "+d" (old)
581 : "d" (new_val), "a" (addr)
586 # define GC_memory_barrier()
588 # if !defined(GENERIC_COMPARE_AND_SWAP)
589 /* Returns the original value of *addr. */
590 inline static GC_word GC_atomic_add(volatile GC_word *addr,
596 } while (!GC_compare_and_exchange(addr, old, old+how_much));
599 # else /* GENERIC_COMPARE_AND_SWAP */
600 /* So long as a GC_word can be atomically updated, it should */
601 /* be OK to read *addr without a lock. */
602 extern GC_word GC_atomic_add(volatile GC_word *addr, GC_word how_much);
603 # endif /* GENERIC_COMPARE_AND_SWAP */
605 # endif /* PARALLEL_MARK */
607 # if !defined(THREAD_LOCAL_ALLOC) && !defined(USE_PTHREAD_LOCKS)
608 /* In the THREAD_LOCAL_ALLOC case, the allocation lock tends to */
609 /* be held for long periods, if it is held at all. Thus spinning */
610 /* and sleeping for fixed periods are likely to result in */
611 /* significant wasted time. We thus rely mostly on queued locks. */
612 # define USE_SPIN_LOCK
613 extern volatile unsigned int GC_allocate_lock;
614 extern void GC_lock(void);
615 /* Allocation lock holder. Only set if acquired by client through */
616 /* GC_call_with_alloc_lock. */
617 # ifdef GC_ASSERTIONS
619 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); \
622 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
623 GC_clear(&GC_allocate_lock); }
626 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
628 GC_clear(&GC_allocate_lock)
629 # endif /* !GC_ASSERTIONS */
631 /* Another alternative for OSF1 might be: */
632 # include <sys/mman.h>
633 extern msemaphore GC_allocate_semaphore;
634 # define LOCK() { if (msem_lock(&GC_allocate_semaphore, MSEM_IF_NOWAIT) \
635 != 0) GC_lock(); else GC_allocate_lock = 1; }
636 /* The following is INCORRECT, since the memory model is too weak. */
637 /* Is this true? Presumably msem_unlock has the right semantics? */
639 # define UNLOCK() { GC_allocate_lock = 0; \
640 msem_unlock(&GC_allocate_semaphore, 0); }
642 # else /* THREAD_LOCAL_ALLOC || USE_PTHREAD_LOCKS */
643 # ifndef USE_PTHREAD_LOCKS
644 # define USE_PTHREAD_LOCKS
646 # endif /* THREAD_LOCAL_ALLOC */
647 # ifdef USE_PTHREAD_LOCKS
648 # include <pthread.h>
649 extern pthread_mutex_t GC_allocate_ml;
650 # ifdef GC_ASSERTIONS
655 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
656 pthread_mutex_unlock(&GC_allocate_ml); }
657 # else /* !GC_ASSERTIONS */
658 # if defined(NO_PTHREAD_TRYLOCK)
659 # define LOCK() GC_lock();
660 # else /* !defined(NO_PTHREAD_TRYLOCK) */
662 { if (0 != pthread_mutex_trylock(&GC_allocate_ml)) GC_lock(); }
664 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
665 # endif /* !GC_ASSERTIONS */
666 # endif /* USE_PTHREAD_LOCKS */
667 # define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
668 # define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
669 # define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
670 extern VOLATILE GC_bool GC_collecting;
671 # define ENTER_GC() GC_collecting = 1;
672 # define EXIT_GC() GC_collecting = 0;
673 extern void GC_lock(void);
674 extern pthread_t GC_lock_holder;
675 # ifdef GC_ASSERTIONS
676 extern pthread_t GC_mark_lock_holder;
678 # endif /* GC_PTHREADS with linux_threads.c implementation */
679 # if defined(GC_WIN32_THREADS)
680 # if defined(GC_PTHREADS)
681 # include <pthread.h>
682 extern pthread_mutex_t GC_allocate_ml;
683 # define LOCK() pthread_mutex_lock(&GC_allocate_ml)
684 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
686 # include <windows.h>
687 GC_API CRITICAL_SECTION GC_allocate_ml;
688 # define LOCK() EnterCriticalSection(&GC_allocate_ml);
689 # define UNLOCK() LeaveCriticalSection(&GC_allocate_ml);
692 # ifndef SET_LOCK_HOLDER
693 # define SET_LOCK_HOLDER()
694 # define UNSET_LOCK_HOLDER()
695 # define I_HOLD_LOCK() FALSE
696 /* Used on platforms were locks can be reacquired, */
697 /* so it doesn't matter if we lie. */
699 # else /* !THREADS */
702 # endif /* !THREADS */
703 # ifndef SET_LOCK_HOLDER
704 # define SET_LOCK_HOLDER()
705 # define UNSET_LOCK_HOLDER()
706 # define I_HOLD_LOCK() FALSE
707 /* Used on platforms were locks can be reacquired, */
708 /* so it doesn't matter if we lie. */
715 # ifndef DCL_LOCK_STATE
716 # define DCL_LOCK_STATE
719 # define FASTLOCK() LOCK()
720 # define FASTLOCK_SUCCEEDED() TRUE
721 # define FASTUNLOCK() UNLOCK()
724 #endif /* GC_LOCKS_H */