22 #define IRQF_TIMER (1<<IRQ_TIMER)
23 #define IRQF_NAND (1<<IRQ_NAND)
24 #define IRQF_AES (1<<IRQ_AES)
25 #define IRQF_SDHC (1<<IRQ_SDHC)
26 #define IRQF_GPIO1B (1<<IRQ_GPIO1B)
27 #define IRQF_GPIO1 (1<<IRQ_GPIO1)
28 #define IRQF_RESET (1<<IRQ_RESET)
29 #define IRQF_IPC (1<<IRQ_IPC)
30 #define IRQF_OHCI0 (1<<IRQ_OHCI0)
31 #define IRQF_OHCI1 (1<<IRQ_OHCI1)
34 IRQF_TIMER|IRQF_NAND|IRQF_GPIO1B|IRQF_GPIO1| \
35 IRQF_RESET|IRQF_IPC|IRQF_AES|IRQF_SDHC| \
36 IRQF_OHCI0|IRQF_OHCI1 \
40 /* broadway processor interface registers */
41 #define BW_PI_IRQFLAG (0x0c003000)
42 #define BW_PI_IRQMASK (0x0c003004)
45 /* stolen from libogc - gc/ogc/machine/processor.h */
46 #define _CPU_ISR_Enable() \
47 { register u32 _val = 0; \
48 __asm__ __volatile__ ( \
50 "ori %0,%0,0x8000\n" \
52 : "=&r" ((_val)) : "0" ((_val)) \
56 #define _CPU_ISR_Disable( _isr_cookie ) \
57 { register u32 _disable_mask = 0; \
59 __asm__ __volatile__ ( \
61 "rlwinm %1,%0,0,17,15\n" \
64 : "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) \
65 : "0" ((_isr_cookie)), "1" ((_disable_mask)) \
69 #define _CPU_ISR_Restore( _isr_cookie ) \
70 { register u32 _enable_mask = 0; \
71 __asm__ __volatile__ ( \
75 " ori %1,%1,0x8000\n" \
78 : "=r"((_isr_cookie)),"=&r" ((_enable_mask)) \
79 : "0"((_isr_cookie)),"1" ((_enable_mask)) \
83 void irq_initialize(void);
84 void irq_shutdown(void);
86 void irq_handler(void);
88 void irq_enable(u32 irq);
89 void irq_disable(u32 irq);
92 void irq_restore(u32 cookie);
95 static inline void irq_wait(void)
98 __asm__ volatile ( "mcr\tp15, 0, %0, c7, c0, 4" : : "r" (data) );
102 //void irq_set_alarm(u32 ms, u8 enable);
106 // stub functions allow us to avoid sprinkling other code with ifdefs
107 static inline u32 irq_kill(void) {
111 static inline void irq_restore(u32 cookie) {