2 mini - a Free Software replacement for the Nintendo/BroadOn IOS.
3 Hollywood register definitions
5 Copyright (C) 2008, 2009 Haxx Enterprises <bushing@gmail.com>
6 Copyright (C) 2008, 2009 Sven Peter <svenpeter@gmail.com>
7 Copyright (C) 2008, 2009 Hector Martin "marcan" <marcan@marcansoft.com>
8 Copyright (C) 2008, 2009 John Kelley <wiidev@kelley.ca>
10 # This code is licensed to you under the terms of the GNU GPL, version 2;
11 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
14 #ifndef __HOLLYWOOD_H__
15 #define __HOLLYWOOD_H__
17 /* Hollywood Registers */
19 #define HW_PPC_REG_BASE 0xd000000
20 #define HW_REG_BASE 0xd800000
22 // The PPC can only see the first three IPC registers
23 #define HW_IPC_PPCMSG (HW_REG_BASE + 0x000)
24 #define HW_IPC_PPCCTRL (HW_REG_BASE + 0x004)
25 #define HW_IPC_ARMMSG (HW_REG_BASE + 0x008)
26 #define HW_IPC_ARMCTRL (HW_REG_BASE + 0x00c)
28 #define HW_TIMER (HW_REG_BASE + 0x010)
29 #define HW_ALARM (HW_REG_BASE + 0x014)
31 #define HW_PPCIRQFLAG (HW_REG_BASE + 0x030)
32 #define HW_PPCIRQMASK (HW_REG_BASE + 0x034)
34 #define HW_ARMIRQFLAG (HW_REG_BASE + 0x038)
35 #define HW_ARMIRQMASK (HW_REG_BASE + 0x03c)
37 #define HW_MEMMIRR (HW_REG_BASE + 0x060)
39 // something to do with PPCBOOT
40 // and legacy DI it seems ?!?
41 #define HW_EXICTRL (HW_REG_BASE + 0x070)
42 #define EXICTRL_ENABLE_EXI 1
44 // PPC side of GPIO1 (Starlet can access this too)
46 #define HW_GPIO1BOUT (HW_REG_BASE + 0x0c0)
47 // Direction (1=output)
48 #define HW_GPIO1BDIR (HW_REG_BASE + 0x0c4)
50 #define HW_GPIO1BIN (HW_REG_BASE + 0x0c8)
52 #define HW_GPIO1BINTLVL (HW_REG_BASE + 0x0cc)
53 // Interrupt flags (write 1 to clear)
54 #define HW_GPIO1BINTFLAG (HW_REG_BASE + 0x0d0)
55 // Interrupt propagation enable
56 // Do these interrupts go anywhere???
57 #define HW_GPIO1BINTENABLE (HW_REG_BASE + 0x0d4)
58 //??? seems to be a mirror of inputs at some point... power-up state?
59 #define HW_GPIO1BINMIR (HW_REG_BASE + 0x0d8)
60 // 0xFFFFFF by default, if cleared disables respective outputs. Top bits non-settable.
61 #define HW_GPIO1ENABLE (HW_REG_BASE + 0x0dc)
63 #define HW_GPIO1_SLOT 0x000020
64 #define HW_GPIO1_DEBUG 0xFF0000
65 #define HW_GPIO1_DEBUG_SH 16
67 // Starlet side of GPIO1
69 #define HW_GPIO1OUT (HW_REG_BASE + 0x0e0)
70 // Direction (1=output)
71 #define HW_GPIO1DIR (HW_REG_BASE + 0x0e4)
73 #define HW_GPIO1IN (HW_REG_BASE + 0x0e8)
75 #define HW_GPIO1INTLVL (HW_REG_BASE + 0x0ec)
76 // Interrupt flags (write 1 to clear)
77 #define HW_GPIO1INTFLAG (HW_REG_BASE + 0x0f0)
78 // Interrupt propagation enable (interrupts go to main interrupt 0x800)
79 #define HW_GPIO1INTENABLE (HW_REG_BASE + 0x0f4)
80 //??? seems to be a mirror of inputs at some point... power-up state?
81 #define HW_GPIO1INMIR (HW_REG_BASE + 0x0f8)
82 // Owner of each GPIO bit. If 1, GPIO1B registers assume control. If 0, GPIO1 registers assume control.
83 #define HW_GPIO1OWNER (HW_REG_BASE + 0x0fc)
86 #define HW_DIFLAGS (HW_REG_BASE + 0x180)
87 #define DIFLAGS_BOOT_CODE 0x100000
90 #define HW_RESETS (HW_REG_BASE + 0x194)
92 #define HW_CLOCKS (HW_REG_BASE + 0x1b4)
94 #define HW_GPIO2OUT (HW_REG_BASE + 0x1c8)
95 #define HW_GPIO2DIR (HW_REG_BASE + 0x1cc)
96 #define HW_GPIO2IN (HW_REG_BASE + 0x1d0)
98 #define HW_OTPCMD (HW_REG_BASE + 0x1ec)
99 #define HW_OTPDATA (HW_REG_BASE + 0x1f0)
100 #define HW_VERSION (HW_REG_BASE + 0x214)
104 #define NAND_REG_BASE 0xd010000
106 #define NAND_CMD (NAND_REG_BASE + 0x000)
107 #define NAND_STATUS NAND_CMD
108 #define NAND_CONF (NAND_REG_BASE + 0x004)
109 #define NAND_ADDR0 (NAND_REG_BASE + 0x008)
110 #define NAND_ADDR1 (NAND_REG_BASE + 0x00c)
111 #define NAND_DATA (NAND_REG_BASE + 0x010)
112 #define NAND_ECC (NAND_REG_BASE + 0x014)
113 #define NAND_UNK1 (NAND_REG_BASE + 0x018)
114 #define NAND_UNK2 (NAND_REG_BASE + 0x01c)
118 #define AES_REG_BASE 0xd020000
120 #define AES_CMD (AES_REG_BASE + 0x000)
121 #define AES_SRC (AES_REG_BASE + 0x004)
122 #define AES_DEST (AES_REG_BASE + 0x008)
123 #define AES_KEY (AES_REG_BASE + 0x00c)
124 #define AES_IV (AES_REG_BASE + 0x010)
126 /* SHA-1 Registers */
128 #define SHA_REG_BASE 0xd030000
130 #define SHA_CMD (SHA_REG_BASE + 0x000)
131 #define SHA_SRC (SHA_REG_BASE + 0x004)
132 #define SHA_H0 (SHA_REG_BASE + 0x008)
133 #define SHA_H1 (SHA_REG_BASE + 0x00c)
134 #define SHA_H2 (SHA_REG_BASE + 0x010)
135 #define SHA_H3 (SHA_REG_BASE + 0x014)
136 #define SHA_H4 (SHA_REG_BASE + 0x018)
138 /* SD Host Controller Registers */
140 #define SDHC_REG_BASE 0xd070000
142 /* OHCI0 Registers */
144 #define OHCI0_REG_BASE 0xd050000
146 #define OHCI0_HC_REVISION (OHCI0_REG_BASE + 0x00)
147 #define OHCI0_HC_CONTROL (OHCI0_REG_BASE + 0x04)
148 #define OHCI0_HC_COMMAND_STATUS (OHCI0_REG_BASE + 0x08)
149 #define OHCI0_HC_INT_STATUS (OHCI0_REG_BASE + 0x0C)
151 #define OHCI0_HC_INT_ENABLE (OHCI0_REG_BASE + 0x10)
152 #define OHCI0_HC_INT_DISABLE (OHCI0_REG_BASE + 0x14)
153 #define OHCI0_HC_HCCA (OHCI0_REG_BASE + 0x18)
154 #define OHCI0_HC_PERIOD_CURRENT_ED (OHCI0_REG_BASE + 0x1C)
156 #define OHCI0_HC_CTRL_HEAD_ED (OHCI0_REG_BASE + 0x20)
157 #define OHCI0_HC_CTRL_CURRENT_ED (OHCI0_REG_BASE + 0x24)
158 #define OHCI0_HC_BULK_HEAD_ED (OHCI0_REG_BASE + 0x28)
159 #define OHCI0_HC_BULK_CURRENT_ED (OHCI0_REG_BASE + 0x2C)
161 #define OHCI0_HC_DONE_HEAD (OHCI0_REG_BASE + 0x30)
162 #define OHCI0_HC_FM_INTERVAL (OHCI0_REG_BASE + 0x34)
163 #define OHCI0_HC_FM_REMAINING (OHCI0_REG_BASE + 0x38)
164 #define OHCI0_HC_FM_NUMBER (OHCI0_REG_BASE + 0x3C)
166 #define OHCI0_HC_PERIODIC_START (OHCI0_REG_BASE + 0x40)
167 #define OHCI0_HC_LS_THRESHOLD (OHCI0_REG_BASE + 0x44)
168 #define OHCI0_HC_RH_DESCRIPTOR_A (OHCI0_REG_BASE + 0x48)
169 #define OHCI0_HC_RH_DESCRIPTOR_B (OHCI0_REG_BASE + 0x4C)
171 #define OHCI0_HC_RH_STATUS (OHCI0_REG_BASE + 0x50)
172 #define OHCI0_HC_RH_PORT_STATUS_1 (OHCI0_REG_BASE + 0x54)
173 #define OHCI0_HC_RH_PORT_STATUS_2 (OHCI0_REG_BASE + 0x58)
175 /* OHCI1 Registers */
177 #define OHCI1_REG_BASE 0xd060000
179 #define OHCI1_HC_REVISION (OHCI1_REG_BASE + 0x00)
180 #define OHCI1_HC_CONTROL (OHCI1_REG_BASE + 0x04)
181 #define OHCI1_HC_COMMAND_STATUS (OHCI1_REG_BASE + 0x08)
182 #define OHCI1_HC_INT_STATUS (OHCI1_REG_BASE + 0x0C)
184 #define OHCI1_HC_INT_ENABLE (OHCI1_REG_BASE + 0x10)
185 #define OHCI1_HC_INT_DISABLE (OHCI1_REG_BASE + 0x14)
186 #define OHCI1_HC_HCCA (OHCI1_REG_BASE + 0x18)
187 #define OHCI1_HC_PERIOD_CURRENT_ED (OHCI1_REG_BASE + 0x1C)
189 #define OHCI1_HC_CTRL_HEAD_ED (OHCI1_REG_BASE + 0x20)
190 #define OHCI1_HC_CTRL_CURRENT_ED (OHCI1_REG_BASE + 0x24)
191 #define OHCI1_HC_BULK_HEAD_ED (OHCI1_REG_BASE + 0x28)
192 #define OHCI1_HC_BULK_CURRENT_ED (OHCI1_REG_BASE + 0x2C)
194 #define OHCI1_HC_DONE_HEAD (OHCI1_REG_BASE + 0x30)
195 #define OHCI1_HC_FM_INTERVAL (OHCI1_REG_BASE + 0x34)
196 #define OHCI1_HC_FM_REMAINING (OHCI1_REG_BASE + 0x38)
197 #define OHCI1_HC_FM_NUMBER (OHCI1_REG_BASE + 0x3C)
199 #define OHCI1_HC_PERIODIC_START (OHCI1_REG_BASE + 0x40)
200 #define OHCI1_HC_LS_THRESHOLD (OHCI1_REG_BASE + 0x44)
201 #define OHCI1_HC_RH_DESCRIPTOR_A (OHCI1_REG_BASE + 0x48)
202 #define OHCI1_HC_RH_DESCRIPTOR_B (OHCI1_REG_BASE + 0x4C)
204 #define OHCI1_HC_RH_STATUS (OHCI1_REG_BASE + 0x50)
205 #define OHCI1_HC_RH_PORT_STATUS_1 (OHCI1_REG_BASE + 0x54)
206 #define OHCI1_HC_RH_PORT_STATUS_2 (OHCI1_REG_BASE + 0x58)
209 #define EHCI_REG_BASE 0xd040000
211 /* stolen from mikep2 patched linux kernel: drivers/usb/host/ohci-mipc.c */
212 #define EHCI_CTL (EHCI_REG_BASE + 0xCC)
213 #define EHCI_CTL_OH0INTE (1<<11) /* oh0 interrupt enable */
214 #define EHCI_CTL_OH1INTE (1<<12) /* oh1 interrupt enable */
218 #define EXI_REG_BASE 0xd806800
219 #define EXI0_REG_BASE (EXI_REG_BASE+0x000)
220 #define EXI1_REG_BASE (EXI_REG_BASE+0x014)
221 #define EXI2_REG_BASE (EXI_REG_BASE+0x028)
223 #define EXI0_CSR (EXI0_REG_BASE+0x000)
224 #define EXI0_MAR (EXI0_REG_BASE+0x004)
225 #define EXI0_LENGTH (EXI0_REG_BASE+0x008)
226 #define EXI0_CR (EXI0_REG_BASE+0x00c)
227 #define EXI0_DATA (EXI0_REG_BASE+0x010)
229 #define EXI1_CSR (EXI1_REG_BASE+0x000)
230 #define EXI1_MAR (EXI1_REG_BASE+0x004)
231 #define EXI1_LENGTH (EXI1_REG_BASE+0x008)
232 #define EXI1_CR (EXI1_REG_BASE+0x00c)
233 #define EXI1_DATA (EXI1_REG_BASE+0x010)
235 #define EXI2_CSR (EXI2_REG_BASE+0x000)
236 #define EXI2_MAR (EXI2_REG_BASE+0x004)
237 #define EXI2_LENGTH (EXI2_REG_BASE+0x008)
238 #define EXI2_CR (EXI2_REG_BASE+0x00c)
239 #define EXI2_DATA (EXI2_REG_BASE+0x010)
241 #define EXI_BOOT_BASE (EXI_REG_BASE+0x040)
243 /* MEMORY CONTROLLER Registers */
245 #define MEM_REG_BASE 0xd8b4000
246 #define MEM_PROT (MEM_REG_BASE+0x20a)
247 #define MEM_PROT_START (MEM_REG_BASE+0x20c)
248 #define MEM_PROT_END (MEM_REG_BASE+0x20e)
249 #define MEM_FLUSHREQ (MEM_REG_BASE+0x228)
250 #define MEM_FLUSHACK (MEM_REG_BASE+0x22a)