2 use ieee.std_logic_1164.all;
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3 use ieee.numeric_std.all;
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4 use work.math_pkg.all;
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6 architecture beh of counter is
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7 signal cnt_int, cnt_next : integer range 0 to CNT_MAX;
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9 cnt <= std_logic_vector(to_unsigned(cnt_int, log2c(CNT_MAX)));
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11 process(sys_clk, sys_res_n)
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13 if sys_res_n = '0' then
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15 elsif rising_edge(sys_clk) then
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16 cnt_int <= cnt_next;
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20 process(cnt_int, clear_cnt)
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22 cnt_next <= cnt_int;
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24 if clear_cnt = '1' then
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26 elsif cnt_int < CNT_MAX then
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27 cnt_next <= cnt_int + 1;
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30 end architecture beh;
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