debouncing/prj/create_project.tcl

   1 package require ::quartus::project\r
   2 \r
   3 set need_to_close_project 0\r
   4 set make_assignments 1\r
   5 \r
   6 # Check that the right project is open\r
   7 if {[is_project_open]} {\r
   8         if {[string compare $quartus(project) "mjl_stratix"]} {\r
   9                 puts "Project mjl_stratix is not open"\r
  10                 set make_assignments 0\r
  11         }\r
  12 } else {\r
  13         # Only open if not already open\r
  14         if {[project_exists mjl_stratix]} {\r
  15                 project_open -revision mjl_stratix mjl_stratix\r
  16         } else {\r
  17                 project_new -revision mjl_stratix mjl_stratix\r
  18         }\r
  19         set need_to_close_project 1\r
  20 }\r
  21 \r
  22 # Make assignments\r
  23 if {$make_assignments} {\r
  24         set_global_assignment -name FAMILY Stratix\r
  25         set_global_assignment -name DEVICE EP1S25F672C6\r
  26         set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"\r
  27         set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation\r
  28         set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga\r
  29         set_global_assignment -name MISC_FILE "mjl_stratix.dpf"\r
  30         set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"\r
  31         set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"\r
  32         set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"\r
  33 \r
  34         set_global_assignment -name TOP_LEVEL_ENTITY debounce_top\r
  35         set_global_assignment -name VHDL_FILE ../src/counter.vhd\r
  36         set_global_assignment -name VHDL_FILE ../src/counter_beh.vhd\r
  37         set_global_assignment -name VHDL_FILE ../src/debounce.vhd\r
  38         set_global_assignment -name VHDL_FILE ../src/debounce_fsm.vhd\r
  39         set_global_assignment -name VHDL_FILE ../src/debounce_fsm_beh.vhd\r
  40         set_global_assignment -name VHDL_FILE ../src/debounce_pkg.vhd\r
  41         set_global_assignment -name VHDL_FILE ../src/debounce_struct.vhd\r
  42         set_global_assignment -name VHDL_FILE ../src/debounce_tb.vhd\r
  43         set_global_assignment -name VHDL_FILE ../src/debounce_top.vhd\r
  44         set_global_assignment -name VHDL_FILE ../src/debounce_top_struct.vhd\r
  45         set_global_assignment -name VHDL_FILE ../src/event_counter.vhd\r
  46         set_global_assignment -name VHDL_FILE ../src/event_counter_beh.vhd\r
  47         set_global_assignment -name VHDL_FILE ../src/event_counter_pkg.vhd\r
  48         set_global_assignment -name VHDL_FILE ../src/math_pkg.vhd\r
  49         set_global_assignment -name VHDL_FILE ../src/sync.vhd\r
  50         set_global_assignment -name VHDL_FILE ../src/sync_beh.vhd\r
  51         set_global_assignment -name VHDL_FILE ../src/sync_pkg.vhd\r
  52 \r
  53         set_location_assignment PIN_T2 -to seg_b[6]\r
  54         set_location_assignment PIN_AA11 -to seg_b[5]\r
  55         set_location_assignment PIN_R6 -to seg_b[4]\r
  56         set_location_assignment PIN_R4 -to seg_b[3]\r
  57         set_location_assignment PIN_N8 -to seg_b[2]\r
  58         set_location_assignment PIN_Y11 -to seg_b[0]\r
  59         set_location_assignment PIN_N7 -to seg_b[1]\r
  60         set_location_assignment PIN_R23 -to seg_a[6]\r
  61         set_location_assignment PIN_R22 -to seg_a[5]\r
  62         set_location_assignment PIN_R21 -to seg_a[4]\r
  63         set_location_assignment PIN_R20 -to seg_a[3]\r
  64         set_location_assignment PIN_R19 -to seg_a[2]\r
  65         set_location_assignment PIN_R9 -to seg_a[1]\r
  66         set_location_assignment PIN_R8 -to seg_a[0]\r
  67         set_location_assignment PIN_N3 -to sys_clk\r
  68         set_location_assignment PIN_AF17 -to sys_res_n\r
  69      set_location_assignment PIN_A3 -to btn_a\r
  70 \r
  71         set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk\r
  72         set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk\r
  73 \r
  74         set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"\r
  75         set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"\r
  76         set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
  77         set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\r
  78         set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\r
  79 \r
  80         # Commit assignments\r
  81         export_assignments\r
  82 \r
  83         # Close project\r
  84         if {$need_to_close_project} {\r
  85                 project_close\r
  86         }\r
  87 }\r