1 # -------------------------------------------------------------------------- #
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3 # Copyright (C) 1991-2009 Altera Corporation
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4 # Your use of Altera Corporation's design tools, logic functions
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5 # and other software and tools, and its AMPP partner logic
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6 # functions, and any output files from any of the foregoing
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7 # (including device programming or simulation files), and any
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8 # associated documentation or information are expressly subject
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9 # to the terms and conditions of the Altera Program License
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10 # Subscription Agreement, Altera MegaCore Function License
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11 # Agreement, or other applicable license agreement, including,
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12 # without limitation, that your use is for the sole purpose of
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13 # programming logic devices manufactured by Altera and sold by
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14 # Altera or its authorized distributors. Please refer to the
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15 # applicable agreement for further details.
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17 # -------------------------------------------------------------------------- #
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20 # Version 9.1 Build 222 10/21/2009 SJ Full Version
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21 # Date created = 10:23:26 March 26, 2010
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23 # -------------------------------------------------------------------------- #
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27 # 1) The default values for assignments are stored in the file:
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28 # mjl_stratix_assignment_defaults.qdf
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29 # If this file doesn't exist, see file:
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30 # assignment_defaults.qdf
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32 # 2) Altera recommends that you do not modify this file. This
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33 # file is updated automatically by the Quartus II software
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34 # and any changes you make may be lost or overwritten.
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36 # -------------------------------------------------------------------------- #
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39 set_global_assignment -name FAMILY Stratix
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40 set_global_assignment -name DEVICE EP1S25F672C6
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41 set_global_assignment -name TOP_LEVEL_ENTITY debounce_top
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42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
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43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:23:26 MARCH 26, 2010"
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44 set_global_assignment -name LAST_QUARTUS_VERSION 9.1
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45 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
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46 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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47 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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48 set_global_assignment -name MISC_FILE mjl_stratix.dpf
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49 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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50 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
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51 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
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52 set_global_assignment -name VHDL_FILE ../src/counter.vhd
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53 set_global_assignment -name VHDL_FILE ../src/counter_beh.vhd
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54 set_global_assignment -name VHDL_FILE ../src/debounce.vhd
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55 set_global_assignment -name VHDL_FILE ../src/debounce_fsm.vhd
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56 set_global_assignment -name VHDL_FILE ../src/debounce_fsm_beh.vhd
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57 set_global_assignment -name VHDL_FILE ../src/debounce_pkg.vhd
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58 set_global_assignment -name VHDL_FILE ../src/debounce_struct.vhd
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59 set_global_assignment -name VHDL_FILE ../src/debounce_tb.vhd
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60 set_global_assignment -name VHDL_FILE ../src/debounce_top.vhd
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61 set_global_assignment -name VHDL_FILE ../src/debounce_top_struct.vhd
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62 set_global_assignment -name VHDL_FILE ../src/event_counter.vhd
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63 set_global_assignment -name VHDL_FILE ../src/event_counter_beh.vhd
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64 set_global_assignment -name VHDL_FILE ../src/event_counter_pkg.vhd
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65 set_global_assignment -name VHDL_FILE ../src/math_pkg.vhd
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66 set_global_assignment -name VHDL_FILE ../src/sync.vhd
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67 set_global_assignment -name VHDL_FILE ../src/sync_beh.vhd
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68 set_global_assignment -name VHDL_FILE ../src/sync_pkg.vhd
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69 set_location_assignment PIN_T2 -to seg_b[6]
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70 set_location_assignment PIN_AA11 -to seg_b[5]
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71 set_location_assignment PIN_R6 -to seg_b[4]
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72 set_location_assignment PIN_R4 -to seg_b[3]
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73 set_location_assignment PIN_N8 -to seg_b[2]
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74 set_location_assignment PIN_Y11 -to seg_b[0]
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75 set_location_assignment PIN_N7 -to seg_b[1]
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76 set_location_assignment PIN_R23 -to seg_a[6]
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77 set_location_assignment PIN_R22 -to seg_a[5]
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78 set_location_assignment PIN_R21 -to seg_a[4]
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79 set_location_assignment PIN_R20 -to seg_a[3]
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80 set_location_assignment PIN_R19 -to seg_a[2]
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81 set_location_assignment PIN_R9 -to seg_a[1]
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82 set_location_assignment PIN_R8 -to seg_a[0]
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83 set_location_assignment PIN_N3 -to sys_clk
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84 set_location_assignment PIN_AF17 -to sys_res_n
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85 set_location_assignment PIN_A3 -to btn_a
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86 set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
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87 set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
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88 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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89 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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90 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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91 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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92 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top