2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
11 use work.extension_7seg_pkg.all;
12 use work.extension_imp_pkg.all;
14 architecture behav of writeback_stage is
16 signal data_ram_read, data_ram_read_ext : word_t;
17 signal data_addr : word_t;
19 signal wb_reg, wb_reg_nxt : writeback_rec;
21 signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp : extmod_rec;
22 signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out : gp_register_t;
24 --signal int_req : interrupt_t;
25 signal uart_int : std_logic;
28 signal sel_nxt, dmem_we, ext_anysel : std_logic;
30 signal calc_mem_res : gp_register_t;
34 ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
35 ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
37 spartan3e: if FPGATYPE = "s3e" generate
44 data_addr(DATA_ADDR_WIDTH+1 downto 2),
45 data_addr(DATA_ADDR_WIDTH+1 downto 2),
48 wb_reg_nxt.data, --ram_data,
52 -- else generate gibt es erst mit vhdl 2008 ...
53 altera: if FPGATYPE /= "s3e" generate
61 data_addr(DATA_ADDR_WIDTH+1 downto 2),
62 data_addr(DATA_ADDR_WIDTH+1 downto 2),
65 wb_reg_nxt.data, --ram_data,
98 altera_7seg: if FPGATYPE /= "s3e" generate
114 interrupt : extension_interrupt
130 syn: process(clk, reset)
134 if (reset = RESET_VALUE) then
135 wb_reg.address <= (others => '0');
136 wb_reg.dmem_en <= '0';
137 wb_reg.dmem_write_en <= '0';
139 wb_reg.byte_s <= '0';
141 wb_reg.byte_en <= (others => '0');
142 wb_reg.data <= (others =>'0');
143 elsif rising_edge(clk) then
144 wb_reg <= wb_reg_nxt;
149 -- type writeback_rec is record
150 -- address : in word_t; --ureg
151 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
152 -- dmem_write_en : in std_logic; --ureg
153 -- hword_hl : in std_logic --ureg
158 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data)
159 variable byte_en : byte_en_t;
160 variable address_val : std_logic_vector(1 downto 0);
162 wb_reg_nxt.address <= address;
163 wb_reg_nxt.dmem_en <= dmem_en;
164 wb_reg_nxt.dmem_write_en <= dmem_write_en;
165 wb_reg_nxt.hword <= hword;
166 wb_reg_nxt.byte_s <= byte_s;
168 calc_mem_res <= result; --(others => '0');
170 wb_reg_nxt.data <= ram_data;
171 byte_en := (others => '0');
172 address_val := address(BYTEADDR-1 downto 0);
173 if dmem_en = '1' then
175 -- case address(BYTEADDR-1 downto 0) is
178 byte_en(1 downto 0) := "11";
180 byte_en(3 downto 2) := "11";
181 wb_reg_nxt.data(31 downto 16) <= ram_data(15 downto 0);
184 elsif byte_s = '1' then
185 -- case address(BYTEADDR-1 downto 0) is
187 when "00" => byte_en(0) := '1';
190 wb_reg_nxt.data(15 downto 8) <= ram_data(7 downto 0);
193 wb_reg_nxt.data(23 downto 16) <= ram_data(7 downto 0);
196 wb_reg_nxt.data(31 downto 24) <= ram_data(7 downto 0);
200 byte_en := (others => '1');
203 wb_reg_nxt.byte_en <= byte_en;
205 -- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
206 -- calc_mem_res <= data_ram_read;
207 -- if (wb_reg.hword = '1') then
208 -- calc_mem_res <= (others => '0');
209 -- if (wb_reg.address(1) = '1') then
210 -- calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
212 -- calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
215 -- if (wb_reg.byte_s = '1') then
216 -- calc_mem_res <= (others => '0');
217 -- case wb_reg.address(1 downto 0) is
218 -- when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
219 -- when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
220 -- when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
221 -- when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
222 -- when others => null;
227 --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
228 jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
230 if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
231 jump_addr <= data_ram_read;
236 -- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
240 -- if ((alu_jmp and wb_reg.dmem_en) = '1') then
241 -- jump_addr <= data_ram_read;
246 -- result : in gp_register_t; --reg (alu result or jumpaddr)
247 -- result_addr : in gp_addr_t; --reg
248 -- address : in word_t; --ureg
249 -- alu_jmp : in std_logic; --reg
250 -- br_pred : in std_logic; --reg
251 -- write_en : in std_logic; --reg (register file)
252 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
253 -- dmem_write_en : in std_logic; --ureg
254 -- hword : in std_logic --ureg
258 out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result, hword, byte_s)
259 variable reg_we_v : std_logic;
260 variable data_out : gp_register_t;
262 reg_we_v := (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
263 reg_addr <= result_addr;
265 data_addr <= (others => '0');
268 if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
269 data_out := data_ram_read;
271 reg_we_v := reg_we_v and ext_anysel;
272 data_out := data_ram_read_ext;
275 if wb_reg.byte_en(0) = '0' then
276 data_out(byte_t'range) := (others => '0');
278 if wb_reg.byte_en(1) = '0' then
279 data_out(2*byte_t'length-1 downto byte_t'length) := (others => '0');
281 if wb_reg.byte_en(2) = '0' then
282 data_out(3*byte_t'length-1 downto 2*byte_t'length) := (others => '0');
284 if wb_reg.byte_en(3) = '0' then
285 data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
289 -- if wb_reg.hword = '1' or wb_reg.byte_s = '1' then
290 -- if wb_reg.address(1)='1' then
291 -- data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2));
293 -- data_out(data_out'high downto (data_out'length/2)) := (others => '0');
294 -- if byte_s = '1' then
295 -- if wb_reg.address(0) = '1' then
296 -- data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2));
298 -- data_out(hword_t'high downto (hword_t'length/2)) := (others => '0');
303 data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
305 if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
306 data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
307 dmem_we <= wb_reg_nxt.dmem_write_en;
310 regfile_val <= data_out;
312 if wb_reg.dmem_en = '0' then
313 regfile_val <= result;
321 addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out)
322 variable wr_en, enable : std_logic; -- these are all registered
323 variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them
324 variable addr : ext_addr_t; -- for example the data memory, because it already has input registers
325 variable addrid : std_logic_vector(27 downto 0);--ext_addrid_t;
326 variable data : gp_register_t;
329 --if selecting enable is too slow, see alu_b
330 enable := wb_reg.dmem_en;
331 wr_en := wb_reg.dmem_write_en;
332 byte_en := wb_reg.byte_en;
333 addr := wb_reg.address(gp_register_t'high downto BYTEADDR);
334 addrid := wb_reg.address(gp_register_t'high downto EXTWORDS);
344 ext_uart.wr_en <= wr_en;
345 ext_7seg.wr_en <= wr_en;
346 ext_timer.wr_en <= wr_en;
347 ext_gpmp.wr_en <= wr_en;
348 ext_int.wr_en <= wr_en;
349 ext_imp.wr_en <= wr_en;
351 ext_uart.byte_en <= byte_en;
352 ext_7seg.byte_en <= byte_en;
353 ext_timer.byte_en <= byte_en;
354 ext_gpmp.byte_en <= byte_en;
355 ext_int.byte_en <= byte_en;
356 ext_imp.byte_en <= byte_en;
358 ext_uart.addr <= addr;
359 ext_7seg.addr <= addr;
360 ext_timer.addr <= addr;
361 ext_gpmp.addr <= addr;
362 ext_int.addr <= addr;
363 ext_imp.addr <= addr;
365 ext_uart.data <= data;
366 ext_7seg.data <= data;
367 ext_timer.data <= data;
368 ext_gpmp.data <= data;
369 ext_int.data <= data;
370 ext_imp.data <= data;
372 -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
374 when EXT_UART_ADDR =>
375 ext_uart.sel <= enable;
376 ext_anysel <= enable;
378 -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
379 -- ext_uart.data <= ram_data;
380 -- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
381 -- case wb_reg_nxt.address(1 downto 0) is
382 -- when "00" => ext_uart.byte_en <= "0001";
383 -- when "01" => ext_uart.byte_en <= "0010";
384 -- when "10" => ext_uart.byte_en <= "0100";
385 -- --when "11" => ext_uart.byte_en <= "1000";
386 -- when "11" => ext_uart.byte_en <= "1111";
387 -- when others => null;
390 ext_imp.sel <= enable;
391 ext_anysel <= enable;
393 -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
394 -- ext_uart.data <= ram_data;
395 -- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
396 -- case wb_reg_nxt.address(1 downto 0) is
397 -- when "00" => ext_uart.byte_en <= "0001";
398 -- when "01" => ext_uart.byte_en <= "0010";
399 -- when "10" => ext_uart.byte_en <= "0100";
400 -- --when "11" => ext_uart.byte_en <= "1000";
401 -- when "11" => ext_uart.byte_en <= "1111";
402 -- when others => null;
406 ext_int.sel <= enable;
407 ext_anysel <= enable;
409 -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
410 -- ext_uart.data <= ram_data;
411 -- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
412 -- case wb_reg_nxt.address(1 downto 0) is
413 -- when "00" => ext_uart.byte_en <= "0001";
414 -- when "01" => ext_uart.byte_en <= "0010";
415 -- when "10" => ext_uart.byte_en <= "0100";
416 -- --when "11" => ext_uart.byte_en <= "1000";
417 -- when "11" => ext_uart.byte_en <= "1111";
418 -- when others => null;
421 when EXT_7SEG_ADDR =>
422 ext_7seg.sel <= enable;
423 ext_anysel <= enable;
425 -- ext_7seg.wr_en <= wb_regdmem_write_en;
426 -- ext_7seg.data <= ram_data;
427 -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
428 -- ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
431 -- case wb_reg_nxt.address(1 downto 0) is
432 -- when "00" => ext_7seg.byte_en <= "0001";
433 -- when "01" => ext_7seg.byte_en <= "0010";
434 -- when "10" => ext_7seg.byte_en <= "0100";
435 -- when "11" => ext_7seg.byte_en <= "1000";
436 -- when others => null;
439 when EXT_TIMER_ADDR =>
440 ext_timer.sel <= enable;
441 ext_anysel <= enable;
442 -- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
443 -- ext_timer.data <= ram_data;
444 -- ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
445 -- case wb_reg.address(1 downto 0) is
446 -- when "00" => ext_timer.byte_en <= "0001";
447 -- when "01" => ext_timer.byte_en <= "0010";
448 -- when "10" => ext_timer.byte_en <= "0100";
449 -- when "11" => ext_timer.byte_en <= "1000";
450 -- when others => null;
452 when EXT_GPMP_ADDR =>
453 ext_gpmp.sel <= enable;
454 ext_anysel <= enable;
455 -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
456 -- ext_gpmp.data <= ram_data;
457 -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
458 -- case wb_reg.address(1 downto 0) is
459 -- when "00" => ext_gpmp.byte_en <= "0001";
460 -- when "01" => ext_gpmp.byte_en <= "0010";
461 -- when "10" => ext_gpmp.byte_en <= "0100";
462 -- when "11" => ext_gpmp.byte_en <= "1000";
463 -- when others => null;
465 -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert
466 when others => ext_anysel <= '0';
469 data_ram_read_ext <= ext_uart_out or ext_gpmp_out or ext_timer_out;