2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
11 use work.extension_7seg_pkg.all;
13 architecture behav of writeback_stage is
15 signal data_ram_read, data_ram_read_ext : word_t;
16 signal data_addr : word_t;
18 signal wb_reg, wb_reg_nxt : writeback_rec;
20 signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec;
21 signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
23 signal sel_nxt, dmem_we, bus_rx, ext_anysel : std_logic;
25 signal calc_mem_res : gp_register_t;
29 ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
30 ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
40 data_addr(DATA_ADDR_WIDTH+1 downto 2),
41 data_addr(DATA_ADDR_WIDTH+1 downto 2),
74 syn: process(clk, reset)
78 if (reset = RESET_VALUE) then
79 wb_reg.address <= (others => '0');
80 wb_reg.dmem_en <= '0';
81 wb_reg.dmem_write_en <= '0';
86 wb_reg.byte_en <= (others => '0');
87 wb_reg.data <= (others =>'0');
88 elsif rising_edge(clk) then
95 -- type writeback_rec is record
96 -- address : in word_t; --ureg
97 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
98 -- dmem_write_en : in std_logic; --ureg
99 -- hword_hl : in std_logic --ureg
104 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data)
105 variable byte_en : byte_en_t;
106 variable address_val : std_logic_vector(1 downto 0);
108 wb_reg_nxt.address <= address;
109 wb_reg_nxt.dmem_en <= dmem_en;
110 wb_reg_nxt.dmem_write_en <= dmem_write_en;
111 wb_reg_nxt.hword <= hword;
112 wb_reg_nxt.byte_s <= byte_s;
114 calc_mem_res <= result; --(others => '0');
116 wb_reg_nxt.data <= ram_data;
117 byte_en := (others => '0');
118 address_val := address(BYTEADDR-1 downto 0);
119 if dmem_en = '1' then
121 -- case address(BYTEADDR-1 downto 0) is
123 when "00" => byte_en(1 downto 0) := "11";
124 when "10" => byte_en(3 downto 2) := "11";
127 elsif byte_s = '1' then
128 -- case address(BYTEADDR-1 downto 0) is
130 when "00" => byte_en(0) := '1';
131 when "01" => byte_en(1) := '1';
132 when "10" => byte_en(2) := '1';
133 when "11" => byte_en(3) := '1';
137 byte_en := (others => '1');
140 wb_reg_nxt.byte_en <= byte_en;
142 -- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
143 -- calc_mem_res <= data_ram_read;
144 -- if (wb_reg.hword = '1') then
145 -- calc_mem_res <= (others => '0');
146 -- if (wb_reg.address(1) = '1') then
147 -- calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
149 -- calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
152 -- if (wb_reg.byte_s = '1') then
153 -- calc_mem_res <= (others => '0');
154 -- case wb_reg.address(1 downto 0) is
155 -- when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
156 -- when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
157 -- when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
158 -- when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
159 -- when others => null;
164 --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
165 jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
167 if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
168 jump_addr <= data_ram_read;
173 -- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
177 -- if ((alu_jmp and wb_reg.dmem_en) = '1') then
178 -- jump_addr <= data_ram_read;
183 -- result : in gp_register_t; --reg (alu result or jumpaddr)
184 -- result_addr : in gp_addr_t; --reg
185 -- address : in word_t; --ureg
186 -- alu_jmp : in std_logic; --reg
187 -- br_pred : in std_logic; --reg
188 -- write_en : in std_logic; --reg (register file)
189 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
190 -- dmem_write_en : in std_logic; --ureg
191 -- hword : in std_logic --ureg
195 out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result)
196 variable reg_we_v : std_logic;
197 variable data_out : gp_register_t;
199 reg_we_v := (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
200 reg_addr <= result_addr;
202 data_addr <= (others => '0');
205 if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
206 data_out := data_ram_read;
208 reg_we_v := reg_we_v and ext_anysel;
209 data_out := data_ram_read_ext;
212 if wb_reg.byte_en(0) = '0' then
213 data_out(byte_t'range) := (others => '0');
215 if wb_reg.byte_en(1) = '0' then
216 data_out(2*byte_t'length-1 downto byte_t'length) := (others => '0');
218 if wb_reg.byte_en(2) = '0' then
219 data_out(3*byte_t'length-1 downto 2*byte_t'length) := (others => '0');
221 if wb_reg.byte_en(3) = '0' then
222 data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
225 data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
227 if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
228 data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
229 dmem_we <= wb_reg_nxt.dmem_write_en;
232 regfile_val <= data_out;
234 if wb_reg.dmem_en = '0' then
235 regfile_val <= result;
243 addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out)
244 variable wr_en, enable : std_logic; -- these are all registered
245 variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them
246 variable addr : ext_addr_t; -- for example the data memory, because it already has input registers
247 variable addrid : std_logic_vector(27 downto 0);--ext_addrid_t;
248 variable data : gp_register_t;
251 --if selecting enable is too slow, see alu_b
252 enable := wb_reg.dmem_en;
253 wr_en := wb_reg.dmem_write_en;
254 byte_en := wb_reg.byte_en;
255 addr := wb_reg.address(gp_register_t'high downto BYTEADDR);
256 addrid := wb_reg.address(gp_register_t'high downto EXTWORDS);
264 ext_uart.wr_en <= wr_en;
265 ext_7seg.wr_en <= wr_en;
266 ext_timer.wr_en <= wr_en;
267 ext_gpmp.wr_en <= wr_en;
269 ext_uart.byte_en <= byte_en;
270 ext_7seg.byte_en <= byte_en;
271 ext_timer.byte_en <= byte_en;
272 ext_gpmp.byte_en <= byte_en;
274 ext_uart.addr <= addr;
275 ext_7seg.addr <= addr;
276 ext_timer.addr <= addr;
277 ext_gpmp.addr <= addr;
279 ext_uart.data <= data;
280 ext_7seg.data <= data;
281 ext_timer.data <= data;
282 ext_gpmp.data <= data;
283 -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
285 when EXT_UART_ADDR =>
286 ext_uart.sel <= enable;
287 ext_anysel <= enable;
288 -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
289 -- ext_uart.data <= ram_data;
290 -- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
291 -- case wb_reg_nxt.address(1 downto 0) is
292 -- when "00" => ext_uart.byte_en <= "0001";
293 -- when "01" => ext_uart.byte_en <= "0010";
294 -- when "10" => ext_uart.byte_en <= "0100";
295 -- --when "11" => ext_uart.byte_en <= "1000";
296 -- when "11" => ext_uart.byte_en <= "1111";
297 -- when others => null;
300 when EXT_7SEG_ADDR =>
301 ext_7seg.sel <= enable;
302 ext_anysel <= enable;
303 -- ext_7seg.wr_en <= wb_regdmem_write_en;
304 -- ext_7seg.data <= ram_data;
305 -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
306 -- ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
309 -- case wb_reg_nxt.address(1 downto 0) is
310 -- when "00" => ext_7seg.byte_en <= "0001";
311 -- when "01" => ext_7seg.byte_en <= "0010";
312 -- when "10" => ext_7seg.byte_en <= "0100";
313 -- when "11" => ext_7seg.byte_en <= "1000";
314 -- when others => null;
317 when EXT_TIMER_ADDR =>
318 ext_timer.sel <= enable;
319 ext_anysel <= enable;
320 -- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
321 -- ext_timer.data <= ram_data;
322 -- ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
323 -- case wb_reg.address(1 downto 0) is
324 -- when "00" => ext_timer.byte_en <= "0001";
325 -- when "01" => ext_timer.byte_en <= "0010";
326 -- when "10" => ext_timer.byte_en <= "0100";
327 -- when "11" => ext_timer.byte_en <= "1000";
328 -- when others => null;
330 when EXT_GPMP_ADDR =>
331 ext_gpmp.sel <= enable;
332 ext_anysel <= enable;
333 -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
334 -- ext_gpmp.data <= ram_data;
335 -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
336 -- case wb_reg.address(1 downto 0) is
337 -- when "00" => ext_gpmp.byte_en <= "0001";
338 -- when "01" => ext_gpmp.byte_en <= "0010";
339 -- when "10" => ext_gpmp.byte_en <= "0100";
340 -- when "11" => ext_gpmp.byte_en <= "1000";
341 -- when others => null;
343 -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert
344 when others => ext_anysel <= '0';
347 data_ram_read_ext <= ext_uart_out or ext_gpmp_out or ext_timer_out;